1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __MB862XX_H__
3*4882a593Smuzhiyun #define __MB862XX_H__
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun struct mb862xx_l1_cfg {
6*4882a593Smuzhiyun unsigned short sx;
7*4882a593Smuzhiyun unsigned short sy;
8*4882a593Smuzhiyun unsigned short sw;
9*4882a593Smuzhiyun unsigned short sh;
10*4882a593Smuzhiyun unsigned short dx;
11*4882a593Smuzhiyun unsigned short dy;
12*4882a593Smuzhiyun unsigned short dw;
13*4882a593Smuzhiyun unsigned short dh;
14*4882a593Smuzhiyun int mirror;
15*4882a593Smuzhiyun };
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define MB862XX_BASE 'M'
18*4882a593Smuzhiyun #define MB862XX_L1_GET_CFG _IOR(MB862XX_BASE, 0, struct mb862xx_l1_cfg*)
19*4882a593Smuzhiyun #define MB862XX_L1_SET_CFG _IOW(MB862XX_BASE, 1, struct mb862xx_l1_cfg*)
20*4882a593Smuzhiyun #define MB862XX_L1_ENABLE _IOW(MB862XX_BASE, 2, int)
21*4882a593Smuzhiyun #define MB862XX_L1_CAP_CTL _IOW(MB862XX_BASE, 3, int)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #ifdef __KERNEL__
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf
26*4882a593Smuzhiyun #define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019
27*4882a593Smuzhiyun #define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e
28*4882a593Smuzhiyun #define PCI_DEVICE_ID_FUJITSU_CARMINE 0x202b
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define GC_MMR_CORALP_EVB_VAL 0x11d7fa13
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun enum gdctype {
33*4882a593Smuzhiyun BT_NONE,
34*4882a593Smuzhiyun BT_LIME,
35*4882a593Smuzhiyun BT_MINT,
36*4882a593Smuzhiyun BT_CORAL,
37*4882a593Smuzhiyun BT_CORALP,
38*4882a593Smuzhiyun BT_CARMINE,
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct mb862xx_gc_mode {
42*4882a593Smuzhiyun struct fb_videomode def_mode; /* mode of connected display */
43*4882a593Smuzhiyun unsigned int def_bpp; /* default depth */
44*4882a593Smuzhiyun unsigned long max_vram; /* connected SDRAM size */
45*4882a593Smuzhiyun unsigned long ccf; /* gdc clk */
46*4882a593Smuzhiyun unsigned long mmr; /* memory mode for SDRAM */
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* private data */
50*4882a593Smuzhiyun struct mb862xxfb_par {
51*4882a593Smuzhiyun struct fb_info *info; /* fb info head */
52*4882a593Smuzhiyun struct device *dev;
53*4882a593Smuzhiyun struct pci_dev *pdev;
54*4882a593Smuzhiyun struct resource *res; /* framebuffer/mmio resource */
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun resource_size_t fb_base_phys; /* fb base, 36-bit PPC440EPx */
57*4882a593Smuzhiyun resource_size_t mmio_base_phys; /* io base addr */
58*4882a593Smuzhiyun void __iomem *fb_base; /* remapped framebuffer */
59*4882a593Smuzhiyun void __iomem *mmio_base; /* remapped registers */
60*4882a593Smuzhiyun size_t mapped_vram; /* length of remapped vram */
61*4882a593Smuzhiyun size_t mmio_len; /* length of register region */
62*4882a593Smuzhiyun unsigned long cap_buf; /* capture buffers offset */
63*4882a593Smuzhiyun size_t cap_len; /* length of capture buffers */
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun void __iomem *host; /* relocatable reg. bases */
66*4882a593Smuzhiyun void __iomem *i2c;
67*4882a593Smuzhiyun void __iomem *disp;
68*4882a593Smuzhiyun void __iomem *disp1;
69*4882a593Smuzhiyun void __iomem *cap;
70*4882a593Smuzhiyun void __iomem *cap1;
71*4882a593Smuzhiyun void __iomem *draw;
72*4882a593Smuzhiyun void __iomem *geo;
73*4882a593Smuzhiyun void __iomem *pio;
74*4882a593Smuzhiyun void __iomem *ctrl;
75*4882a593Smuzhiyun void __iomem *dram_ctrl;
76*4882a593Smuzhiyun void __iomem *wrback;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun unsigned int irq;
79*4882a593Smuzhiyun unsigned int type; /* GDC type */
80*4882a593Smuzhiyun unsigned int refclk; /* disp. reference clock */
81*4882a593Smuzhiyun struct mb862xx_gc_mode *gc_mode; /* GDC mode init data */
82*4882a593Smuzhiyun int pre_init; /* don't init display if 1 */
83*4882a593Smuzhiyun struct i2c_adapter *adap; /* GDC I2C bus adapter */
84*4882a593Smuzhiyun int i2c_rs;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun struct mb862xx_l1_cfg l1_cfg;
87*4882a593Smuzhiyun int l1_stride;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun u32 pseudo_palette[16];
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun extern void mb862xxfb_init_accel(struct fb_info *info, struct fb_ops *fbops, int xres);
93*4882a593Smuzhiyun #ifdef CONFIG_FB_MB862XX_I2C
94*4882a593Smuzhiyun extern int mb862xx_i2c_init(struct mb862xxfb_par *par);
95*4882a593Smuzhiyun extern void mb862xx_i2c_exit(struct mb862xxfb_par *par);
96*4882a593Smuzhiyun #else
mb862xx_i2c_init(struct mb862xxfb_par * par)97*4882a593Smuzhiyun static inline int mb862xx_i2c_init(struct mb862xxfb_par *par) { return 0; }
mb862xx_i2c_exit(struct mb862xxfb_par * par)98*4882a593Smuzhiyun static inline void mb862xx_i2c_exit(struct mb862xxfb_par *par) { }
99*4882a593Smuzhiyun #endif
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC)
102*4882a593Smuzhiyun #error "Select Lime GDC or CoralP/Carmine support, but not both together"
103*4882a593Smuzhiyun #endif
104*4882a593Smuzhiyun #if defined(CONFIG_FB_MB862XX_LIME)
105*4882a593Smuzhiyun #define gdc_read __raw_readl
106*4882a593Smuzhiyun #define gdc_write __raw_writel
107*4882a593Smuzhiyun #else
108*4882a593Smuzhiyun #define gdc_read readl
109*4882a593Smuzhiyun #define gdc_write writel
110*4882a593Smuzhiyun #endif
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun #define inreg(type, off) \
113*4882a593Smuzhiyun gdc_read((par->type + (off)))
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #define outreg(type, off, val) \
116*4882a593Smuzhiyun gdc_write((val), (par->type + (off)))
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #define pack(a, b) (((a) << 16) | (b))
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun #endif /* __KERNEL__ */
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #endif
123