1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __MATROXFB_DAC1064_H__ 3*4882a593Smuzhiyun #define __MATROXFB_DAC1064_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #include "matroxfb_base.h" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifdef CONFIG_FB_MATROX_MYSTIQUE 9*4882a593Smuzhiyun extern struct matrox_switch matrox_mystique; 10*4882a593Smuzhiyun #endif 11*4882a593Smuzhiyun #ifdef CONFIG_FB_MATROX_G 12*4882a593Smuzhiyun extern struct matrox_switch matrox_G100; 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun #ifdef NEED_DAC1064 15*4882a593Smuzhiyun void DAC1064_global_init(struct matrox_fb_info *minfo); 16*4882a593Smuzhiyun void DAC1064_global_restore(struct matrox_fb_info *minfo); 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define M1064_INDEX 0x00 20*4882a593Smuzhiyun #define M1064_PALWRADD 0x00 21*4882a593Smuzhiyun #define M1064_PALDATA 0x01 22*4882a593Smuzhiyun #define M1064_PIXRDMSK 0x02 23*4882a593Smuzhiyun #define M1064_PALRDADD 0x03 24*4882a593Smuzhiyun #define M1064_X_DATAREG 0x0A 25*4882a593Smuzhiyun #define M1064_CURPOSXL 0x0C /* can be accessed as DWORD */ 26*4882a593Smuzhiyun #define M1064_CURPOSXH 0x0D 27*4882a593Smuzhiyun #define M1064_CURPOSYL 0x0E 28*4882a593Smuzhiyun #define M1064_CURPOSYH 0x0F 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define M1064_XCURADDL 0x04 31*4882a593Smuzhiyun #define M1064_XCURADDH 0x05 32*4882a593Smuzhiyun #define M1064_XCURCTRL 0x06 33*4882a593Smuzhiyun #define M1064_XCURCTRL_DIS 0x00 /* transparent, transparent, transparent, transparent */ 34*4882a593Smuzhiyun #define M1064_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */ 35*4882a593Smuzhiyun #define M1064_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */ 36*4882a593Smuzhiyun #define M1064_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */ 37*4882a593Smuzhiyun /* drive DVI by standard(0)/DVI(1) PLL */ 38*4882a593Smuzhiyun /* if set(1), C?DVICLKEN and C?DVICLKSEL must be set(1) */ 39*4882a593Smuzhiyun #define M1064_XDVICLKCTRL_DVIDATAPATHSEL 0x01 40*4882a593Smuzhiyun /* drive CRTC1 by standard(0)/DVI(1) PLL */ 41*4882a593Smuzhiyun #define M1064_XDVICLKCTRL_C1DVICLKSEL 0x02 42*4882a593Smuzhiyun /* drive CRTC2 by standard(0)/DVI(1) PLL */ 43*4882a593Smuzhiyun #define M1064_XDVICLKCTRL_C2DVICLKSEL 0x04 44*4882a593Smuzhiyun /* pixel clock allowed to(0)/blocked from(1) driving CRTC1 */ 45*4882a593Smuzhiyun #define M1064_XDVICLKCTRL_C1DVICLKEN 0x08 46*4882a593Smuzhiyun /* DVI PLL loop filter bandwidth selection bits */ 47*4882a593Smuzhiyun #define M1064_XDVICLKCTRL_DVILOOPCTL 0x30 48*4882a593Smuzhiyun /* CRTC2 pixel clock allowed to(0)/blocked from(1) driving CRTC2 */ 49*4882a593Smuzhiyun #define M1064_XDVICLKCTRL_C2DVICLKEN 0x40 50*4882a593Smuzhiyun /* P1PLL loop filter bandwidth selection */ 51*4882a593Smuzhiyun #define M1064_XDVICLKCTRL_P1LOOPBWDTCTL 0x80 52*4882a593Smuzhiyun #define M1064_XCURCOL0RED 0x08 53*4882a593Smuzhiyun #define M1064_XCURCOL0GREEN 0x09 54*4882a593Smuzhiyun #define M1064_XCURCOL0BLUE 0x0A 55*4882a593Smuzhiyun #define M1064_XCURCOL1RED 0x0C 56*4882a593Smuzhiyun #define M1064_XCURCOL1GREEN 0x0D 57*4882a593Smuzhiyun #define M1064_XCURCOL1BLUE 0x0E 58*4882a593Smuzhiyun #define M1064_XDVICLKCTRL 0x0F 59*4882a593Smuzhiyun #define M1064_XCURCOL2RED 0x10 60*4882a593Smuzhiyun #define M1064_XCURCOL2GREEN 0x11 61*4882a593Smuzhiyun #define M1064_XCURCOL2BLUE 0x12 62*4882a593Smuzhiyun #define DAC1064_XVREFCTRL 0x18 63*4882a593Smuzhiyun #define DAC1064_XVREFCTRL_INTERNAL 0x3F 64*4882a593Smuzhiyun #define DAC1064_XVREFCTRL_EXTERNAL 0x00 65*4882a593Smuzhiyun #define DAC1064_XVREFCTRL_G100_DEFAULT 0x03 66*4882a593Smuzhiyun #define M1064_XMULCTRL 0x19 67*4882a593Smuzhiyun #define M1064_XMULCTRL_DEPTH_8BPP 0x00 /* 8 bpp paletized */ 68*4882a593Smuzhiyun #define M1064_XMULCTRL_DEPTH_15BPP_1BPP 0x01 /* 15 bpp paletized + 1 bpp overlay */ 69*4882a593Smuzhiyun #define M1064_XMULCTRL_DEPTH_16BPP 0x02 /* 16 bpp paletized */ 70*4882a593Smuzhiyun #define M1064_XMULCTRL_DEPTH_24BPP 0x03 /* 24 bpp paletized */ 71*4882a593Smuzhiyun #define M1064_XMULCTRL_DEPTH_24BPP_8BPP 0x04 /* 24 bpp direct + 8 bpp overlay paletized */ 72*4882a593Smuzhiyun #define M1064_XMULCTRL_2G8V16 0x05 /* 15 bpp video direct, half xres, 8bpp paletized */ 73*4882a593Smuzhiyun #define M1064_XMULCTRL_G16V16 0x06 /* 15 bpp video, 15bpp graphics, one of them paletized */ 74*4882a593Smuzhiyun #define M1064_XMULCTRL_DEPTH_32BPP 0x07 /* 24 bpp paletized + 8 bpp unused */ 75*4882a593Smuzhiyun #define M1064_XMULCTRL_GRAPHICS_PALETIZED 0x00 76*4882a593Smuzhiyun #define M1064_XMULCTRL_VIDEO_PALETIZED 0x08 77*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL 0x1A 78*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_SRC_PCI 0x00 79*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_SRC_PLL 0x01 80*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_SRC_EXT 0x02 81*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_SRC_SYS 0x03 /* G200/G400 */ 82*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_SRC_PLL2 0x03 /* G450 */ 83*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_SRC_MASK 0x03 84*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_EN 0x00 85*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_DIS 0x04 86*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_PLL_DOWN 0x00 87*4882a593Smuzhiyun #define M1064_XPIXCLKCTRL_PLL_UP 0x08 88*4882a593Smuzhiyun #define M1064_XGENCTRL 0x1D 89*4882a593Smuzhiyun #define M1064_XGENCTRL_VS_0 0x00 90*4882a593Smuzhiyun #define M1064_XGENCTRL_VS_1 0x01 91*4882a593Smuzhiyun #define M1064_XGENCTRL_ALPHA_DIS 0x00 92*4882a593Smuzhiyun #define M1064_XGENCTRL_ALPHA_EN 0x02 93*4882a593Smuzhiyun #define M1064_XGENCTRL_BLACK_0IRE 0x00 94*4882a593Smuzhiyun #define M1064_XGENCTRL_BLACK_75IRE 0x10 95*4882a593Smuzhiyun #define M1064_XGENCTRL_SYNC_ON_GREEN 0x00 96*4882a593Smuzhiyun #define M1064_XGENCTRL_NO_SYNC_ON_GREEN 0x20 97*4882a593Smuzhiyun #define M1064_XGENCTRL_SYNC_ON_GREEN_MASK 0x20 98*4882a593Smuzhiyun #define M1064_XMISCCTRL 0x1E 99*4882a593Smuzhiyun #define M1064_XMISCCTRL_DAC_DIS 0x00 100*4882a593Smuzhiyun #define M1064_XMISCCTRL_DAC_EN 0x01 101*4882a593Smuzhiyun #define M1064_XMISCCTRL_MFC_VGA 0x00 102*4882a593Smuzhiyun #define M1064_XMISCCTRL_MFC_MAFC 0x02 103*4882a593Smuzhiyun #define M1064_XMISCCTRL_MFC_DIS 0x06 104*4882a593Smuzhiyun #define GX00_XMISCCTRL_MFC_MAFC 0x02 105*4882a593Smuzhiyun #define GX00_XMISCCTRL_MFC_PANELLINK 0x04 106*4882a593Smuzhiyun #define GX00_XMISCCTRL_MFC_DIS 0x06 107*4882a593Smuzhiyun #define GX00_XMISCCTRL_MFC_MASK 0x06 108*4882a593Smuzhiyun #define M1064_XMISCCTRL_DAC_6BIT 0x00 109*4882a593Smuzhiyun #define M1064_XMISCCTRL_DAC_8BIT 0x08 110*4882a593Smuzhiyun #define M1064_XMISCCTRL_DAC_WIDTHMASK 0x08 111*4882a593Smuzhiyun #define M1064_XMISCCTRL_LUT_DIS 0x00 112*4882a593Smuzhiyun #define M1064_XMISCCTRL_LUT_EN 0x10 113*4882a593Smuzhiyun #define G400_XMISCCTRL_VDO_MAFC12 0x00 114*4882a593Smuzhiyun #define G400_XMISCCTRL_VDO_BYPASS656 0x40 115*4882a593Smuzhiyun #define G400_XMISCCTRL_VDO_C2_MAFC12 0x80 116*4882a593Smuzhiyun #define G400_XMISCCTRL_VDO_C2_BYPASS656 0xC0 117*4882a593Smuzhiyun #define G400_XMISCCTRL_VDO_MASK 0xE0 118*4882a593Smuzhiyun #define M1064_XGENIOCTRL 0x2A 119*4882a593Smuzhiyun #define M1064_XGENIODATA 0x2B 120*4882a593Smuzhiyun #define DAC1064_XSYSPLLM 0x2C 121*4882a593Smuzhiyun #define DAC1064_XSYSPLLN 0x2D 122*4882a593Smuzhiyun #define DAC1064_XSYSPLLP 0x2E 123*4882a593Smuzhiyun #define DAC1064_XSYSPLLSTAT 0x2F 124*4882a593Smuzhiyun #define M1064_XZOOMCTRL 0x38 125*4882a593Smuzhiyun #define M1064_XZOOMCTRL_1 0x00 126*4882a593Smuzhiyun #define M1064_XZOOMCTRL_2 0x01 127*4882a593Smuzhiyun #define M1064_XZOOMCTRL_4 0x03 128*4882a593Smuzhiyun #define M1064_XSENSETEST 0x3A 129*4882a593Smuzhiyun #define M1064_XSENSETEST_BCOMP 0x01 130*4882a593Smuzhiyun #define M1064_XSENSETEST_GCOMP 0x02 131*4882a593Smuzhiyun #define M1064_XSENSETEST_RCOMP 0x04 132*4882a593Smuzhiyun #define M1064_XSENSETEST_PDOWN 0x00 133*4882a593Smuzhiyun #define M1064_XSENSETEST_PUP 0x80 134*4882a593Smuzhiyun #define M1064_XCRCREML 0x3C 135*4882a593Smuzhiyun #define M1064_XCRCREMH 0x3D 136*4882a593Smuzhiyun #define M1064_XCRCBITSEL 0x3E 137*4882a593Smuzhiyun #define M1064_XCOLKEYMASKL 0x40 138*4882a593Smuzhiyun #define M1064_XCOLKEYMASKH 0x41 139*4882a593Smuzhiyun #define M1064_XCOLKEYL 0x42 140*4882a593Smuzhiyun #define M1064_XCOLKEYH 0x43 141*4882a593Smuzhiyun #define M1064_XPIXPLLAM 0x44 142*4882a593Smuzhiyun #define M1064_XPIXPLLAN 0x45 143*4882a593Smuzhiyun #define M1064_XPIXPLLAP 0x46 144*4882a593Smuzhiyun #define M1064_XPIXPLLBM 0x48 145*4882a593Smuzhiyun #define M1064_XPIXPLLBN 0x49 146*4882a593Smuzhiyun #define M1064_XPIXPLLBP 0x4A 147*4882a593Smuzhiyun #define M1064_XPIXPLLCM 0x4C 148*4882a593Smuzhiyun #define M1064_XPIXPLLCN 0x4D 149*4882a593Smuzhiyun #define M1064_XPIXPLLCP 0x4E 150*4882a593Smuzhiyun #define M1064_XPIXPLLSTAT 0x4F 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define M1064_XTVO_IDX 0x87 153*4882a593Smuzhiyun #define M1064_XTVO_DATA 0x88 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #define M1064_XOUTPUTCONN 0x8A 156*4882a593Smuzhiyun #define M1064_XSYNCCTRL 0x8B 157*4882a593Smuzhiyun #define M1064_XVIDPLLSTAT 0x8C 158*4882a593Smuzhiyun #define M1064_XVIDPLLP 0x8D 159*4882a593Smuzhiyun #define M1064_XVIDPLLM 0x8E 160*4882a593Smuzhiyun #define M1064_XVIDPLLN 0x8F 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define M1064_XPWRCTRL 0xA0 163*4882a593Smuzhiyun #define M1064_XPWRCTRL_PANELPDN 0x04 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define M1064_XPANMODE 0xA2 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun enum POS1064 { 168*4882a593Smuzhiyun POS1064_XCURADDL=0, POS1064_XCURADDH, POS1064_XCURCTRL, 169*4882a593Smuzhiyun POS1064_XCURCOL0RED, POS1064_XCURCOL0GREEN, POS1064_XCURCOL0BLUE, 170*4882a593Smuzhiyun POS1064_XCURCOL1RED, POS1064_XCURCOL1GREEN, POS1064_XCURCOL1BLUE, 171*4882a593Smuzhiyun POS1064_XCURCOL2RED, POS1064_XCURCOL2GREEN, POS1064_XCURCOL2BLUE, 172*4882a593Smuzhiyun POS1064_XVREFCTRL, POS1064_XMULCTRL, POS1064_XPIXCLKCTRL, POS1064_XGENCTRL, 173*4882a593Smuzhiyun POS1064_XMISCCTRL, 174*4882a593Smuzhiyun POS1064_XGENIOCTRL, POS1064_XGENIODATA, POS1064_XZOOMCTRL, POS1064_XSENSETEST, 175*4882a593Smuzhiyun POS1064_XCRCBITSEL, 176*4882a593Smuzhiyun POS1064_XCOLKEYMASKL, POS1064_XCOLKEYMASKH, POS1064_XCOLKEYL, POS1064_XCOLKEYH, 177*4882a593Smuzhiyun POS1064_XOUTPUTCONN, POS1064_XPANMODE, POS1064_XPWRCTRL }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #endif /* __MATROXFB_DAC1064_H__ */ 181