1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _INTELFB_H 3*4882a593Smuzhiyun #define _INTELFB_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* $DHD: intelfb/intelfb.h,v 1.40 2003/06/27 15:06:25 dawes Exp $ */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/agp_backend.h> 8*4882a593Smuzhiyun #include <linux/fb.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifdef CONFIG_FB_INTEL_I2C 11*4882a593Smuzhiyun #include <linux/i2c.h> 12*4882a593Smuzhiyun #include <linux/i2c-algo-bit.h> 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /*** Version/name ***/ 16*4882a593Smuzhiyun #define INTELFB_VERSION "0.9.6" 17*4882a593Smuzhiyun #define INTELFB_MODULE_NAME "intelfb" 18*4882a593Smuzhiyun #define SUPPORTED_CHIPSETS "830M/845G/852GM/855GM/865G/915G/915GM/945G/945GM/945GME/965G/965GM" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /*** Debug/feature defines ***/ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef DEBUG 24*4882a593Smuzhiyun #define DEBUG 0 25*4882a593Smuzhiyun #endif 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifndef VERBOSE 28*4882a593Smuzhiyun #define VERBOSE 0 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifndef REGDUMP 32*4882a593Smuzhiyun #define REGDUMP 0 33*4882a593Smuzhiyun #endif 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef DETECT_VGA_CLASS_ONLY 36*4882a593Smuzhiyun #define DETECT_VGA_CLASS_ONLY 1 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #ifndef ALLOCATE_FOR_PANNING 40*4882a593Smuzhiyun #define ALLOCATE_FOR_PANNING 1 41*4882a593Smuzhiyun #endif 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #ifndef PREFERRED_MODE 44*4882a593Smuzhiyun #define PREFERRED_MODE "1024x768-32@70" 45*4882a593Smuzhiyun #endif 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /*** hw-related values ***/ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Resource Allocation */ 50*4882a593Smuzhiyun #define INTELFB_FB_ACQUIRED 1 51*4882a593Smuzhiyun #define INTELFB_MMIO_ACQUIRED 2 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* PCI ids for supported devices */ 54*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_830M 0x3577 55*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_845G 0x2562 56*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_85XGM 0x3582 57*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_854 0x358E 58*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_865G 0x2572 59*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_915G 0x2582 60*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_915GM 0x2592 61*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_945G 0x2772 62*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_945GM 0x27A2 63*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_945GME 0x27AE 64*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_965G 0x29A2 65*4882a593Smuzhiyun #define PCI_DEVICE_ID_INTEL_965GM 0x2A02 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Size of MMIO region */ 68*4882a593Smuzhiyun #define INTEL_REG_SIZE 0x80000 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define STRIDE_ALIGNMENT 16 71*4882a593Smuzhiyun #define STRIDE_ALIGNMENT_I9XX 64 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define PALETTE_8_ENTRIES 256 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /*** Macros ***/ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* basic arithmetic */ 79*4882a593Smuzhiyun #define KB(x) ((x) * 1024) 80*4882a593Smuzhiyun #define MB(x) ((x) * 1024 * 1024) 81*4882a593Smuzhiyun #define BtoKB(x) ((x) / 1024) 82*4882a593Smuzhiyun #define BtoMB(x) ((x) / 1024 / 1024) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define GTT_PAGE_SIZE KB(4) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) 87*4882a593Smuzhiyun #define ROUND_DOWN_TO(x, y) ((x) / (y) * (y)) 88*4882a593Smuzhiyun #define ROUND_UP_TO_PAGE(x) ROUND_UP_TO((x), GTT_PAGE_SIZE) 89*4882a593Smuzhiyun #define ROUND_DOWN_TO_PAGE(x) ROUND_DOWN_TO((x), GTT_PAGE_SIZE) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* messages */ 92*4882a593Smuzhiyun #define PFX INTELFB_MODULE_NAME ": " 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define ERR_MSG(fmt, args...) printk(KERN_ERR PFX fmt, ## args) 95*4882a593Smuzhiyun #define WRN_MSG(fmt, args...) printk(KERN_WARNING PFX fmt, ## args) 96*4882a593Smuzhiyun #define NOT_MSG(fmt, args...) printk(KERN_NOTICE PFX fmt, ## args) 97*4882a593Smuzhiyun #define INF_MSG(fmt, args...) printk(KERN_INFO PFX fmt, ## args) 98*4882a593Smuzhiyun #if DEBUG 99*4882a593Smuzhiyun #define DBG_MSG(fmt, args...) printk(KERN_DEBUG PFX fmt, ## args) 100*4882a593Smuzhiyun #else 101*4882a593Smuzhiyun #define DBG_MSG(fmt, args...) while (0) printk(fmt, ## args) 102*4882a593Smuzhiyun #endif 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* get commonly used pointers */ 105*4882a593Smuzhiyun #define GET_DINFO(info) (info)->par 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* misc macros */ 108*4882a593Smuzhiyun #define ACCEL(d, i) \ 109*4882a593Smuzhiyun ((d)->accel && !(d)->ring_lockup && \ 110*4882a593Smuzhiyun ((i)->var.accel_flags & FB_ACCELF_TEXT)) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /*#define NOACCEL_CHIPSET(d) \ 113*4882a593Smuzhiyun ((d)->chipset != INTEL_865G)*/ 114*4882a593Smuzhiyun #define NOACCEL_CHIPSET(d) \ 115*4882a593Smuzhiyun (0) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define FIXED_MODE(d) ((d)->fixed_mode) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /*** Driver parameters ***/ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define RINGBUFFER_SIZE KB(64) 122*4882a593Smuzhiyun #define HW_CURSOR_SIZE KB(4) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* Intel agpgart driver */ 125*4882a593Smuzhiyun #define AGP_PHYSICAL_MEMORY 2 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* store information about an Ixxx DVO */ 128*4882a593Smuzhiyun /* The i830->i865 use multiple DVOs with multiple i2cs */ 129*4882a593Smuzhiyun /* the i915, i945 have a single sDVO i2c bus - which is different */ 130*4882a593Smuzhiyun #define MAX_OUTPUTS 6 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* these are outputs from the chip - integrated only 133*4882a593Smuzhiyun external chips are via DVO or SDVO output */ 134*4882a593Smuzhiyun #define INTELFB_OUTPUT_UNUSED 0 135*4882a593Smuzhiyun #define INTELFB_OUTPUT_ANALOG 1 136*4882a593Smuzhiyun #define INTELFB_OUTPUT_DVO 2 137*4882a593Smuzhiyun #define INTELFB_OUTPUT_SDVO 3 138*4882a593Smuzhiyun #define INTELFB_OUTPUT_LVDS 4 139*4882a593Smuzhiyun #define INTELFB_OUTPUT_TVOUT 5 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define INTELFB_DVO_CHIP_NONE 0 142*4882a593Smuzhiyun #define INTELFB_DVO_CHIP_LVDS 1 143*4882a593Smuzhiyun #define INTELFB_DVO_CHIP_TMDS 2 144*4882a593Smuzhiyun #define INTELFB_DVO_CHIP_TVOUT 4 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define INTELFB_OUTPUT_PIPE_NC 0 147*4882a593Smuzhiyun #define INTELFB_OUTPUT_PIPE_A 1 148*4882a593Smuzhiyun #define INTELFB_OUTPUT_PIPE_B 2 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /*** Data Types ***/ 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* supported chipsets */ 153*4882a593Smuzhiyun enum intel_chips { 154*4882a593Smuzhiyun INTEL_830M, 155*4882a593Smuzhiyun INTEL_845G, 156*4882a593Smuzhiyun INTEL_85XGM, 157*4882a593Smuzhiyun INTEL_852GM, 158*4882a593Smuzhiyun INTEL_852GME, 159*4882a593Smuzhiyun INTEL_854, 160*4882a593Smuzhiyun INTEL_855GM, 161*4882a593Smuzhiyun INTEL_855GME, 162*4882a593Smuzhiyun INTEL_865G, 163*4882a593Smuzhiyun INTEL_915G, 164*4882a593Smuzhiyun INTEL_915GM, 165*4882a593Smuzhiyun INTEL_945G, 166*4882a593Smuzhiyun INTEL_945GM, 167*4882a593Smuzhiyun INTEL_945GME, 168*4882a593Smuzhiyun INTEL_965G, 169*4882a593Smuzhiyun INTEL_965GM, 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun struct intelfb_hwstate { 173*4882a593Smuzhiyun u32 vga0_divisor; 174*4882a593Smuzhiyun u32 vga1_divisor; 175*4882a593Smuzhiyun u32 vga_pd; 176*4882a593Smuzhiyun u32 dpll_a; 177*4882a593Smuzhiyun u32 dpll_b; 178*4882a593Smuzhiyun u32 fpa0; 179*4882a593Smuzhiyun u32 fpa1; 180*4882a593Smuzhiyun u32 fpb0; 181*4882a593Smuzhiyun u32 fpb1; 182*4882a593Smuzhiyun u32 palette_a[PALETTE_8_ENTRIES]; 183*4882a593Smuzhiyun u32 palette_b[PALETTE_8_ENTRIES]; 184*4882a593Smuzhiyun u32 htotal_a; 185*4882a593Smuzhiyun u32 hblank_a; 186*4882a593Smuzhiyun u32 hsync_a; 187*4882a593Smuzhiyun u32 vtotal_a; 188*4882a593Smuzhiyun u32 vblank_a; 189*4882a593Smuzhiyun u32 vsync_a; 190*4882a593Smuzhiyun u32 src_size_a; 191*4882a593Smuzhiyun u32 bclrpat_a; 192*4882a593Smuzhiyun u32 htotal_b; 193*4882a593Smuzhiyun u32 hblank_b; 194*4882a593Smuzhiyun u32 hsync_b; 195*4882a593Smuzhiyun u32 vtotal_b; 196*4882a593Smuzhiyun u32 vblank_b; 197*4882a593Smuzhiyun u32 vsync_b; 198*4882a593Smuzhiyun u32 src_size_b; 199*4882a593Smuzhiyun u32 bclrpat_b; 200*4882a593Smuzhiyun u32 adpa; 201*4882a593Smuzhiyun u32 dvoa; 202*4882a593Smuzhiyun u32 dvob; 203*4882a593Smuzhiyun u32 dvoc; 204*4882a593Smuzhiyun u32 dvoa_srcdim; 205*4882a593Smuzhiyun u32 dvob_srcdim; 206*4882a593Smuzhiyun u32 dvoc_srcdim; 207*4882a593Smuzhiyun u32 lvds; 208*4882a593Smuzhiyun u32 pipe_a_conf; 209*4882a593Smuzhiyun u32 pipe_b_conf; 210*4882a593Smuzhiyun u32 disp_arb; 211*4882a593Smuzhiyun u32 cursor_a_control; 212*4882a593Smuzhiyun u32 cursor_b_control; 213*4882a593Smuzhiyun u32 cursor_a_base; 214*4882a593Smuzhiyun u32 cursor_b_base; 215*4882a593Smuzhiyun u32 cursor_size; 216*4882a593Smuzhiyun u32 disp_a_ctrl; 217*4882a593Smuzhiyun u32 disp_b_ctrl; 218*4882a593Smuzhiyun u32 disp_a_base; 219*4882a593Smuzhiyun u32 disp_b_base; 220*4882a593Smuzhiyun u32 cursor_a_palette[4]; 221*4882a593Smuzhiyun u32 cursor_b_palette[4]; 222*4882a593Smuzhiyun u32 disp_a_stride; 223*4882a593Smuzhiyun u32 disp_b_stride; 224*4882a593Smuzhiyun u32 vgacntrl; 225*4882a593Smuzhiyun u32 add_id; 226*4882a593Smuzhiyun u32 swf0x[7]; 227*4882a593Smuzhiyun u32 swf1x[7]; 228*4882a593Smuzhiyun u32 swf3x[3]; 229*4882a593Smuzhiyun u32 fence[8]; 230*4882a593Smuzhiyun u32 instpm; 231*4882a593Smuzhiyun u32 mem_mode; 232*4882a593Smuzhiyun u32 fw_blc_0; 233*4882a593Smuzhiyun u32 fw_blc_1; 234*4882a593Smuzhiyun u16 hwstam; 235*4882a593Smuzhiyun u16 ier; 236*4882a593Smuzhiyun u16 iir; 237*4882a593Smuzhiyun u16 imr; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun struct intelfb_heap_data { 241*4882a593Smuzhiyun u32 physical; 242*4882a593Smuzhiyun u8 __iomem *virtual; 243*4882a593Smuzhiyun u32 offset; /* in GATT pages */ 244*4882a593Smuzhiyun u32 size; /* in bytes */ 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun #ifdef CONFIG_FB_INTEL_I2C 248*4882a593Smuzhiyun struct intelfb_i2c_chan { 249*4882a593Smuzhiyun struct intelfb_info *dinfo; 250*4882a593Smuzhiyun u32 reg; 251*4882a593Smuzhiyun struct i2c_adapter adapter; 252*4882a593Smuzhiyun struct i2c_algo_bit_data algo; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun #endif 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun struct intelfb_output_rec { 257*4882a593Smuzhiyun int type; 258*4882a593Smuzhiyun int pipe; 259*4882a593Smuzhiyun int flags; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #ifdef CONFIG_FB_INTEL_I2C 262*4882a593Smuzhiyun struct intelfb_i2c_chan i2c_bus; 263*4882a593Smuzhiyun struct intelfb_i2c_chan ddc_bus; 264*4882a593Smuzhiyun #endif 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun struct intelfb_vsync { 268*4882a593Smuzhiyun wait_queue_head_t wait; 269*4882a593Smuzhiyun unsigned int count; 270*4882a593Smuzhiyun int pan_display; 271*4882a593Smuzhiyun u32 pan_offset; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun struct intelfb_info { 275*4882a593Smuzhiyun struct fb_info *info; 276*4882a593Smuzhiyun const struct fb_ops *fbops; 277*4882a593Smuzhiyun struct pci_dev *pdev; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun struct intelfb_hwstate save_state; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* agpgart structs */ 282*4882a593Smuzhiyun struct agp_memory *gtt_fb_mem; /* use all stolen memory or vram */ 283*4882a593Smuzhiyun struct agp_memory *gtt_ring_mem; /* ring buffer */ 284*4882a593Smuzhiyun struct agp_memory *gtt_cursor_mem; /* hw cursor */ 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun /* use a gart reserved fb mem */ 287*4882a593Smuzhiyun u8 fbmem_gart; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun int wc_cookie; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun /* heap data */ 292*4882a593Smuzhiyun struct intelfb_heap_data aperture; 293*4882a593Smuzhiyun struct intelfb_heap_data fb; 294*4882a593Smuzhiyun struct intelfb_heap_data ring; 295*4882a593Smuzhiyun struct intelfb_heap_data cursor; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun /* mmio regs */ 298*4882a593Smuzhiyun u32 mmio_base_phys; 299*4882a593Smuzhiyun u8 __iomem *mmio_base; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* fb start offset (in bytes) */ 302*4882a593Smuzhiyun u32 fb_start; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /* ring buffer */ 305*4882a593Smuzhiyun u32 ring_head; 306*4882a593Smuzhiyun u32 ring_tail; 307*4882a593Smuzhiyun u32 ring_tail_mask; 308*4882a593Smuzhiyun u32 ring_space; 309*4882a593Smuzhiyun u32 ring_lockup; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun /* palette */ 312*4882a593Smuzhiyun u32 pseudo_palette[16]; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* chip info */ 315*4882a593Smuzhiyun int pci_chipset; 316*4882a593Smuzhiyun int chipset; 317*4882a593Smuzhiyun const char *name; 318*4882a593Smuzhiyun int mobile; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun /* current mode */ 321*4882a593Smuzhiyun int bpp, depth; 322*4882a593Smuzhiyun u32 visual; 323*4882a593Smuzhiyun int xres, yres, pitch; 324*4882a593Smuzhiyun int pixclock; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /* current pipe */ 327*4882a593Smuzhiyun int pipe; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun /* some flags */ 330*4882a593Smuzhiyun int accel; 331*4882a593Smuzhiyun int hwcursor; 332*4882a593Smuzhiyun int fixed_mode; 333*4882a593Smuzhiyun int ring_active; 334*4882a593Smuzhiyun int flag; 335*4882a593Smuzhiyun unsigned long irq_flags; 336*4882a593Smuzhiyun int open; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun /* vsync */ 339*4882a593Smuzhiyun struct intelfb_vsync vsync; 340*4882a593Smuzhiyun spinlock_t int_lock; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun /* hw cursor */ 343*4882a593Smuzhiyun int cursor_on; 344*4882a593Smuzhiyun int cursor_blanked; 345*4882a593Smuzhiyun u8 cursor_src[64]; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun /* initial parameters */ 348*4882a593Smuzhiyun int initial_vga; 349*4882a593Smuzhiyun struct fb_var_screeninfo initial_var; 350*4882a593Smuzhiyun u32 initial_fb_base; 351*4882a593Smuzhiyun u32 initial_video_ram; 352*4882a593Smuzhiyun u32 initial_pitch; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun /* driver registered */ 355*4882a593Smuzhiyun int registered; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun /* index into plls */ 358*4882a593Smuzhiyun int pll_index; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun /* outputs */ 361*4882a593Smuzhiyun int num_outputs; 362*4882a593Smuzhiyun struct intelfb_output_rec output[MAX_OUTPUTS]; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun #define IS_I9XX(dinfo) (((dinfo)->chipset == INTEL_915G) || \ 366*4882a593Smuzhiyun ((dinfo)->chipset == INTEL_915GM) || \ 367*4882a593Smuzhiyun ((dinfo)->chipset == INTEL_945G) || \ 368*4882a593Smuzhiyun ((dinfo)->chipset == INTEL_945GM) || \ 369*4882a593Smuzhiyun ((dinfo)->chipset == INTEL_945GME) || \ 370*4882a593Smuzhiyun ((dinfo)->chipset == INTEL_965G) || \ 371*4882a593Smuzhiyun ((dinfo)->chipset == INTEL_965GM)) 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun /*** function prototypes ***/ 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun extern int intelfb_var_to_depth(const struct fb_var_screeninfo *var); 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun #ifdef CONFIG_FB_INTEL_I2C 378*4882a593Smuzhiyun extern void intelfb_create_i2c_busses(struct intelfb_info *dinfo); 379*4882a593Smuzhiyun extern void intelfb_delete_i2c_busses(struct intelfb_info *dinfo); 380*4882a593Smuzhiyun #endif 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun #endif /* _INTELFB_H */ 383