xref: /OK3568_Linux_fs/kernel/drivers/video/fbdev/i810/i810-i2c.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun  /*-*- linux-c -*-
2*4882a593Smuzhiyun  *  linux/drivers/video/i810-i2c.c -- Intel 810/815 I2C support
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *      Copyright (C) 2004 Antonino Daplas<adaplas@pol.net>
5*4882a593Smuzhiyun  *      All Rights Reserved
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  *  This file is subject to the terms and conditions of the GNU General Public
8*4882a593Smuzhiyun  *  License. See the file COPYING in the main directory of this archive for
9*4882a593Smuzhiyun  *  more details.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/gfp.h>
15*4882a593Smuzhiyun #include <linux/pci.h>
16*4882a593Smuzhiyun #include <linux/fb.h>
17*4882a593Smuzhiyun #include "i810.h"
18*4882a593Smuzhiyun #include "i810_regs.h"
19*4882a593Smuzhiyun #include "i810_main.h"
20*4882a593Smuzhiyun #include "../edid.h"
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* bit locations in the registers */
23*4882a593Smuzhiyun #define SCL_DIR_MASK		0x0001
24*4882a593Smuzhiyun #define SCL_DIR			0x0002
25*4882a593Smuzhiyun #define SCL_VAL_MASK		0x0004
26*4882a593Smuzhiyun #define SCL_VAL_OUT		0x0008
27*4882a593Smuzhiyun #define SCL_VAL_IN		0x0010
28*4882a593Smuzhiyun #define SDA_DIR_MASK		0x0100
29*4882a593Smuzhiyun #define SDA_DIR			0x0200
30*4882a593Smuzhiyun #define SDA_VAL_MASK		0x0400
31*4882a593Smuzhiyun #define SDA_VAL_OUT		0x0800
32*4882a593Smuzhiyun #define SDA_VAL_IN		0x1000
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define DEBUG  /* define this for verbose EDID parsing output */
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #ifdef DEBUG
37*4882a593Smuzhiyun #define DPRINTK(fmt, args...) printk(fmt,## args)
38*4882a593Smuzhiyun #else
39*4882a593Smuzhiyun #define DPRINTK(fmt, args...)
40*4882a593Smuzhiyun #endif
41*4882a593Smuzhiyun 
i810i2c_setscl(void * data,int state)42*4882a593Smuzhiyun static void i810i2c_setscl(void *data, int state)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun         struct i810fb_i2c_chan    *chan = data;
45*4882a593Smuzhiyun         struct i810fb_par         *par = chan->par;
46*4882a593Smuzhiyun 	u8                        __iomem *mmio = par->mmio_start_virtual;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	if (state)
49*4882a593Smuzhiyun 		i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK);
50*4882a593Smuzhiyun 	else
51*4882a593Smuzhiyun 		i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
52*4882a593Smuzhiyun 	i810_readl(mmio, chan->ddc_base);	/* flush posted write */
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
i810i2c_setsda(void * data,int state)55*4882a593Smuzhiyun static void i810i2c_setsda(void *data, int state)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun         struct i810fb_i2c_chan    *chan = data;
58*4882a593Smuzhiyun         struct i810fb_par         *par = chan->par;
59*4882a593Smuzhiyun 	u8                        __iomem *mmio = par->mmio_start_virtual;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	if (state)
62*4882a593Smuzhiyun 		i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK);
63*4882a593Smuzhiyun 	else
64*4882a593Smuzhiyun 		i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);
65*4882a593Smuzhiyun 	i810_readl(mmio, chan->ddc_base);	/* flush posted write */
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun 
i810i2c_getscl(void * data)68*4882a593Smuzhiyun static int i810i2c_getscl(void *data)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun         struct i810fb_i2c_chan    *chan = data;
71*4882a593Smuzhiyun         struct i810fb_par         *par = chan->par;
72*4882a593Smuzhiyun 	u8                        __iomem *mmio = par->mmio_start_virtual;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK);
75*4882a593Smuzhiyun 	i810_writel(mmio, chan->ddc_base, 0);
76*4882a593Smuzhiyun 	return ((i810_readl(mmio, chan->ddc_base) & SCL_VAL_IN) != 0);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
i810i2c_getsda(void * data)79*4882a593Smuzhiyun static int i810i2c_getsda(void *data)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun         struct i810fb_i2c_chan    *chan = data;
82*4882a593Smuzhiyun         struct i810fb_par         *par = chan->par;
83*4882a593Smuzhiyun 	u8                        __iomem *mmio = par->mmio_start_virtual;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK);
86*4882a593Smuzhiyun 	i810_writel(mmio, chan->ddc_base, 0);
87*4882a593Smuzhiyun 	return ((i810_readl(mmio, chan->ddc_base) & SDA_VAL_IN) != 0);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
i810_setup_i2c_bus(struct i810fb_i2c_chan * chan,const char * name)90*4882a593Smuzhiyun static int i810_setup_i2c_bus(struct i810fb_i2c_chan *chan, const char *name)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun         int rc;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun         strcpy(chan->adapter.name, name);
95*4882a593Smuzhiyun         chan->adapter.owner             = THIS_MODULE;
96*4882a593Smuzhiyun         chan->adapter.algo_data         = &chan->algo;
97*4882a593Smuzhiyun         chan->adapter.dev.parent        = &chan->par->dev->dev;
98*4882a593Smuzhiyun 	chan->algo.setsda               = i810i2c_setsda;
99*4882a593Smuzhiyun 	chan->algo.setscl               = i810i2c_setscl;
100*4882a593Smuzhiyun 	chan->algo.getsda               = i810i2c_getsda;
101*4882a593Smuzhiyun 	chan->algo.getscl               = i810i2c_getscl;
102*4882a593Smuzhiyun 	chan->algo.udelay               = 10;
103*4882a593Smuzhiyun         chan->algo.timeout              = (HZ/2);
104*4882a593Smuzhiyun         chan->algo.data                 = chan;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun         i2c_set_adapdata(&chan->adapter, chan);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun         /* Raise SCL and SDA */
109*4882a593Smuzhiyun         chan->algo.setsda(chan, 1);
110*4882a593Smuzhiyun         chan->algo.setscl(chan, 1);
111*4882a593Smuzhiyun         udelay(20);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun         rc = i2c_bit_add_bus(&chan->adapter);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun         if (rc == 0)
116*4882a593Smuzhiyun                 dev_dbg(&chan->par->dev->dev, "I2C bus %s registered.\n",name);
117*4882a593Smuzhiyun         else {
118*4882a593Smuzhiyun                 dev_warn(&chan->par->dev->dev, "Failed to register I2C bus "
119*4882a593Smuzhiyun 			 "%s.\n", name);
120*4882a593Smuzhiyun 		chan->par = NULL;
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun         return rc;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
i810_create_i2c_busses(struct i810fb_par * par)126*4882a593Smuzhiyun void i810_create_i2c_busses(struct i810fb_par *par)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun         par->chan[0].par        = par;
129*4882a593Smuzhiyun 	par->chan[1].par        = par;
130*4882a593Smuzhiyun 	par->chan[2].par        = par;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	par->chan[0].ddc_base = GPIOA;
133*4882a593Smuzhiyun 	i810_setup_i2c_bus(&par->chan[0], "I810-DDC");
134*4882a593Smuzhiyun 	par->chan[1].ddc_base = GPIOB;
135*4882a593Smuzhiyun 	i810_setup_i2c_bus(&par->chan[1], "I810-I2C");
136*4882a593Smuzhiyun 	par->chan[2].ddc_base = GPIOC;
137*4882a593Smuzhiyun 	i810_setup_i2c_bus(&par->chan[2], "I810-GPIOC");
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
i810_delete_i2c_busses(struct i810fb_par * par)140*4882a593Smuzhiyun void i810_delete_i2c_busses(struct i810fb_par *par)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun         if (par->chan[0].par)
143*4882a593Smuzhiyun 		i2c_del_adapter(&par->chan[0].adapter);
144*4882a593Smuzhiyun         par->chan[0].par = NULL;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	if (par->chan[1].par)
147*4882a593Smuzhiyun 		i2c_del_adapter(&par->chan[1].adapter);
148*4882a593Smuzhiyun 	par->chan[1].par = NULL;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	if (par->chan[2].par)
151*4882a593Smuzhiyun 		i2c_del_adapter(&par->chan[2].adapter);
152*4882a593Smuzhiyun 	par->chan[2].par = NULL;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
i810_probe_i2c_connector(struct fb_info * info,u8 ** out_edid,int conn)155*4882a593Smuzhiyun int i810_probe_i2c_connector(struct fb_info *info, u8 **out_edid, int conn)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	struct i810fb_par *par = info->par;
158*4882a593Smuzhiyun         u8 *edid = NULL;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	DPRINTK("i810-i2c: Probe DDC%i Bus\n", conn+1);
161*4882a593Smuzhiyun 	if (conn < par->ddc_num) {
162*4882a593Smuzhiyun 		edid = fb_ddc_read(&par->chan[conn].adapter);
163*4882a593Smuzhiyun 	} else {
164*4882a593Smuzhiyun 		const u8 *e = fb_firmware_edid(info->device);
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 		if (e != NULL) {
167*4882a593Smuzhiyun 			DPRINTK("i810-i2c: Getting EDID from BIOS\n");
168*4882a593Smuzhiyun 			edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL);
169*4882a593Smuzhiyun 		}
170*4882a593Smuzhiyun 	}
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	*out_edid = edid;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun         return (edid) ? 0 : 1;
175*4882a593Smuzhiyun }
176