1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * drivers/video/geode/display_gx1.h 4*4882a593Smuzhiyun * -- Geode GX1 display controller 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2005 Arcom Control Systems Ltd. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Based on AMD's original 2.4 driver: 9*4882a593Smuzhiyun * Copyright (C) 2004 Advanced Micro Devices, Inc. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #ifndef __DISPLAY_GX1_H__ 12*4882a593Smuzhiyun #define __DISPLAY_GX1_H__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun unsigned gx1_gx_base(void); 15*4882a593Smuzhiyun int gx1_frame_buffer_size(void); 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun extern const struct geode_dc_ops gx1_dc_ops; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* GX1 configuration I/O registers */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CONFIG_CCR3 0xc3 22*4882a593Smuzhiyun # define CONFIG_CCR3_MAPEN 0x10 23*4882a593Smuzhiyun #define CONFIG_GCR 0xb8 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Memory controller registers */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define MC_BANK_CFG 0x08 28*4882a593Smuzhiyun # define MC_BCFG_DIMM0_SZ_MASK 0x00000700 29*4882a593Smuzhiyun # define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070 30*4882a593Smuzhiyun # define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define MC_GBASE_ADD 0x14 33*4882a593Smuzhiyun # define MC_GADD_GBADD_MASK 0x000003ff 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Display controller registers */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define DC_PAL_ADDRESS 0x70 38*4882a593Smuzhiyun #define DC_PAL_DATA 0x74 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define DC_UNLOCK 0x00 41*4882a593Smuzhiyun # define DC_UNLOCK_CODE 0x00004758 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define DC_GENERAL_CFG 0x04 44*4882a593Smuzhiyun # define DC_GCFG_DFLE 0x00000001 45*4882a593Smuzhiyun # define DC_GCFG_CURE 0x00000002 46*4882a593Smuzhiyun # define DC_GCFG_VCLK_DIV 0x00000004 47*4882a593Smuzhiyun # define DC_GCFG_PLNO 0x00000004 48*4882a593Smuzhiyun # define DC_GCFG_PPC 0x00000008 49*4882a593Smuzhiyun # define DC_GCFG_CMPE 0x00000010 50*4882a593Smuzhiyun # define DC_GCFG_DECE 0x00000020 51*4882a593Smuzhiyun # define DC_GCFG_DCLK_MASK 0x000000C0 52*4882a593Smuzhiyun # define DC_GCFG_DCLK_DIV_1 0x00000080 53*4882a593Smuzhiyun # define DC_GCFG_DFHPSL_MASK 0x00000F00 54*4882a593Smuzhiyun # define DC_GCFG_DFHPSL_POS 8 55*4882a593Smuzhiyun # define DC_GCFG_DFHPEL_MASK 0x0000F000 56*4882a593Smuzhiyun # define DC_GCFG_DFHPEL_POS 12 57*4882a593Smuzhiyun # define DC_GCFG_CIM_MASK 0x00030000 58*4882a593Smuzhiyun # define DC_GCFG_CIM_POS 16 59*4882a593Smuzhiyun # define DC_GCFG_FDTY 0x00040000 60*4882a593Smuzhiyun # define DC_GCFG_RTPM 0x00080000 61*4882a593Smuzhiyun # define DC_GCFG_DAC_RS_MASK 0x00700000 62*4882a593Smuzhiyun # define DC_GCFG_DAC_RS_POS 20 63*4882a593Smuzhiyun # define DC_GCFG_CKWR 0x00800000 64*4882a593Smuzhiyun # define DC_GCFG_LDBL 0x01000000 65*4882a593Smuzhiyun # define DC_GCFG_DIAG 0x02000000 66*4882a593Smuzhiyun # define DC_GCFG_CH4S 0x04000000 67*4882a593Smuzhiyun # define DC_GCFG_SSLC 0x08000000 68*4882a593Smuzhiyun # define DC_GCFG_VIDE 0x10000000 69*4882a593Smuzhiyun # define DC_GCFG_VRDY 0x20000000 70*4882a593Smuzhiyun # define DC_GCFG_DPCK 0x40000000 71*4882a593Smuzhiyun # define DC_GCFG_DDCK 0x80000000 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define DC_TIMING_CFG 0x08 74*4882a593Smuzhiyun # define DC_TCFG_FPPE 0x00000001 75*4882a593Smuzhiyun # define DC_TCFG_HSYE 0x00000002 76*4882a593Smuzhiyun # define DC_TCFG_VSYE 0x00000004 77*4882a593Smuzhiyun # define DC_TCFG_BLKE 0x00000008 78*4882a593Smuzhiyun # define DC_TCFG_DDCK 0x00000010 79*4882a593Smuzhiyun # define DC_TCFG_TGEN 0x00000020 80*4882a593Smuzhiyun # define DC_TCFG_VIEN 0x00000040 81*4882a593Smuzhiyun # define DC_TCFG_BLNK 0x00000080 82*4882a593Smuzhiyun # define DC_TCFG_CHSP 0x00000100 83*4882a593Smuzhiyun # define DC_TCFG_CVSP 0x00000200 84*4882a593Smuzhiyun # define DC_TCFG_FHSP 0x00000400 85*4882a593Smuzhiyun # define DC_TCFG_FVSP 0x00000800 86*4882a593Smuzhiyun # define DC_TCFG_FCEN 0x00001000 87*4882a593Smuzhiyun # define DC_TCFG_CDCE 0x00002000 88*4882a593Smuzhiyun # define DC_TCFG_PLNR 0x00002000 89*4882a593Smuzhiyun # define DC_TCFG_INTL 0x00004000 90*4882a593Smuzhiyun # define DC_TCFG_PXDB 0x00008000 91*4882a593Smuzhiyun # define DC_TCFG_BKRT 0x00010000 92*4882a593Smuzhiyun # define DC_TCFG_PSD_MASK 0x000E0000 93*4882a593Smuzhiyun # define DC_TCFG_PSD_POS 17 94*4882a593Smuzhiyun # define DC_TCFG_DDCI 0x08000000 95*4882a593Smuzhiyun # define DC_TCFG_SENS 0x10000000 96*4882a593Smuzhiyun # define DC_TCFG_DNA 0x20000000 97*4882a593Smuzhiyun # define DC_TCFG_VNA 0x40000000 98*4882a593Smuzhiyun # define DC_TCFG_VINT 0x80000000 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define DC_OUTPUT_CFG 0x0C 101*4882a593Smuzhiyun # define DC_OCFG_8BPP 0x00000001 102*4882a593Smuzhiyun # define DC_OCFG_555 0x00000002 103*4882a593Smuzhiyun # define DC_OCFG_PCKE 0x00000004 104*4882a593Smuzhiyun # define DC_OCFG_FRME 0x00000008 105*4882a593Smuzhiyun # define DC_OCFG_DITE 0x00000010 106*4882a593Smuzhiyun # define DC_OCFG_2PXE 0x00000020 107*4882a593Smuzhiyun # define DC_OCFG_2XCK 0x00000040 108*4882a593Smuzhiyun # define DC_OCFG_2IND 0x00000080 109*4882a593Smuzhiyun # define DC_OCFG_34ADD 0x00000100 110*4882a593Smuzhiyun # define DC_OCFG_FRMS 0x00000200 111*4882a593Smuzhiyun # define DC_OCFG_CKSL 0x00000400 112*4882a593Smuzhiyun # define DC_OCFG_PRMP 0x00000800 113*4882a593Smuzhiyun # define DC_OCFG_PDEL 0x00001000 114*4882a593Smuzhiyun # define DC_OCFG_PDEH 0x00002000 115*4882a593Smuzhiyun # define DC_OCFG_CFRW 0x00004000 116*4882a593Smuzhiyun # define DC_OCFG_DIAG 0x00008000 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define DC_FB_ST_OFFSET 0x10 119*4882a593Smuzhiyun #define DC_CB_ST_OFFSET 0x14 120*4882a593Smuzhiyun #define DC_CURS_ST_OFFSET 0x18 121*4882a593Smuzhiyun #define DC_ICON_ST_OFFSET 0x1C 122*4882a593Smuzhiyun #define DC_VID_ST_OFFSET 0x20 123*4882a593Smuzhiyun #define DC_LINE_DELTA 0x24 124*4882a593Smuzhiyun #define DC_BUF_SIZE 0x28 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define DC_H_TIMING_1 0x30 127*4882a593Smuzhiyun #define DC_H_TIMING_2 0x34 128*4882a593Smuzhiyun #define DC_H_TIMING_3 0x38 129*4882a593Smuzhiyun #define DC_FP_H_TIMING 0x3C 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define DC_V_TIMING_1 0x40 132*4882a593Smuzhiyun #define DC_V_TIMING_2 0x44 133*4882a593Smuzhiyun #define DC_V_TIMING_3 0x48 134*4882a593Smuzhiyun #define DC_FP_V_TIMING 0x4C 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define DC_CURSOR_X 0x50 137*4882a593Smuzhiyun #define DC_ICON_X 0x54 138*4882a593Smuzhiyun #define DC_V_LINE_CNT 0x54 139*4882a593Smuzhiyun #define DC_CURSOR_Y 0x58 140*4882a593Smuzhiyun #define DC_ICON_Y 0x5C 141*4882a593Smuzhiyun #define DC_SS_LINE_CMP 0x5C 142*4882a593Smuzhiyun #define DC_CURSOR_COLOR 0x60 143*4882a593Smuzhiyun #define DC_ICON_COLOR 0x64 144*4882a593Smuzhiyun #define DC_BORDER_COLOR 0x68 145*4882a593Smuzhiyun #define DC_PAL_ADDRESS 0x70 146*4882a593Smuzhiyun #define DC_PAL_DATA 0x74 147*4882a593Smuzhiyun #define DC_DFIFO_DIAG 0x78 148*4882a593Smuzhiyun #define DC_CFIFO_DIAG 0x7C 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #endif /* !__DISPLAY_GX1_H__ */ 151