1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/drivers/video/ep93xx-fb.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Framebuffer support for the EP93xx series.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2007 Bluewater Systems Ltd
8*4882a593Smuzhiyun * Author: Ryan Mallon
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (c) 2009 H Hartley Sweeten <hsweeten@visionengravers.com>
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Based on the Cirrus Logic ep93xxfb driver, and various other ep93xxfb
13*4882a593Smuzhiyun * drivers.
14*4882a593Smuzhiyun */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/module.h>
18*4882a593Smuzhiyun #include <linux/dma-mapping.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/clk.h>
21*4882a593Smuzhiyun #include <linux/fb.h>
22*4882a593Smuzhiyun #include <linux/io.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include <linux/platform_data/video-ep93xx.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Vertical Frame Timing Registers */
27*4882a593Smuzhiyun #define EP93XXFB_VLINES_TOTAL 0x0000 /* SW locked */
28*4882a593Smuzhiyun #define EP93XXFB_VSYNC 0x0004 /* SW locked */
29*4882a593Smuzhiyun #define EP93XXFB_VACTIVE 0x0008 /* SW locked */
30*4882a593Smuzhiyun #define EP93XXFB_VBLANK 0x0228 /* SW locked */
31*4882a593Smuzhiyun #define EP93XXFB_VCLK 0x000c /* SW locked */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Horizontal Frame Timing Registers */
34*4882a593Smuzhiyun #define EP93XXFB_HCLKS_TOTAL 0x0010 /* SW locked */
35*4882a593Smuzhiyun #define EP93XXFB_HSYNC 0x0014 /* SW locked */
36*4882a593Smuzhiyun #define EP93XXFB_HACTIVE 0x0018 /* SW locked */
37*4882a593Smuzhiyun #define EP93XXFB_HBLANK 0x022c /* SW locked */
38*4882a593Smuzhiyun #define EP93XXFB_HCLK 0x001c /* SW locked */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Frame Buffer Memory Configuration Registers */
41*4882a593Smuzhiyun #define EP93XXFB_SCREEN_PAGE 0x0028
42*4882a593Smuzhiyun #define EP93XXFB_SCREEN_HPAGE 0x002c
43*4882a593Smuzhiyun #define EP93XXFB_SCREEN_LINES 0x0030
44*4882a593Smuzhiyun #define EP93XXFB_LINE_LENGTH 0x0034
45*4882a593Smuzhiyun #define EP93XXFB_VLINE_STEP 0x0038
46*4882a593Smuzhiyun #define EP93XXFB_LINE_CARRY 0x003c /* SW locked */
47*4882a593Smuzhiyun #define EP93XXFB_EOL_OFFSET 0x0230
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Other Video Registers */
50*4882a593Smuzhiyun #define EP93XXFB_BRIGHTNESS 0x0020
51*4882a593Smuzhiyun #define EP93XXFB_ATTRIBS 0x0024 /* SW locked */
52*4882a593Smuzhiyun #define EP93XXFB_SWLOCK 0x007c /* SW locked */
53*4882a593Smuzhiyun #define EP93XXFB_AC_RATE 0x0214
54*4882a593Smuzhiyun #define EP93XXFB_FIFO_LEVEL 0x0234
55*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE 0x0054
56*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE_32BPP (0x7 << 0)
57*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE_24BPP (0x6 << 0)
58*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE_16BPP (0x4 << 0)
59*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE_8BPP (0x2 << 0)
60*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE_SHIFT_1P_24B (0x0 << 3)
61*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE_SHIFT_1P_18B (0x1 << 3)
62*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE_COLOR_LUT (0x0 << 10)
63*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE_COLOR_888 (0x4 << 10)
64*4882a593Smuzhiyun #define EP93XXFB_PIXELMODE_COLOR_555 (0x5 << 10)
65*4882a593Smuzhiyun #define EP93XXFB_PARL_IF_OUT 0x0058
66*4882a593Smuzhiyun #define EP93XXFB_PARL_IF_IN 0x005c
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Blink Control Registers */
69*4882a593Smuzhiyun #define EP93XXFB_BLINK_RATE 0x0040
70*4882a593Smuzhiyun #define EP93XXFB_BLINK_MASK 0x0044
71*4882a593Smuzhiyun #define EP93XXFB_BLINK_PATTRN 0x0048
72*4882a593Smuzhiyun #define EP93XXFB_PATTRN_MASK 0x004c
73*4882a593Smuzhiyun #define EP93XXFB_BKGRND_OFFSET 0x0050
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Hardware Cursor Registers */
76*4882a593Smuzhiyun #define EP93XXFB_CURSOR_ADR_START 0x0060
77*4882a593Smuzhiyun #define EP93XXFB_CURSOR_ADR_RESET 0x0064
78*4882a593Smuzhiyun #define EP93XXFB_CURSOR_SIZE 0x0068
79*4882a593Smuzhiyun #define EP93XXFB_CURSOR_COLOR1 0x006c
80*4882a593Smuzhiyun #define EP93XXFB_CURSOR_COLOR2 0x0070
81*4882a593Smuzhiyun #define EP93XXFB_CURSOR_BLINK_COLOR1 0x021c
82*4882a593Smuzhiyun #define EP93XXFB_CURSOR_BLINK_COLOR2 0x0220
83*4882a593Smuzhiyun #define EP93XXFB_CURSOR_XY_LOC 0x0074
84*4882a593Smuzhiyun #define EP93XXFB_CURSOR_DSCAN_HY_LOC 0x0078
85*4882a593Smuzhiyun #define EP93XXFB_CURSOR_BLINK_RATE_CTRL 0x0224
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* LUT Registers */
88*4882a593Smuzhiyun #define EP93XXFB_GRY_SCL_LUTR 0x0080
89*4882a593Smuzhiyun #define EP93XXFB_GRY_SCL_LUTG 0x0280
90*4882a593Smuzhiyun #define EP93XXFB_GRY_SCL_LUTB 0x0300
91*4882a593Smuzhiyun #define EP93XXFB_LUT_SW_CONTROL 0x0218
92*4882a593Smuzhiyun #define EP93XXFB_LUT_SW_CONTROL_SWTCH (1 << 0)
93*4882a593Smuzhiyun #define EP93XXFB_LUT_SW_CONTROL_SSTAT (1 << 1)
94*4882a593Smuzhiyun #define EP93XXFB_COLOR_LUT 0x0400
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* Video Signature Registers */
97*4882a593Smuzhiyun #define EP93XXFB_VID_SIG_RSLT_VAL 0x0200
98*4882a593Smuzhiyun #define EP93XXFB_VID_SIG_CTRL 0x0204
99*4882a593Smuzhiyun #define EP93XXFB_VSIG 0x0208
100*4882a593Smuzhiyun #define EP93XXFB_HSIG 0x020c
101*4882a593Smuzhiyun #define EP93XXFB_SIG_CLR_STR 0x0210
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Minimum / Maximum resolutions supported */
104*4882a593Smuzhiyun #define EP93XXFB_MIN_XRES 64
105*4882a593Smuzhiyun #define EP93XXFB_MIN_YRES 64
106*4882a593Smuzhiyun #define EP93XXFB_MAX_XRES 1024
107*4882a593Smuzhiyun #define EP93XXFB_MAX_YRES 768
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun struct ep93xx_fbi {
110*4882a593Smuzhiyun struct ep93xxfb_mach_info *mach_info;
111*4882a593Smuzhiyun struct clk *clk;
112*4882a593Smuzhiyun struct resource *res;
113*4882a593Smuzhiyun void __iomem *mmio_base;
114*4882a593Smuzhiyun unsigned int pseudo_palette[256];
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static int check_screenpage_bug = 1;
118*4882a593Smuzhiyun module_param(check_screenpage_bug, int, 0644);
119*4882a593Smuzhiyun MODULE_PARM_DESC(check_screenpage_bug,
120*4882a593Smuzhiyun "Check for bit 27 screen page bug. Default = 1");
121*4882a593Smuzhiyun
ep93xxfb_readl(struct ep93xx_fbi * fbi,unsigned int off)122*4882a593Smuzhiyun static inline unsigned int ep93xxfb_readl(struct ep93xx_fbi *fbi,
123*4882a593Smuzhiyun unsigned int off)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun return __raw_readl(fbi->mmio_base + off);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
ep93xxfb_writel(struct ep93xx_fbi * fbi,unsigned int val,unsigned int off)128*4882a593Smuzhiyun static inline void ep93xxfb_writel(struct ep93xx_fbi *fbi,
129*4882a593Smuzhiyun unsigned int val, unsigned int off)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun __raw_writel(val, fbi->mmio_base + off);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun * Write to one of the locked raster registers.
136*4882a593Smuzhiyun */
ep93xxfb_out_locked(struct ep93xx_fbi * fbi,unsigned int val,unsigned int reg)137*4882a593Smuzhiyun static inline void ep93xxfb_out_locked(struct ep93xx_fbi *fbi,
138*4882a593Smuzhiyun unsigned int val, unsigned int reg)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun /*
141*4882a593Smuzhiyun * We don't need a lock or delay here since the raster register
142*4882a593Smuzhiyun * block will remain unlocked until the next access.
143*4882a593Smuzhiyun */
144*4882a593Smuzhiyun ep93xxfb_writel(fbi, 0xaa, EP93XXFB_SWLOCK);
145*4882a593Smuzhiyun ep93xxfb_writel(fbi, val, reg);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
ep93xxfb_set_video_attribs(struct fb_info * info)148*4882a593Smuzhiyun static void ep93xxfb_set_video_attribs(struct fb_info *info)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun struct ep93xx_fbi *fbi = info->par;
151*4882a593Smuzhiyun unsigned int attribs;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun attribs = EP93XXFB_ENABLE;
154*4882a593Smuzhiyun attribs |= fbi->mach_info->flags;
155*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, attribs, EP93XXFB_ATTRIBS);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
ep93xxfb_set_pixelmode(struct fb_info * info)158*4882a593Smuzhiyun static int ep93xxfb_set_pixelmode(struct fb_info *info)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun struct ep93xx_fbi *fbi = info->par;
161*4882a593Smuzhiyun unsigned int val;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun info->var.transp.offset = 0;
164*4882a593Smuzhiyun info->var.transp.length = 0;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun switch (info->var.bits_per_pixel) {
167*4882a593Smuzhiyun case 8:
168*4882a593Smuzhiyun val = EP93XXFB_PIXELMODE_8BPP | EP93XXFB_PIXELMODE_COLOR_LUT |
169*4882a593Smuzhiyun EP93XXFB_PIXELMODE_SHIFT_1P_18B;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun info->var.red.offset = 0;
172*4882a593Smuzhiyun info->var.red.length = 8;
173*4882a593Smuzhiyun info->var.green.offset = 0;
174*4882a593Smuzhiyun info->var.green.length = 8;
175*4882a593Smuzhiyun info->var.blue.offset = 0;
176*4882a593Smuzhiyun info->var.blue.length = 8;
177*4882a593Smuzhiyun info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
178*4882a593Smuzhiyun break;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun case 16:
181*4882a593Smuzhiyun val = EP93XXFB_PIXELMODE_16BPP | EP93XXFB_PIXELMODE_COLOR_555 |
182*4882a593Smuzhiyun EP93XXFB_PIXELMODE_SHIFT_1P_18B;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun info->var.red.offset = 11;
185*4882a593Smuzhiyun info->var.red.length = 5;
186*4882a593Smuzhiyun info->var.green.offset = 5;
187*4882a593Smuzhiyun info->var.green.length = 6;
188*4882a593Smuzhiyun info->var.blue.offset = 0;
189*4882a593Smuzhiyun info->var.blue.length = 5;
190*4882a593Smuzhiyun info->fix.visual = FB_VISUAL_TRUECOLOR;
191*4882a593Smuzhiyun break;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun case 24:
194*4882a593Smuzhiyun val = EP93XXFB_PIXELMODE_24BPP | EP93XXFB_PIXELMODE_COLOR_888 |
195*4882a593Smuzhiyun EP93XXFB_PIXELMODE_SHIFT_1P_24B;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun info->var.red.offset = 16;
198*4882a593Smuzhiyun info->var.red.length = 8;
199*4882a593Smuzhiyun info->var.green.offset = 8;
200*4882a593Smuzhiyun info->var.green.length = 8;
201*4882a593Smuzhiyun info->var.blue.offset = 0;
202*4882a593Smuzhiyun info->var.blue.length = 8;
203*4882a593Smuzhiyun info->fix.visual = FB_VISUAL_TRUECOLOR;
204*4882a593Smuzhiyun break;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun case 32:
207*4882a593Smuzhiyun val = EP93XXFB_PIXELMODE_32BPP | EP93XXFB_PIXELMODE_COLOR_888 |
208*4882a593Smuzhiyun EP93XXFB_PIXELMODE_SHIFT_1P_24B;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun info->var.red.offset = 16;
211*4882a593Smuzhiyun info->var.red.length = 8;
212*4882a593Smuzhiyun info->var.green.offset = 8;
213*4882a593Smuzhiyun info->var.green.length = 8;
214*4882a593Smuzhiyun info->var.blue.offset = 0;
215*4882a593Smuzhiyun info->var.blue.length = 8;
216*4882a593Smuzhiyun info->fix.visual = FB_VISUAL_TRUECOLOR;
217*4882a593Smuzhiyun break;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun default:
220*4882a593Smuzhiyun return -EINVAL;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun ep93xxfb_writel(fbi, val, EP93XXFB_PIXELMODE);
224*4882a593Smuzhiyun return 0;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
ep93xxfb_set_timing(struct fb_info * info)227*4882a593Smuzhiyun static void ep93xxfb_set_timing(struct fb_info *info)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun struct ep93xx_fbi *fbi = info->par;
230*4882a593Smuzhiyun unsigned int vlines_total, hclks_total, start, stop;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun vlines_total = info->var.yres + info->var.upper_margin +
233*4882a593Smuzhiyun info->var.lower_margin + info->var.vsync_len - 1;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun hclks_total = info->var.xres + info->var.left_margin +
236*4882a593Smuzhiyun info->var.right_margin + info->var.hsync_len - 1;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, vlines_total, EP93XXFB_VLINES_TOTAL);
239*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, hclks_total, EP93XXFB_HCLKS_TOTAL);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun start = vlines_total;
242*4882a593Smuzhiyun stop = vlines_total - info->var.vsync_len;
243*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VSYNC);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun start = vlines_total - info->var.vsync_len - info->var.upper_margin;
246*4882a593Smuzhiyun stop = info->var.lower_margin - 1;
247*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VBLANK);
248*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VACTIVE);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun start = vlines_total;
251*4882a593Smuzhiyun stop = vlines_total + 1;
252*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VCLK);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun start = hclks_total;
255*4882a593Smuzhiyun stop = hclks_total - info->var.hsync_len;
256*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HSYNC);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun start = hclks_total - info->var.hsync_len - info->var.left_margin;
259*4882a593Smuzhiyun stop = info->var.right_margin - 1;
260*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HBLANK);
261*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HACTIVE);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun start = hclks_total;
264*4882a593Smuzhiyun stop = hclks_total;
265*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HCLK);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, 0x0, EP93XXFB_LINE_CARRY);
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
ep93xxfb_set_par(struct fb_info * info)270*4882a593Smuzhiyun static int ep93xxfb_set_par(struct fb_info *info)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun struct ep93xx_fbi *fbi = info->par;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun clk_set_rate(fbi->clk, 1000 * PICOS2KHZ(info->var.pixclock));
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun ep93xxfb_set_timing(info);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun info->fix.line_length = info->var.xres_virtual *
279*4882a593Smuzhiyun info->var.bits_per_pixel / 8;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun ep93xxfb_writel(fbi, info->fix.smem_start, EP93XXFB_SCREEN_PAGE);
282*4882a593Smuzhiyun ep93xxfb_writel(fbi, info->var.yres - 1, EP93XXFB_SCREEN_LINES);
283*4882a593Smuzhiyun ep93xxfb_writel(fbi, ((info->var.xres * info->var.bits_per_pixel)
284*4882a593Smuzhiyun / 32) - 1, EP93XXFB_LINE_LENGTH);
285*4882a593Smuzhiyun ep93xxfb_writel(fbi, info->fix.line_length / 4, EP93XXFB_VLINE_STEP);
286*4882a593Smuzhiyun ep93xxfb_set_video_attribs(info);
287*4882a593Smuzhiyun return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
ep93xxfb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)290*4882a593Smuzhiyun static int ep93xxfb_check_var(struct fb_var_screeninfo *var,
291*4882a593Smuzhiyun struct fb_info *info)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun int err;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun err = ep93xxfb_set_pixelmode(info);
296*4882a593Smuzhiyun if (err)
297*4882a593Smuzhiyun return err;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun var->xres = max_t(unsigned int, var->xres, EP93XXFB_MIN_XRES);
300*4882a593Smuzhiyun var->xres = min_t(unsigned int, var->xres, EP93XXFB_MAX_XRES);
301*4882a593Smuzhiyun var->xres_virtual = max(var->xres_virtual, var->xres);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun var->yres = max_t(unsigned int, var->yres, EP93XXFB_MIN_YRES);
304*4882a593Smuzhiyun var->yres = min_t(unsigned int, var->yres, EP93XXFB_MAX_YRES);
305*4882a593Smuzhiyun var->yres_virtual = max(var->yres_virtual, var->yres);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return 0;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
ep93xxfb_mmap(struct fb_info * info,struct vm_area_struct * vma)310*4882a593Smuzhiyun static int ep93xxfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun unsigned int offset = vma->vm_pgoff << PAGE_SHIFT;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun if (offset < info->fix.smem_len) {
315*4882a593Smuzhiyun return dma_mmap_wc(info->dev, vma, info->screen_base,
316*4882a593Smuzhiyun info->fix.smem_start, info->fix.smem_len);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun return -EINVAL;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
ep93xxfb_blank(int blank_mode,struct fb_info * info)322*4882a593Smuzhiyun static int ep93xxfb_blank(int blank_mode, struct fb_info *info)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun struct ep93xx_fbi *fbi = info->par;
325*4882a593Smuzhiyun unsigned int attribs = ep93xxfb_readl(fbi, EP93XXFB_ATTRIBS);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun if (blank_mode) {
328*4882a593Smuzhiyun if (fbi->mach_info->blank)
329*4882a593Smuzhiyun fbi->mach_info->blank(blank_mode, info);
330*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, attribs & ~EP93XXFB_ENABLE,
331*4882a593Smuzhiyun EP93XXFB_ATTRIBS);
332*4882a593Smuzhiyun clk_disable(fbi->clk);
333*4882a593Smuzhiyun } else {
334*4882a593Smuzhiyun clk_enable(fbi->clk);
335*4882a593Smuzhiyun ep93xxfb_out_locked(fbi, attribs | EP93XXFB_ENABLE,
336*4882a593Smuzhiyun EP93XXFB_ATTRIBS);
337*4882a593Smuzhiyun if (fbi->mach_info->blank)
338*4882a593Smuzhiyun fbi->mach_info->blank(blank_mode, info);
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun return 0;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
ep93xxfb_convert_color(int val,int width)344*4882a593Smuzhiyun static inline int ep93xxfb_convert_color(int val, int width)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun return ((val << width) + 0x7fff - val) >> 16;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
ep93xxfb_setcolreg(unsigned int regno,unsigned int red,unsigned int green,unsigned int blue,unsigned int transp,struct fb_info * info)349*4882a593Smuzhiyun static int ep93xxfb_setcolreg(unsigned int regno, unsigned int red,
350*4882a593Smuzhiyun unsigned int green, unsigned int blue,
351*4882a593Smuzhiyun unsigned int transp, struct fb_info *info)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun struct ep93xx_fbi *fbi = info->par;
354*4882a593Smuzhiyun unsigned int *pal = info->pseudo_palette;
355*4882a593Smuzhiyun unsigned int ctrl, i, rgb, lut_current, lut_stat;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun switch (info->fix.visual) {
358*4882a593Smuzhiyun case FB_VISUAL_PSEUDOCOLOR:
359*4882a593Smuzhiyun if (regno > 255)
360*4882a593Smuzhiyun return 1;
361*4882a593Smuzhiyun rgb = ((red & 0xff00) << 8) | (green & 0xff00) |
362*4882a593Smuzhiyun ((blue & 0xff00) >> 8);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun pal[regno] = rgb;
365*4882a593Smuzhiyun ep93xxfb_writel(fbi, rgb, (EP93XXFB_COLOR_LUT + (regno << 2)));
366*4882a593Smuzhiyun ctrl = ep93xxfb_readl(fbi, EP93XXFB_LUT_SW_CONTROL);
367*4882a593Smuzhiyun lut_stat = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SSTAT);
368*4882a593Smuzhiyun lut_current = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SWTCH);
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (lut_stat == lut_current) {
371*4882a593Smuzhiyun for (i = 0; i < 256; i++) {
372*4882a593Smuzhiyun ep93xxfb_writel(fbi, pal[i],
373*4882a593Smuzhiyun EP93XXFB_COLOR_LUT + (i << 2));
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun ep93xxfb_writel(fbi,
377*4882a593Smuzhiyun ctrl ^ EP93XXFB_LUT_SW_CONTROL_SWTCH,
378*4882a593Smuzhiyun EP93XXFB_LUT_SW_CONTROL);
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun break;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun case FB_VISUAL_TRUECOLOR:
383*4882a593Smuzhiyun if (regno > 16)
384*4882a593Smuzhiyun return 1;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun red = ep93xxfb_convert_color(red, info->var.red.length);
387*4882a593Smuzhiyun green = ep93xxfb_convert_color(green, info->var.green.length);
388*4882a593Smuzhiyun blue = ep93xxfb_convert_color(blue, info->var.blue.length);
389*4882a593Smuzhiyun transp = ep93xxfb_convert_color(transp,
390*4882a593Smuzhiyun info->var.transp.length);
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun pal[regno] = (red << info->var.red.offset) |
393*4882a593Smuzhiyun (green << info->var.green.offset) |
394*4882a593Smuzhiyun (blue << info->var.blue.offset) |
395*4882a593Smuzhiyun (transp << info->var.transp.offset);
396*4882a593Smuzhiyun break;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun default:
399*4882a593Smuzhiyun return 1;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun return 0;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun static const struct fb_ops ep93xxfb_ops = {
406*4882a593Smuzhiyun .owner = THIS_MODULE,
407*4882a593Smuzhiyun .fb_check_var = ep93xxfb_check_var,
408*4882a593Smuzhiyun .fb_set_par = ep93xxfb_set_par,
409*4882a593Smuzhiyun .fb_blank = ep93xxfb_blank,
410*4882a593Smuzhiyun .fb_fillrect = cfb_fillrect,
411*4882a593Smuzhiyun .fb_copyarea = cfb_copyarea,
412*4882a593Smuzhiyun .fb_imageblit = cfb_imageblit,
413*4882a593Smuzhiyun .fb_setcolreg = ep93xxfb_setcolreg,
414*4882a593Smuzhiyun .fb_mmap = ep93xxfb_mmap,
415*4882a593Smuzhiyun };
416*4882a593Smuzhiyun
ep93xxfb_alloc_videomem(struct fb_info * info)417*4882a593Smuzhiyun static int ep93xxfb_alloc_videomem(struct fb_info *info)
418*4882a593Smuzhiyun {
419*4882a593Smuzhiyun char __iomem *virt_addr;
420*4882a593Smuzhiyun dma_addr_t phys_addr;
421*4882a593Smuzhiyun unsigned int fb_size;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun /* Maximum 16bpp -> used memory is maximum x*y*2 bytes */
424*4882a593Smuzhiyun fb_size = EP93XXFB_MAX_XRES * EP93XXFB_MAX_YRES * 2;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun virt_addr = dma_alloc_wc(info->dev, fb_size, &phys_addr, GFP_KERNEL);
427*4882a593Smuzhiyun if (!virt_addr)
428*4882a593Smuzhiyun return -ENOMEM;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun /*
431*4882a593Smuzhiyun * There is a bug in the ep93xx framebuffer which causes problems
432*4882a593Smuzhiyun * if bit 27 of the physical address is set.
433*4882a593Smuzhiyun * See: https://marc.info/?l=linux-arm-kernel&m=110061245502000&w=2
434*4882a593Smuzhiyun * There does not seem to be any official errata for this, but I
435*4882a593Smuzhiyun * have confirmed the problem exists on my hardware (ep9315) at
436*4882a593Smuzhiyun * least.
437*4882a593Smuzhiyun */
438*4882a593Smuzhiyun if (check_screenpage_bug && phys_addr & (1 << 27)) {
439*4882a593Smuzhiyun dev_err(info->dev, "ep93xx framebuffer bug. phys addr (0x%x) "
440*4882a593Smuzhiyun "has bit 27 set: cannot init framebuffer\n",
441*4882a593Smuzhiyun phys_addr);
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun dma_free_coherent(info->dev, fb_size, virt_addr, phys_addr);
444*4882a593Smuzhiyun return -ENOMEM;
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun info->fix.smem_start = phys_addr;
448*4882a593Smuzhiyun info->fix.smem_len = fb_size;
449*4882a593Smuzhiyun info->screen_base = virt_addr;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun return 0;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
ep93xxfb_dealloc_videomem(struct fb_info * info)454*4882a593Smuzhiyun static void ep93xxfb_dealloc_videomem(struct fb_info *info)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun if (info->screen_base)
457*4882a593Smuzhiyun dma_free_coherent(info->dev, info->fix.smem_len,
458*4882a593Smuzhiyun info->screen_base, info->fix.smem_start);
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun
ep93xxfb_probe(struct platform_device * pdev)461*4882a593Smuzhiyun static int ep93xxfb_probe(struct platform_device *pdev)
462*4882a593Smuzhiyun {
463*4882a593Smuzhiyun struct ep93xxfb_mach_info *mach_info = dev_get_platdata(&pdev->dev);
464*4882a593Smuzhiyun struct fb_info *info;
465*4882a593Smuzhiyun struct ep93xx_fbi *fbi;
466*4882a593Smuzhiyun struct resource *res;
467*4882a593Smuzhiyun char *video_mode;
468*4882a593Smuzhiyun int err;
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun if (!mach_info)
471*4882a593Smuzhiyun return -EINVAL;
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun info = framebuffer_alloc(sizeof(struct ep93xx_fbi), &pdev->dev);
474*4882a593Smuzhiyun if (!info)
475*4882a593Smuzhiyun return -ENOMEM;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun info->dev = &pdev->dev;
478*4882a593Smuzhiyun platform_set_drvdata(pdev, info);
479*4882a593Smuzhiyun fbi = info->par;
480*4882a593Smuzhiyun fbi->mach_info = mach_info;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun err = fb_alloc_cmap(&info->cmap, 256, 0);
483*4882a593Smuzhiyun if (err)
484*4882a593Smuzhiyun goto failed_cmap;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun err = ep93xxfb_alloc_videomem(info);
487*4882a593Smuzhiyun if (err)
488*4882a593Smuzhiyun goto failed_videomem;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
491*4882a593Smuzhiyun if (!res) {
492*4882a593Smuzhiyun err = -ENXIO;
493*4882a593Smuzhiyun goto failed_resource;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun /*
497*4882a593Smuzhiyun * FIXME - We don't do a request_mem_region here because we are
498*4882a593Smuzhiyun * sharing the register space with the backlight driver (see
499*4882a593Smuzhiyun * drivers/video/backlight/ep93xx_bl.c) and doing so will cause
500*4882a593Smuzhiyun * the second loaded driver to return -EBUSY.
501*4882a593Smuzhiyun *
502*4882a593Smuzhiyun * NOTE: No locking is required; the backlight does not touch
503*4882a593Smuzhiyun * any of the framebuffer registers.
504*4882a593Smuzhiyun */
505*4882a593Smuzhiyun fbi->res = res;
506*4882a593Smuzhiyun fbi->mmio_base = devm_ioremap(&pdev->dev, res->start,
507*4882a593Smuzhiyun resource_size(res));
508*4882a593Smuzhiyun if (!fbi->mmio_base) {
509*4882a593Smuzhiyun err = -ENXIO;
510*4882a593Smuzhiyun goto failed_resource;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun strcpy(info->fix.id, pdev->name);
514*4882a593Smuzhiyun info->fbops = &ep93xxfb_ops;
515*4882a593Smuzhiyun info->fix.type = FB_TYPE_PACKED_PIXELS;
516*4882a593Smuzhiyun info->fix.accel = FB_ACCEL_NONE;
517*4882a593Smuzhiyun info->var.activate = FB_ACTIVATE_NOW;
518*4882a593Smuzhiyun info->var.vmode = FB_VMODE_NONINTERLACED;
519*4882a593Smuzhiyun info->flags = FBINFO_DEFAULT;
520*4882a593Smuzhiyun info->node = -1;
521*4882a593Smuzhiyun info->state = FBINFO_STATE_RUNNING;
522*4882a593Smuzhiyun info->pseudo_palette = &fbi->pseudo_palette;
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun fb_get_options("ep93xx-fb", &video_mode);
525*4882a593Smuzhiyun err = fb_find_mode(&info->var, info, video_mode,
526*4882a593Smuzhiyun NULL, 0, NULL, 16);
527*4882a593Smuzhiyun if (err == 0) {
528*4882a593Smuzhiyun dev_err(info->dev, "No suitable video mode found\n");
529*4882a593Smuzhiyun err = -EINVAL;
530*4882a593Smuzhiyun goto failed_resource;
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun if (mach_info->setup) {
534*4882a593Smuzhiyun err = mach_info->setup(pdev);
535*4882a593Smuzhiyun if (err)
536*4882a593Smuzhiyun goto failed_resource;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun err = ep93xxfb_check_var(&info->var, info);
540*4882a593Smuzhiyun if (err)
541*4882a593Smuzhiyun goto failed_check;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun fbi->clk = devm_clk_get(&pdev->dev, NULL);
544*4882a593Smuzhiyun if (IS_ERR(fbi->clk)) {
545*4882a593Smuzhiyun err = PTR_ERR(fbi->clk);
546*4882a593Smuzhiyun fbi->clk = NULL;
547*4882a593Smuzhiyun goto failed_check;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun ep93xxfb_set_par(info);
551*4882a593Smuzhiyun clk_enable(fbi->clk);
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun err = register_framebuffer(info);
554*4882a593Smuzhiyun if (err)
555*4882a593Smuzhiyun goto failed_check;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun dev_info(info->dev, "registered. Mode = %dx%d-%d\n",
558*4882a593Smuzhiyun info->var.xres, info->var.yres, info->var.bits_per_pixel);
559*4882a593Smuzhiyun return 0;
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun failed_check:
562*4882a593Smuzhiyun if (fbi->mach_info->teardown)
563*4882a593Smuzhiyun fbi->mach_info->teardown(pdev);
564*4882a593Smuzhiyun failed_resource:
565*4882a593Smuzhiyun ep93xxfb_dealloc_videomem(info);
566*4882a593Smuzhiyun failed_videomem:
567*4882a593Smuzhiyun fb_dealloc_cmap(&info->cmap);
568*4882a593Smuzhiyun failed_cmap:
569*4882a593Smuzhiyun kfree(info);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun return err;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
ep93xxfb_remove(struct platform_device * pdev)574*4882a593Smuzhiyun static int ep93xxfb_remove(struct platform_device *pdev)
575*4882a593Smuzhiyun {
576*4882a593Smuzhiyun struct fb_info *info = platform_get_drvdata(pdev);
577*4882a593Smuzhiyun struct ep93xx_fbi *fbi = info->par;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun unregister_framebuffer(info);
580*4882a593Smuzhiyun clk_disable(fbi->clk);
581*4882a593Smuzhiyun ep93xxfb_dealloc_videomem(info);
582*4882a593Smuzhiyun fb_dealloc_cmap(&info->cmap);
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun if (fbi->mach_info->teardown)
585*4882a593Smuzhiyun fbi->mach_info->teardown(pdev);
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun kfree(info);
588*4882a593Smuzhiyun
589*4882a593Smuzhiyun return 0;
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun static struct platform_driver ep93xxfb_driver = {
593*4882a593Smuzhiyun .probe = ep93xxfb_probe,
594*4882a593Smuzhiyun .remove = ep93xxfb_remove,
595*4882a593Smuzhiyun .driver = {
596*4882a593Smuzhiyun .name = "ep93xx-fb",
597*4882a593Smuzhiyun },
598*4882a593Smuzhiyun };
599*4882a593Smuzhiyun module_platform_driver(ep93xxfb_driver);
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun MODULE_DESCRIPTION("EP93XX Framebuffer Driver");
602*4882a593Smuzhiyun MODULE_ALIAS("platform:ep93xx-fb");
603*4882a593Smuzhiyun MODULE_AUTHOR("Ryan Mallon, "
604*4882a593Smuzhiyun "H Hartley Sweeten <hsweeten@visionengravers.com");
605*4882a593Smuzhiyun MODULE_LICENSE("GPL");
606