xref: /OK3568_Linux_fs/kernel/drivers/video/fbdev/dnfb.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun #include <linux/kernel.h>
3*4882a593Smuzhiyun #include <linux/errno.h>
4*4882a593Smuzhiyun #include <linux/string.h>
5*4882a593Smuzhiyun #include <linux/mm.h>
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/interrupt.h>
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <asm/setup.h>
11*4882a593Smuzhiyun #include <asm/irq.h>
12*4882a593Smuzhiyun #include <asm/amigahw.h>
13*4882a593Smuzhiyun #include <asm/amigaints.h>
14*4882a593Smuzhiyun #include <asm/apollohw.h>
15*4882a593Smuzhiyun #include <linux/fb.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* apollo video HW definitions */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun  * Control Registers.   IOBASE + $x
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * Note: these are the Memory/IO BASE definitions for a mono card set to the
24*4882a593Smuzhiyun  * alternate address
25*4882a593Smuzhiyun  *
26*4882a593Smuzhiyun  * Control 3A and 3B serve identical functions except that 3A
27*4882a593Smuzhiyun  * deals with control 1 and 3b deals with Color LUT reg.
28*4882a593Smuzhiyun  */
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define AP_IOBASE       0x3b0	/* Base address of 1 plane board. */
31*4882a593Smuzhiyun #define AP_STATUS       isaIO2mem(AP_IOBASE+0)	/* Status register.  Read */
32*4882a593Smuzhiyun #define AP_WRITE_ENABLE isaIO2mem(AP_IOBASE+0)	/* Write Enable Register Write */
33*4882a593Smuzhiyun #define AP_DEVICE_ID    isaIO2mem(AP_IOBASE+1)	/* Device ID Register. Read */
34*4882a593Smuzhiyun #define AP_ROP_1        isaIO2mem(AP_IOBASE+2)	/* Raster Operation reg. Write Word */
35*4882a593Smuzhiyun #define AP_DIAG_MEM_REQ isaIO2mem(AP_IOBASE+4)	/* Diagnostic Memory Request. Write Word */
36*4882a593Smuzhiyun #define AP_CONTROL_0    isaIO2mem(AP_IOBASE+8)	/* Control Register 0.  Read/Write */
37*4882a593Smuzhiyun #define AP_CONTROL_1    isaIO2mem(AP_IOBASE+0xa)	/* Control Register 1.  Read/Write */
38*4882a593Smuzhiyun #define AP_CONTROL_3A   isaIO2mem(AP_IOBASE+0xe)	/* Control Register 3a. Read/Write */
39*4882a593Smuzhiyun #define AP_CONTROL_2    isaIO2mem(AP_IOBASE+0xc)	/* Control Register 2. Read/Write */
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define FRAME_BUFFER_START 0x0FA0000
43*4882a593Smuzhiyun #define FRAME_BUFFER_LEN 0x40000
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /* CREG 0 */
46*4882a593Smuzhiyun #define VECTOR_MODE 0x40	/* 010x.xxxx */
47*4882a593Smuzhiyun #define DBLT_MODE   0x80	/* 100x.xxxx */
48*4882a593Smuzhiyun #define NORMAL_MODE 0xE0	/* 111x.xxxx */
49*4882a593Smuzhiyun #define SHIFT_BITS  0x1F	/* xxx1.1111 */
50*4882a593Smuzhiyun 	/* other bits are Shift value */
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* CREG 1 */
53*4882a593Smuzhiyun #define AD_BLT      0x80	/* 1xxx.xxxx */
54*4882a593Smuzhiyun #define NORMAL      0x80 /* 1xxx.xxxx */	/* What is happening here ?? */
55*4882a593Smuzhiyun #define INVERSE     0x00 /* 0xxx.xxxx */	/* Clearing this reverses the screen */
56*4882a593Smuzhiyun #define PIX_BLT     0x00	/* 0xxx.xxxx */
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define AD_HIBIT        0x40	/* xIxx.xxxx */
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun #define ROP_EN          0x10	/* xxx1.xxxx */
61*4882a593Smuzhiyun #define DST_EQ_SRC      0x00	/* xxx0.xxxx */
62*4882a593Smuzhiyun #define nRESET_SYNC     0x08	/* xxxx.1xxx */
63*4882a593Smuzhiyun #define SYNC_ENAB       0x02	/* xxxx.xx1x */
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define BLANK_DISP      0x00	/* xxxx.xxx0 */
66*4882a593Smuzhiyun #define ENAB_DISP       0x01	/* xxxx.xxx1 */
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define NORM_CREG1      (nRESET_SYNC | SYNC_ENAB | ENAB_DISP)	/* no reset sync */
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /* CREG 2 */
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /*
73*4882a593Smuzhiyun  * Following 3 defines are common to 1, 4 and 8 plane.
74*4882a593Smuzhiyun  */
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define S_DATA_1s   0x00 /* 00xx.xxxx */	/* set source to all 1's -- vector drawing */
77*4882a593Smuzhiyun #define S_DATA_PIX  0x40 /* 01xx.xxxx */	/* takes source from ls-bits and replicates over 16 bits */
78*4882a593Smuzhiyun #define S_DATA_PLN  0xC0 /* 11xx.xxxx */	/* normal, each data access =16-bits in
79*4882a593Smuzhiyun 						   one plane of image mem */
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /* CREG 3A/CREG 3B */
82*4882a593Smuzhiyun #       define RESET_CREG 0x80	/* 1000.0000 */
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* ROP REG  -  all one nibble */
85*4882a593Smuzhiyun /*      ********* NOTE : this is used r0,r1,r2,r3 *********** */
86*4882a593Smuzhiyun #define ROP(r2,r3,r0,r1) ( (U_SHORT)((r0)|((r1)<<4)|((r2)<<8)|((r3)<<12)) )
87*4882a593Smuzhiyun #define DEST_ZERO               0x0
88*4882a593Smuzhiyun #define SRC_AND_DEST    0x1
89*4882a593Smuzhiyun #define SRC_AND_nDEST   0x2
90*4882a593Smuzhiyun #define SRC                             0x3
91*4882a593Smuzhiyun #define nSRC_AND_DEST   0x4
92*4882a593Smuzhiyun #define DEST                    0x5
93*4882a593Smuzhiyun #define SRC_XOR_DEST    0x6
94*4882a593Smuzhiyun #define SRC_OR_DEST             0x7
95*4882a593Smuzhiyun #define SRC_NOR_DEST    0x8
96*4882a593Smuzhiyun #define SRC_XNOR_DEST   0x9
97*4882a593Smuzhiyun #define nDEST                   0xA
98*4882a593Smuzhiyun #define SRC_OR_nDEST    0xB
99*4882a593Smuzhiyun #define nSRC                    0xC
100*4882a593Smuzhiyun #define nSRC_OR_DEST    0xD
101*4882a593Smuzhiyun #define SRC_NAND_DEST   0xE
102*4882a593Smuzhiyun #define DEST_ONE                0xF
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun #define SWAP(A) ((A>>8) | ((A&0xff) <<8))
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /* frame buffer operations */
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun static int dnfb_blank(int blank, struct fb_info *info);
109*4882a593Smuzhiyun static void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun static const struct fb_ops dn_fb_ops = {
112*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
113*4882a593Smuzhiyun 	.fb_blank	= dnfb_blank,
114*4882a593Smuzhiyun 	.fb_fillrect	= cfb_fillrect,
115*4882a593Smuzhiyun 	.fb_copyarea	= dnfb_copyarea,
116*4882a593Smuzhiyun 	.fb_imageblit	= cfb_imageblit,
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun static const struct fb_var_screeninfo dnfb_var = {
120*4882a593Smuzhiyun 	.xres		= 1280,
121*4882a593Smuzhiyun 	.yres		= 1024,
122*4882a593Smuzhiyun 	.xres_virtual	= 2048,
123*4882a593Smuzhiyun 	.yres_virtual	= 1024,
124*4882a593Smuzhiyun 	.bits_per_pixel	= 1,
125*4882a593Smuzhiyun 	.height		= -1,
126*4882a593Smuzhiyun 	.width		= -1,
127*4882a593Smuzhiyun 	.vmode		= FB_VMODE_NONINTERLACED,
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun static const struct fb_fix_screeninfo dnfb_fix = {
131*4882a593Smuzhiyun 	.id		= "Apollo Mono",
132*4882a593Smuzhiyun 	.smem_start	= (FRAME_BUFFER_START + IO_BASE),
133*4882a593Smuzhiyun 	.smem_len	= FRAME_BUFFER_LEN,
134*4882a593Smuzhiyun 	.type		= FB_TYPE_PACKED_PIXELS,
135*4882a593Smuzhiyun 	.visual		= FB_VISUAL_MONO10,
136*4882a593Smuzhiyun 	.line_length	= 256,
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun 
dnfb_blank(int blank,struct fb_info * info)139*4882a593Smuzhiyun static int dnfb_blank(int blank, struct fb_info *info)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	if (blank)
142*4882a593Smuzhiyun 		out_8(AP_CONTROL_3A, 0x0);
143*4882a593Smuzhiyun 	else
144*4882a593Smuzhiyun 		out_8(AP_CONTROL_3A, 0x1);
145*4882a593Smuzhiyun 	return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun static
dnfb_copyarea(struct fb_info * info,const struct fb_copyarea * area)149*4882a593Smuzhiyun void dnfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	int incr, y_delta, pre_read = 0, x_end, x_word_count;
153*4882a593Smuzhiyun 	uint start_mask, end_mask, dest;
154*4882a593Smuzhiyun 	ushort *src, dummy;
155*4882a593Smuzhiyun 	short i, j;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	incr = (area->dy <= area->sy) ? 1 : -1;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	src = (ushort *)(info->screen_base + area->sy * info->fix.line_length +
160*4882a593Smuzhiyun 			(area->sx >> 4));
161*4882a593Smuzhiyun 	dest = area->dy * (info->fix.line_length >> 1) + (area->dx >> 4);
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	if (incr > 0) {
164*4882a593Smuzhiyun 		y_delta = (info->fix.line_length * 8) - area->sx - area->width;
165*4882a593Smuzhiyun 		x_end = area->dx + area->width - 1;
166*4882a593Smuzhiyun 		x_word_count = (x_end >> 4) - (area->dx >> 4) + 1;
167*4882a593Smuzhiyun 		start_mask = 0xffff0000 >> (area->dx & 0xf);
168*4882a593Smuzhiyun 		end_mask = 0x7ffff >> (x_end & 0xf);
169*4882a593Smuzhiyun 		out_8(AP_CONTROL_0,
170*4882a593Smuzhiyun 		     (((area->dx & 0xf) - (area->sx & 0xf)) % 16) | (0x4 << 5));
171*4882a593Smuzhiyun 		if ((area->dx & 0xf) < (area->sx & 0xf))
172*4882a593Smuzhiyun 			pre_read = 1;
173*4882a593Smuzhiyun 	} else {
174*4882a593Smuzhiyun 		y_delta = -((info->fix.line_length * 8) - area->sx - area->width);
175*4882a593Smuzhiyun 		x_end = area->dx - area->width + 1;
176*4882a593Smuzhiyun 		x_word_count = (area->dx >> 4) - (x_end >> 4) + 1;
177*4882a593Smuzhiyun 		start_mask = 0x7ffff >> (area->dx & 0xf);
178*4882a593Smuzhiyun 		end_mask = 0xffff0000 >> (x_end & 0xf);
179*4882a593Smuzhiyun 		out_8(AP_CONTROL_0,
180*4882a593Smuzhiyun 		     ((-((area->sx & 0xf) - (area->dx & 0xf))) % 16) |
181*4882a593Smuzhiyun 		     (0x4 << 5));
182*4882a593Smuzhiyun 		if ((area->dx & 0xf) > (area->sx & 0xf))
183*4882a593Smuzhiyun 			pre_read = 1;
184*4882a593Smuzhiyun 	}
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	for (i = 0; i < area->height; i++) {
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 		out_8(AP_CONTROL_3A, 0xc | (dest >> 16));
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 		if (pre_read) {
191*4882a593Smuzhiyun 			dummy = *src;
192*4882a593Smuzhiyun 			src += incr;
193*4882a593Smuzhiyun 		}
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 		if (x_word_count) {
196*4882a593Smuzhiyun 			out_8(AP_WRITE_ENABLE, start_mask);
197*4882a593Smuzhiyun 			*src = dest;
198*4882a593Smuzhiyun 			src += incr;
199*4882a593Smuzhiyun 			dest += incr;
200*4882a593Smuzhiyun 			out_8(AP_WRITE_ENABLE, 0);
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 			for (j = 1; j < (x_word_count - 1); j++) {
203*4882a593Smuzhiyun 				*src = dest;
204*4882a593Smuzhiyun 				src += incr;
205*4882a593Smuzhiyun 				dest += incr;
206*4882a593Smuzhiyun 			}
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 			out_8(AP_WRITE_ENABLE, start_mask);
209*4882a593Smuzhiyun 			*src = dest;
210*4882a593Smuzhiyun 			dest += incr;
211*4882a593Smuzhiyun 			src += incr;
212*4882a593Smuzhiyun 		} else {
213*4882a593Smuzhiyun 			out_8(AP_WRITE_ENABLE, start_mask | end_mask);
214*4882a593Smuzhiyun 			*src = dest;
215*4882a593Smuzhiyun 			dest += incr;
216*4882a593Smuzhiyun 			src += incr;
217*4882a593Smuzhiyun 		}
218*4882a593Smuzhiyun 		src += (y_delta / 16);
219*4882a593Smuzhiyun 		dest += (y_delta / 16);
220*4882a593Smuzhiyun 	}
221*4882a593Smuzhiyun 	out_8(AP_CONTROL_0, NORMAL_MODE);
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun /*
225*4882a593Smuzhiyun  * Initialization
226*4882a593Smuzhiyun  */
227*4882a593Smuzhiyun 
dnfb_probe(struct platform_device * dev)228*4882a593Smuzhiyun static int dnfb_probe(struct platform_device *dev)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	struct fb_info *info;
231*4882a593Smuzhiyun 	int err = 0;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	info = framebuffer_alloc(0, &dev->dev);
234*4882a593Smuzhiyun 	if (!info)
235*4882a593Smuzhiyun 		return -ENOMEM;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	info->fbops = &dn_fb_ops;
238*4882a593Smuzhiyun 	info->fix = dnfb_fix;
239*4882a593Smuzhiyun 	info->var = dnfb_var;
240*4882a593Smuzhiyun 	info->var.red.length = 1;
241*4882a593Smuzhiyun 	info->var.red.offset = 0;
242*4882a593Smuzhiyun 	info->var.green = info->var.blue = info->var.red;
243*4882a593Smuzhiyun 	info->screen_base = (u_char *) info->fix.smem_start;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	err = fb_alloc_cmap(&info->cmap, 2, 0);
246*4882a593Smuzhiyun 	if (err < 0)
247*4882a593Smuzhiyun 		goto release_framebuffer;
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	err = register_framebuffer(info);
250*4882a593Smuzhiyun 	if (err < 0) {
251*4882a593Smuzhiyun 		fb_dealloc_cmap(&info->cmap);
252*4882a593Smuzhiyun 		goto release_framebuffer;
253*4882a593Smuzhiyun 	}
254*4882a593Smuzhiyun 	platform_set_drvdata(dev, info);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	/* now we have registered we can safely setup the hardware */
257*4882a593Smuzhiyun 	out_8(AP_CONTROL_3A, RESET_CREG);
258*4882a593Smuzhiyun 	out_be16(AP_WRITE_ENABLE, 0x0);
259*4882a593Smuzhiyun 	out_8(AP_CONTROL_0, NORMAL_MODE);
260*4882a593Smuzhiyun 	out_8(AP_CONTROL_1, (AD_BLT | DST_EQ_SRC | NORM_CREG1));
261*4882a593Smuzhiyun 	out_8(AP_CONTROL_2, S_DATA_PLN);
262*4882a593Smuzhiyun 	out_be16(AP_ROP_1, SWAP(0x3));
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	printk("apollo frame buffer alive and kicking !\n");
265*4882a593Smuzhiyun 	return err;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun release_framebuffer:
268*4882a593Smuzhiyun 	framebuffer_release(info);
269*4882a593Smuzhiyun 	return err;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun static struct platform_driver dnfb_driver = {
273*4882a593Smuzhiyun 	.probe	= dnfb_probe,
274*4882a593Smuzhiyun 	.driver	= {
275*4882a593Smuzhiyun 		.name	= "dnfb",
276*4882a593Smuzhiyun 	},
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun static struct platform_device dnfb_device = {
280*4882a593Smuzhiyun 	.name	= "dnfb",
281*4882a593Smuzhiyun };
282*4882a593Smuzhiyun 
dnfb_init(void)283*4882a593Smuzhiyun int __init dnfb_init(void)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	int ret;
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	if (!MACH_IS_APOLLO)
288*4882a593Smuzhiyun 		return -ENODEV;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	if (fb_get_options("dnfb", NULL))
291*4882a593Smuzhiyun 		return -ENODEV;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	ret = platform_driver_register(&dnfb_driver);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	if (!ret) {
296*4882a593Smuzhiyun 		ret = platform_device_register(&dnfb_device);
297*4882a593Smuzhiyun 		if (ret)
298*4882a593Smuzhiyun 			platform_driver_unregister(&dnfb_driver);
299*4882a593Smuzhiyun 	}
300*4882a593Smuzhiyun 	return ret;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun module_init(dnfb_init);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun MODULE_LICENSE("GPL");
306