1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /* cg14.c: CGFOURTEEN frame buffer driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
5*4882a593Smuzhiyun * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
6*4882a593Smuzhiyun * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Driver layout based loosely on tgafb.c, see that file for credits.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/errno.h>
14*4882a593Smuzhiyun #include <linux/string.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/fb.h>
18*4882a593Smuzhiyun #include <linux/mm.h>
19*4882a593Smuzhiyun #include <linux/uaccess.h>
20*4882a593Smuzhiyun #include <linux/of_device.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <asm/io.h>
23*4882a593Smuzhiyun #include <asm/fbio.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include "sbuslib.h"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * Local functions.
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
32*4882a593Smuzhiyun unsigned, struct fb_info *);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static int cg14_mmap(struct fb_info *, struct vm_area_struct *);
35*4882a593Smuzhiyun static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
36*4882a593Smuzhiyun static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * Frame buffer operations
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static const struct fb_ops cg14_ops = {
43*4882a593Smuzhiyun .owner = THIS_MODULE,
44*4882a593Smuzhiyun .fb_setcolreg = cg14_setcolreg,
45*4882a593Smuzhiyun .fb_pan_display = cg14_pan_display,
46*4882a593Smuzhiyun .fb_fillrect = cfb_fillrect,
47*4882a593Smuzhiyun .fb_copyarea = cfb_copyarea,
48*4882a593Smuzhiyun .fb_imageblit = cfb_imageblit,
49*4882a593Smuzhiyun .fb_mmap = cg14_mmap,
50*4882a593Smuzhiyun .fb_ioctl = cg14_ioctl,
51*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
52*4882a593Smuzhiyun .fb_compat_ioctl = sbusfb_compat_ioctl,
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define CG14_MCR_INTENABLE_SHIFT 7
57*4882a593Smuzhiyun #define CG14_MCR_INTENABLE_MASK 0x80
58*4882a593Smuzhiyun #define CG14_MCR_VIDENABLE_SHIFT 6
59*4882a593Smuzhiyun #define CG14_MCR_VIDENABLE_MASK 0x40
60*4882a593Smuzhiyun #define CG14_MCR_PIXMODE_SHIFT 4
61*4882a593Smuzhiyun #define CG14_MCR_PIXMODE_MASK 0x30
62*4882a593Smuzhiyun #define CG14_MCR_TMR_SHIFT 2
63*4882a593Smuzhiyun #define CG14_MCR_TMR_MASK 0x0c
64*4882a593Smuzhiyun #define CG14_MCR_TMENABLE_SHIFT 1
65*4882a593Smuzhiyun #define CG14_MCR_TMENABLE_MASK 0x02
66*4882a593Smuzhiyun #define CG14_MCR_RESET_SHIFT 0
67*4882a593Smuzhiyun #define CG14_MCR_RESET_MASK 0x01
68*4882a593Smuzhiyun #define CG14_REV_REVISION_SHIFT 4
69*4882a593Smuzhiyun #define CG14_REV_REVISION_MASK 0xf0
70*4882a593Smuzhiyun #define CG14_REV_IMPL_SHIFT 0
71*4882a593Smuzhiyun #define CG14_REV_IMPL_MASK 0x0f
72*4882a593Smuzhiyun #define CG14_VBR_FRAMEBASE_SHIFT 12
73*4882a593Smuzhiyun #define CG14_VBR_FRAMEBASE_MASK 0x00fff000
74*4882a593Smuzhiyun #define CG14_VMCR1_SETUP_SHIFT 0
75*4882a593Smuzhiyun #define CG14_VMCR1_SETUP_MASK 0x000001ff
76*4882a593Smuzhiyun #define CG14_VMCR1_VCONFIG_SHIFT 9
77*4882a593Smuzhiyun #define CG14_VMCR1_VCONFIG_MASK 0x00000e00
78*4882a593Smuzhiyun #define CG14_VMCR2_REFRESH_SHIFT 0
79*4882a593Smuzhiyun #define CG14_VMCR2_REFRESH_MASK 0x00000001
80*4882a593Smuzhiyun #define CG14_VMCR2_TESTROWCNT_SHIFT 1
81*4882a593Smuzhiyun #define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
82*4882a593Smuzhiyun #define CG14_VMCR2_FBCONFIG_SHIFT 2
83*4882a593Smuzhiyun #define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
84*4882a593Smuzhiyun #define CG14_VCR_REFRESHREQ_SHIFT 0
85*4882a593Smuzhiyun #define CG14_VCR_REFRESHREQ_MASK 0x000003ff
86*4882a593Smuzhiyun #define CG14_VCR1_REFRESHENA_SHIFT 10
87*4882a593Smuzhiyun #define CG14_VCR1_REFRESHENA_MASK 0x00000400
88*4882a593Smuzhiyun #define CG14_VCA_CAD_SHIFT 0
89*4882a593Smuzhiyun #define CG14_VCA_CAD_MASK 0x000003ff
90*4882a593Smuzhiyun #define CG14_VCA_VERS_SHIFT 10
91*4882a593Smuzhiyun #define CG14_VCA_VERS_MASK 0x00000c00
92*4882a593Smuzhiyun #define CG14_VCA_RAMSPEED_SHIFT 12
93*4882a593Smuzhiyun #define CG14_VCA_RAMSPEED_MASK 0x00001000
94*4882a593Smuzhiyun #define CG14_VCA_8MB_SHIFT 13
95*4882a593Smuzhiyun #define CG14_VCA_8MB_MASK 0x00002000
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #define CG14_MCR_PIXMODE_8 0
98*4882a593Smuzhiyun #define CG14_MCR_PIXMODE_16 2
99*4882a593Smuzhiyun #define CG14_MCR_PIXMODE_32 3
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun struct cg14_regs{
102*4882a593Smuzhiyun u8 mcr; /* Master Control Reg */
103*4882a593Smuzhiyun u8 ppr; /* Packed Pixel Reg */
104*4882a593Smuzhiyun u8 tms[2]; /* Test Mode Status Regs */
105*4882a593Smuzhiyun u8 msr; /* Master Status Reg */
106*4882a593Smuzhiyun u8 fsr; /* Fault Status Reg */
107*4882a593Smuzhiyun u8 rev; /* Revision & Impl */
108*4882a593Smuzhiyun u8 ccr; /* Clock Control Reg */
109*4882a593Smuzhiyun u32 tmr; /* Test Mode Read Back */
110*4882a593Smuzhiyun u8 mod; /* Monitor Operation Data Reg */
111*4882a593Smuzhiyun u8 acr; /* Aux Control */
112*4882a593Smuzhiyun u8 xxx0[6];
113*4882a593Smuzhiyun u16 hct; /* Hor Counter */
114*4882a593Smuzhiyun u16 vct; /* Vert Counter */
115*4882a593Smuzhiyun u16 hbs; /* Hor Blank Start */
116*4882a593Smuzhiyun u16 hbc; /* Hor Blank Clear */
117*4882a593Smuzhiyun u16 hss; /* Hor Sync Start */
118*4882a593Smuzhiyun u16 hsc; /* Hor Sync Clear */
119*4882a593Smuzhiyun u16 csc; /* Composite Sync Clear */
120*4882a593Smuzhiyun u16 vbs; /* Vert Blank Start */
121*4882a593Smuzhiyun u16 vbc; /* Vert Blank Clear */
122*4882a593Smuzhiyun u16 vss; /* Vert Sync Start */
123*4882a593Smuzhiyun u16 vsc; /* Vert Sync Clear */
124*4882a593Smuzhiyun u16 xcs;
125*4882a593Smuzhiyun u16 xcc;
126*4882a593Smuzhiyun u16 fsa; /* Fault Status Address */
127*4882a593Smuzhiyun u16 adr; /* Address Registers */
128*4882a593Smuzhiyun u8 xxx1[0xce];
129*4882a593Smuzhiyun u8 pcg[0x100]; /* Pixel Clock Generator */
130*4882a593Smuzhiyun u32 vbr; /* Frame Base Row */
131*4882a593Smuzhiyun u32 vmcr; /* VBC Master Control */
132*4882a593Smuzhiyun u32 vcr; /* VBC refresh */
133*4882a593Smuzhiyun u32 vca; /* VBC Config */
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #define CG14_CCR_ENABLE 0x04
137*4882a593Smuzhiyun #define CG14_CCR_SELECT 0x02 /* HW/Full screen */
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun struct cg14_cursor {
140*4882a593Smuzhiyun u32 cpl0[32]; /* Enable plane 0 */
141*4882a593Smuzhiyun u32 cpl1[32]; /* Color selection plane */
142*4882a593Smuzhiyun u8 ccr; /* Cursor Control Reg */
143*4882a593Smuzhiyun u8 xxx0[3];
144*4882a593Smuzhiyun u16 cursx; /* Cursor x,y position */
145*4882a593Smuzhiyun u16 cursy; /* Cursor x,y position */
146*4882a593Smuzhiyun u32 color0;
147*4882a593Smuzhiyun u32 color1;
148*4882a593Smuzhiyun u32 xxx1[0x1bc];
149*4882a593Smuzhiyun u32 cpl0i[32]; /* Enable plane 0 autoinc */
150*4882a593Smuzhiyun u32 cpl1i[32]; /* Color selection autoinc */
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun struct cg14_dac {
154*4882a593Smuzhiyun u8 addr; /* Address Register */
155*4882a593Smuzhiyun u8 xxx0[255];
156*4882a593Smuzhiyun u8 glut; /* Gamma table */
157*4882a593Smuzhiyun u8 xxx1[255];
158*4882a593Smuzhiyun u8 select; /* Register Select */
159*4882a593Smuzhiyun u8 xxx2[255];
160*4882a593Smuzhiyun u8 mode; /* Mode Register */
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun struct cg14_xlut{
164*4882a593Smuzhiyun u8 x_xlut [256];
165*4882a593Smuzhiyun u8 x_xlutd [256];
166*4882a593Smuzhiyun u8 xxx0[0x600];
167*4882a593Smuzhiyun u8 x_xlut_inc [256];
168*4882a593Smuzhiyun u8 x_xlutd_inc [256];
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /* Color look up table (clut) */
172*4882a593Smuzhiyun /* Each one of these arrays hold the color lookup table (for 256
173*4882a593Smuzhiyun * colors) for each MDI page (I assume then there should be 4 MDI
174*4882a593Smuzhiyun * pages, I still wonder what they are. I have seen NeXTStep split
175*4882a593Smuzhiyun * the screen in four parts, while operating in 24 bits mode. Each
176*4882a593Smuzhiyun * integer holds 4 values: alpha value (transparency channel, thanks
177*4882a593Smuzhiyun * go to John Stone (johns@umr.edu) from OpenBSD), red, green and blue
178*4882a593Smuzhiyun *
179*4882a593Smuzhiyun * I currently use the clut instead of the Xlut
180*4882a593Smuzhiyun */
181*4882a593Smuzhiyun struct cg14_clut {
182*4882a593Smuzhiyun u32 c_clut [256];
183*4882a593Smuzhiyun u32 c_clutd [256]; /* i wonder what the 'd' is for */
184*4882a593Smuzhiyun u32 c_clut_inc [256];
185*4882a593Smuzhiyun u32 c_clutd_inc [256];
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun #define CG14_MMAP_ENTRIES 16
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun struct cg14_par {
191*4882a593Smuzhiyun spinlock_t lock;
192*4882a593Smuzhiyun struct cg14_regs __iomem *regs;
193*4882a593Smuzhiyun struct cg14_clut __iomem *clut;
194*4882a593Smuzhiyun struct cg14_cursor __iomem *cursor;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun u32 flags;
197*4882a593Smuzhiyun #define CG14_FLAG_BLANKED 0x00000001
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun unsigned long iospace;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES];
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun int mode;
204*4882a593Smuzhiyun int ramsize;
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun
__cg14_reset(struct cg14_par * par)207*4882a593Smuzhiyun static void __cg14_reset(struct cg14_par *par)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun struct cg14_regs __iomem *regs = par->regs;
210*4882a593Smuzhiyun u8 val;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun val = sbus_readb(®s->mcr);
213*4882a593Smuzhiyun val &= ~(CG14_MCR_PIXMODE_MASK);
214*4882a593Smuzhiyun sbus_writeb(val, ®s->mcr);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
cg14_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)217*4882a593Smuzhiyun static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun struct cg14_par *par = (struct cg14_par *) info->par;
220*4882a593Smuzhiyun unsigned long flags;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /* We just use this to catch switches out of
223*4882a593Smuzhiyun * graphics mode.
224*4882a593Smuzhiyun */
225*4882a593Smuzhiyun spin_lock_irqsave(&par->lock, flags);
226*4882a593Smuzhiyun __cg14_reset(par);
227*4882a593Smuzhiyun spin_unlock_irqrestore(&par->lock, flags);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun if (var->xoffset || var->yoffset || var->vmode)
230*4882a593Smuzhiyun return -EINVAL;
231*4882a593Smuzhiyun return 0;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /**
235*4882a593Smuzhiyun * cg14_setcolreg - Optional function. Sets a color register.
236*4882a593Smuzhiyun * @regno: boolean, 0 copy local, 1 get_user() function
237*4882a593Smuzhiyun * @red: frame buffer colormap structure
238*4882a593Smuzhiyun * @green: The green value which can be up to 16 bits wide
239*4882a593Smuzhiyun * @blue: The blue value which can be up to 16 bits wide.
240*4882a593Smuzhiyun * @transp: If supported the alpha value which can be up to 16 bits wide.
241*4882a593Smuzhiyun * @info: frame buffer info structure
242*4882a593Smuzhiyun */
cg14_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)243*4882a593Smuzhiyun static int cg14_setcolreg(unsigned regno,
244*4882a593Smuzhiyun unsigned red, unsigned green, unsigned blue,
245*4882a593Smuzhiyun unsigned transp, struct fb_info *info)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun struct cg14_par *par = (struct cg14_par *) info->par;
248*4882a593Smuzhiyun struct cg14_clut __iomem *clut = par->clut;
249*4882a593Smuzhiyun unsigned long flags;
250*4882a593Smuzhiyun u32 val;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun if (regno >= 256)
253*4882a593Smuzhiyun return 1;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun red >>= 8;
256*4882a593Smuzhiyun green >>= 8;
257*4882a593Smuzhiyun blue >>= 8;
258*4882a593Smuzhiyun val = (red | (green << 8) | (blue << 16));
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun spin_lock_irqsave(&par->lock, flags);
261*4882a593Smuzhiyun sbus_writel(val, &clut->c_clut[regno]);
262*4882a593Smuzhiyun spin_unlock_irqrestore(&par->lock, flags);
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun return 0;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
cg14_mmap(struct fb_info * info,struct vm_area_struct * vma)267*4882a593Smuzhiyun static int cg14_mmap(struct fb_info *info, struct vm_area_struct *vma)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct cg14_par *par = (struct cg14_par *) info->par;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun return sbusfb_mmap_helper(par->mmap_map,
272*4882a593Smuzhiyun info->fix.smem_start, info->fix.smem_len,
273*4882a593Smuzhiyun par->iospace, vma);
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
cg14_ioctl(struct fb_info * info,unsigned int cmd,unsigned long arg)276*4882a593Smuzhiyun static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun struct cg14_par *par = (struct cg14_par *) info->par;
279*4882a593Smuzhiyun struct cg14_regs __iomem *regs = par->regs;
280*4882a593Smuzhiyun struct mdi_cfginfo kmdi, __user *mdii;
281*4882a593Smuzhiyun unsigned long flags;
282*4882a593Smuzhiyun int cur_mode, mode, ret = 0;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun switch (cmd) {
285*4882a593Smuzhiyun case MDI_RESET:
286*4882a593Smuzhiyun spin_lock_irqsave(&par->lock, flags);
287*4882a593Smuzhiyun __cg14_reset(par);
288*4882a593Smuzhiyun spin_unlock_irqrestore(&par->lock, flags);
289*4882a593Smuzhiyun break;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun case MDI_GET_CFGINFO:
292*4882a593Smuzhiyun memset(&kmdi, 0, sizeof(kmdi));
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun spin_lock_irqsave(&par->lock, flags);
295*4882a593Smuzhiyun kmdi.mdi_type = FBTYPE_MDICOLOR;
296*4882a593Smuzhiyun kmdi.mdi_height = info->var.yres;
297*4882a593Smuzhiyun kmdi.mdi_width = info->var.xres;
298*4882a593Smuzhiyun kmdi.mdi_mode = par->mode;
299*4882a593Smuzhiyun kmdi.mdi_pixfreq = 72; /* FIXME */
300*4882a593Smuzhiyun kmdi.mdi_size = par->ramsize;
301*4882a593Smuzhiyun spin_unlock_irqrestore(&par->lock, flags);
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun mdii = (struct mdi_cfginfo __user *) arg;
304*4882a593Smuzhiyun if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
305*4882a593Smuzhiyun ret = -EFAULT;
306*4882a593Smuzhiyun break;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun case MDI_SET_PIXELMODE:
309*4882a593Smuzhiyun if (get_user(mode, (int __user *) arg)) {
310*4882a593Smuzhiyun ret = -EFAULT;
311*4882a593Smuzhiyun break;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun spin_lock_irqsave(&par->lock, flags);
315*4882a593Smuzhiyun cur_mode = sbus_readb(®s->mcr);
316*4882a593Smuzhiyun cur_mode &= ~CG14_MCR_PIXMODE_MASK;
317*4882a593Smuzhiyun switch(mode) {
318*4882a593Smuzhiyun case MDI_32_PIX:
319*4882a593Smuzhiyun cur_mode |= (CG14_MCR_PIXMODE_32 <<
320*4882a593Smuzhiyun CG14_MCR_PIXMODE_SHIFT);
321*4882a593Smuzhiyun break;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun case MDI_16_PIX:
324*4882a593Smuzhiyun cur_mode |= (CG14_MCR_PIXMODE_16 <<
325*4882a593Smuzhiyun CG14_MCR_PIXMODE_SHIFT);
326*4882a593Smuzhiyun break;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun case MDI_8_PIX:
329*4882a593Smuzhiyun break;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun default:
332*4882a593Smuzhiyun ret = -ENOSYS;
333*4882a593Smuzhiyun break;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun if (!ret) {
336*4882a593Smuzhiyun sbus_writeb(cur_mode, ®s->mcr);
337*4882a593Smuzhiyun par->mode = mode;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun spin_unlock_irqrestore(&par->lock, flags);
340*4882a593Smuzhiyun break;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun default:
343*4882a593Smuzhiyun ret = sbusfb_ioctl_helper(cmd, arg, info,
344*4882a593Smuzhiyun FBTYPE_MDICOLOR, 8,
345*4882a593Smuzhiyun info->fix.smem_len);
346*4882a593Smuzhiyun break;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun return ret;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun /*
353*4882a593Smuzhiyun * Initialisation
354*4882a593Smuzhiyun */
355*4882a593Smuzhiyun
cg14_init_fix(struct fb_info * info,int linebytes,struct device_node * dp)356*4882a593Smuzhiyun static void cg14_init_fix(struct fb_info *info, int linebytes,
357*4882a593Smuzhiyun struct device_node *dp)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun snprintf(info->fix.id, sizeof(info->fix.id), "%pOFn", dp);
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun info->fix.type = FB_TYPE_PACKED_PIXELS;
362*4882a593Smuzhiyun info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun info->fix.line_length = linebytes;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun info->fix.accel = FB_ACCEL_SUN_CG14;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] = {
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun .voff = CG14_REGS,
372*4882a593Smuzhiyun .poff = 0x80000000,
373*4882a593Smuzhiyun .size = 0x1000
374*4882a593Smuzhiyun },
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun .voff = CG14_XLUT,
377*4882a593Smuzhiyun .poff = 0x80003000,
378*4882a593Smuzhiyun .size = 0x1000
379*4882a593Smuzhiyun },
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun .voff = CG14_CLUT1,
382*4882a593Smuzhiyun .poff = 0x80004000,
383*4882a593Smuzhiyun .size = 0x1000
384*4882a593Smuzhiyun },
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun .voff = CG14_CLUT2,
387*4882a593Smuzhiyun .poff = 0x80005000,
388*4882a593Smuzhiyun .size = 0x1000
389*4882a593Smuzhiyun },
390*4882a593Smuzhiyun {
391*4882a593Smuzhiyun .voff = CG14_CLUT3,
392*4882a593Smuzhiyun .poff = 0x80006000,
393*4882a593Smuzhiyun .size = 0x1000
394*4882a593Smuzhiyun },
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun .voff = CG3_MMAP_OFFSET - 0x7000,
397*4882a593Smuzhiyun .poff = 0x80000000,
398*4882a593Smuzhiyun .size = 0x7000
399*4882a593Smuzhiyun },
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun .voff = CG3_MMAP_OFFSET,
402*4882a593Smuzhiyun .poff = 0x00000000,
403*4882a593Smuzhiyun .size = SBUS_MMAP_FBSIZE(1)
404*4882a593Smuzhiyun },
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun .voff = MDI_CURSOR_MAP,
407*4882a593Smuzhiyun .poff = 0x80001000,
408*4882a593Smuzhiyun .size = 0x1000
409*4882a593Smuzhiyun },
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun .voff = MDI_CHUNKY_BGR_MAP,
412*4882a593Smuzhiyun .poff = 0x01000000,
413*4882a593Smuzhiyun .size = 0x400000
414*4882a593Smuzhiyun },
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun .voff = MDI_PLANAR_X16_MAP,
417*4882a593Smuzhiyun .poff = 0x02000000,
418*4882a593Smuzhiyun .size = 0x200000
419*4882a593Smuzhiyun },
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun .voff = MDI_PLANAR_C16_MAP,
422*4882a593Smuzhiyun .poff = 0x02800000,
423*4882a593Smuzhiyun .size = 0x200000
424*4882a593Smuzhiyun },
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun .voff = MDI_PLANAR_X32_MAP,
427*4882a593Smuzhiyun .poff = 0x03000000,
428*4882a593Smuzhiyun .size = 0x100000
429*4882a593Smuzhiyun },
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun .voff = MDI_PLANAR_B32_MAP,
432*4882a593Smuzhiyun .poff = 0x03400000,
433*4882a593Smuzhiyun .size = 0x100000
434*4882a593Smuzhiyun },
435*4882a593Smuzhiyun {
436*4882a593Smuzhiyun .voff = MDI_PLANAR_G32_MAP,
437*4882a593Smuzhiyun .poff = 0x03800000,
438*4882a593Smuzhiyun .size = 0x100000
439*4882a593Smuzhiyun },
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun .voff = MDI_PLANAR_R32_MAP,
442*4882a593Smuzhiyun .poff = 0x03c00000,
443*4882a593Smuzhiyun .size = 0x100000
444*4882a593Smuzhiyun },
445*4882a593Smuzhiyun { .size = 0 }
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun
cg14_unmap_regs(struct platform_device * op,struct fb_info * info,struct cg14_par * par)448*4882a593Smuzhiyun static void cg14_unmap_regs(struct platform_device *op, struct fb_info *info,
449*4882a593Smuzhiyun struct cg14_par *par)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun if (par->regs)
452*4882a593Smuzhiyun of_iounmap(&op->resource[0],
453*4882a593Smuzhiyun par->regs, sizeof(struct cg14_regs));
454*4882a593Smuzhiyun if (par->clut)
455*4882a593Smuzhiyun of_iounmap(&op->resource[0],
456*4882a593Smuzhiyun par->clut, sizeof(struct cg14_clut));
457*4882a593Smuzhiyun if (par->cursor)
458*4882a593Smuzhiyun of_iounmap(&op->resource[0],
459*4882a593Smuzhiyun par->cursor, sizeof(struct cg14_cursor));
460*4882a593Smuzhiyun if (info->screen_base)
461*4882a593Smuzhiyun of_iounmap(&op->resource[1],
462*4882a593Smuzhiyun info->screen_base, info->fix.smem_len);
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
cg14_probe(struct platform_device * op)465*4882a593Smuzhiyun static int cg14_probe(struct platform_device *op)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun struct device_node *dp = op->dev.of_node;
468*4882a593Smuzhiyun struct fb_info *info;
469*4882a593Smuzhiyun struct cg14_par *par;
470*4882a593Smuzhiyun int is_8mb, linebytes, i, err;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev);
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun err = -ENOMEM;
475*4882a593Smuzhiyun if (!info)
476*4882a593Smuzhiyun goto out_err;
477*4882a593Smuzhiyun par = info->par;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun spin_lock_init(&par->lock);
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun sbusfb_fill_var(&info->var, dp, 8);
482*4882a593Smuzhiyun info->var.red.length = 8;
483*4882a593Smuzhiyun info->var.green.length = 8;
484*4882a593Smuzhiyun info->var.blue.length = 8;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun linebytes = of_getintprop_default(dp, "linebytes",
487*4882a593Smuzhiyun info->var.xres);
488*4882a593Smuzhiyun info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun if (of_node_name_eq(dp->parent, "sbus") ||
491*4882a593Smuzhiyun of_node_name_eq(dp->parent, "sbi")) {
492*4882a593Smuzhiyun info->fix.smem_start = op->resource[0].start;
493*4882a593Smuzhiyun par->iospace = op->resource[0].flags & IORESOURCE_BITS;
494*4882a593Smuzhiyun } else {
495*4882a593Smuzhiyun info->fix.smem_start = op->resource[1].start;
496*4882a593Smuzhiyun par->iospace = op->resource[0].flags & IORESOURCE_BITS;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun par->regs = of_ioremap(&op->resource[0], 0,
500*4882a593Smuzhiyun sizeof(struct cg14_regs), "cg14 regs");
501*4882a593Smuzhiyun par->clut = of_ioremap(&op->resource[0], CG14_CLUT1,
502*4882a593Smuzhiyun sizeof(struct cg14_clut), "cg14 clut");
503*4882a593Smuzhiyun par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
504*4882a593Smuzhiyun sizeof(struct cg14_cursor), "cg14 cursor");
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun info->screen_base = of_ioremap(&op->resource[1], 0,
507*4882a593Smuzhiyun info->fix.smem_len, "cg14 ram");
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun if (!par->regs || !par->clut || !par->cursor || !info->screen_base)
510*4882a593Smuzhiyun goto out_unmap_regs;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun is_8mb = (resource_size(&op->resource[1]) == (8 * 1024 * 1024));
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map));
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map));
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
519*4882a593Smuzhiyun struct sbus_mmap_map *map = &par->mmap_map[i];
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun if (!map->size)
522*4882a593Smuzhiyun break;
523*4882a593Smuzhiyun if (map->poff & 0x80000000)
524*4882a593Smuzhiyun map->poff = (map->poff & 0x7fffffff) +
525*4882a593Smuzhiyun (op->resource[0].start -
526*4882a593Smuzhiyun op->resource[1].start);
527*4882a593Smuzhiyun if (is_8mb &&
528*4882a593Smuzhiyun map->size >= 0x100000 &&
529*4882a593Smuzhiyun map->size <= 0x400000)
530*4882a593Smuzhiyun map->size *= 2;
531*4882a593Smuzhiyun }
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun par->mode = MDI_8_PIX;
534*4882a593Smuzhiyun par->ramsize = (is_8mb ? 0x800000 : 0x400000);
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
537*4882a593Smuzhiyun info->fbops = &cg14_ops;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun __cg14_reset(par);
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun if (fb_alloc_cmap(&info->cmap, 256, 0))
542*4882a593Smuzhiyun goto out_unmap_regs;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun fb_set_cmap(&info->cmap, info);
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun cg14_init_fix(info, linebytes, dp);
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun err = register_framebuffer(info);
549*4882a593Smuzhiyun if (err < 0)
550*4882a593Smuzhiyun goto out_dealloc_cmap;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun dev_set_drvdata(&op->dev, info);
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun printk(KERN_INFO "%pOF: cgfourteen at %lx:%lx, %dMB\n",
555*4882a593Smuzhiyun dp,
556*4882a593Smuzhiyun par->iospace, info->fix.smem_start,
557*4882a593Smuzhiyun par->ramsize >> 20);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun return 0;
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun out_dealloc_cmap:
562*4882a593Smuzhiyun fb_dealloc_cmap(&info->cmap);
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun out_unmap_regs:
565*4882a593Smuzhiyun cg14_unmap_regs(op, info, par);
566*4882a593Smuzhiyun framebuffer_release(info);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun out_err:
569*4882a593Smuzhiyun return err;
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun
cg14_remove(struct platform_device * op)572*4882a593Smuzhiyun static int cg14_remove(struct platform_device *op)
573*4882a593Smuzhiyun {
574*4882a593Smuzhiyun struct fb_info *info = dev_get_drvdata(&op->dev);
575*4882a593Smuzhiyun struct cg14_par *par = info->par;
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun unregister_framebuffer(info);
578*4882a593Smuzhiyun fb_dealloc_cmap(&info->cmap);
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun cg14_unmap_regs(op, info, par);
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun framebuffer_release(info);
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun return 0;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun static const struct of_device_id cg14_match[] = {
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun .name = "cgfourteen",
590*4882a593Smuzhiyun },
591*4882a593Smuzhiyun {},
592*4882a593Smuzhiyun };
593*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, cg14_match);
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun static struct platform_driver cg14_driver = {
596*4882a593Smuzhiyun .driver = {
597*4882a593Smuzhiyun .name = "cg14",
598*4882a593Smuzhiyun .of_match_table = cg14_match,
599*4882a593Smuzhiyun },
600*4882a593Smuzhiyun .probe = cg14_probe,
601*4882a593Smuzhiyun .remove = cg14_remove,
602*4882a593Smuzhiyun };
603*4882a593Smuzhiyun
cg14_init(void)604*4882a593Smuzhiyun static int __init cg14_init(void)
605*4882a593Smuzhiyun {
606*4882a593Smuzhiyun if (fb_get_options("cg14fb", NULL))
607*4882a593Smuzhiyun return -ENODEV;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun return platform_driver_register(&cg14_driver);
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
cg14_exit(void)612*4882a593Smuzhiyun static void __exit cg14_exit(void)
613*4882a593Smuzhiyun {
614*4882a593Smuzhiyun platform_driver_unregister(&cg14_driver);
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun module_init(cg14_init);
618*4882a593Smuzhiyun module_exit(cg14_exit);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
621*4882a593Smuzhiyun MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
622*4882a593Smuzhiyun MODULE_VERSION("2.0");
623*4882a593Smuzhiyun MODULE_LICENSE("GPL");
624