xref: /OK3568_Linux_fs/kernel/drivers/video/fbdev/carminefb_regs.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef _CARMINEFB_REGS_H
3*4882a593Smuzhiyun #define _CARMINEFB_REGS_H
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #define CARMINE_OVERLAY_EXT_MODE	(0x00000002)
6*4882a593Smuzhiyun #define CARMINE_GRAPH_REG		(0x00000000)
7*4882a593Smuzhiyun #define CARMINE_DISP0_REG		(0x00100000)
8*4882a593Smuzhiyun #define CARMINE_DISP1_REG		(0x00140000)
9*4882a593Smuzhiyun #define CARMINE_WB_REG			(0x00180000)
10*4882a593Smuzhiyun #define CARMINE_DCTL_REG		(0x00300000)
11*4882a593Smuzhiyun #define CARMINE_CTL_REG			(0x00400000)
12*4882a593Smuzhiyun #define CARMINE_WINDOW_MODE		(0x00000001)
13*4882a593Smuzhiyun #define CARMINE_EXTEND_MODE		(CARMINE_WINDOW_MODE | \
14*4882a593Smuzhiyun 					CARMINE_OVERLAY_EXT_MODE)
15*4882a593Smuzhiyun #define CARMINE_L0E			(1 << 16)
16*4882a593Smuzhiyun #define CARMINE_L2E			(1 << 18)
17*4882a593Smuzhiyun #define CARMINE_DEN			(1 << 31)
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define CARMINE_EXT_CMODE_DIRECT24_RGBA		(0xC0000000)
20*4882a593Smuzhiyun #define CARMINE_DCTL_REG_MODE_ADD		(0x00)
21*4882a593Smuzhiyun #define CARMINE_DCTL_REG_SETTIME1_EMODE		(0x04)
22*4882a593Smuzhiyun #define CARMINE_DCTL_REG_REFRESH_SETTIME2	(0x08)
23*4882a593Smuzhiyun #define CARMINE_DCTL_REG_RSV0_STATES		(0x0C)
24*4882a593Smuzhiyun #define CARMINE_DCTL_REG_RSV2_RSV1		(0x10)
25*4882a593Smuzhiyun #define CARMINE_DCTL_REG_DDRIF2_DDRIF1		(0x14)
26*4882a593Smuzhiyun #define CARMINE_DCTL_REG_IOCONT1_IOCONT0	(0x24)
27*4882a593Smuzhiyun #define CARMINE_DCTL_REG_STATES_MASK		(0x000F)
28*4882a593Smuzhiyun #define CARMINE_DCTL_INIT_WAIT_INTERVAL		(1)
29*4882a593Smuzhiyun #define CARMINE_DCTL_INIT_WAIT_LIMIT		(5000)
30*4882a593Smuzhiyun #define CARMINE_WB_REG_WBM_DEFAULT		(0x0001c020)
31*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0RM			(0x1880)
32*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0PX			(0x1884)
33*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0PY			(0x1888)
34*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2RM			(0x18A0)
35*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2PX			(0x18A4)
36*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2PY			(0x18A8)
37*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3RM			(0x18B0)
38*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3PX			(0x18B4)
39*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3PY			(0x18B8)
40*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4RM			(0x18C0)
41*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4PX			(0x18C4)
42*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4PY			(0x18C8)
43*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5RM			(0x18D0)
44*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5PX			(0x18D4)
45*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5PY			(0x18D8)
46*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6RM			(0x1924)
47*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6PX			(0x1928)
48*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6PY			(0x192C)
49*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7RM			(0x1964)
50*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7PX			(0x1968)
51*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7PY			(0x196C)
52*4882a593Smuzhiyun #define CARMINE_WB_REG_WBM			(0x0004)
53*4882a593Smuzhiyun #define CARMINE_DISP_HTP_SHIFT			(16)
54*4882a593Smuzhiyun #define CARMINE_DISP_HDB_SHIFT			(16)
55*4882a593Smuzhiyun #define CARMINE_DISP_HSW_SHIFT			(16)
56*4882a593Smuzhiyun #define CARMINE_DISP_VSW_SHIFT			(24)
57*4882a593Smuzhiyun #define CARMINE_DISP_VTR_SHIFT			(16)
58*4882a593Smuzhiyun #define CARMINE_DISP_VDP_SHIFT			(16)
59*4882a593Smuzhiyun #define CARMINE_CURSOR_CUTZ_MASK		(0x00000100)
60*4882a593Smuzhiyun #define CARMINE_CURSOR0_PRIORITY_MASK		(0x00010000)
61*4882a593Smuzhiyun #define CARMINE_CURSOR1_PRIORITY_MASK		(0x00020000)
62*4882a593Smuzhiyun #define CARMINE_DISP_WIDTH_SHIFT		(16)
63*4882a593Smuzhiyun #define CARMINE_DISP_WIN_H_SHIFT		(16)
64*4882a593Smuzhiyun #define CARMINE_DISP_REG_H_TOTAL		(0x0004)
65*4882a593Smuzhiyun #define CARMINE_DISP_REG_H_PERIOD		(0x0008)
66*4882a593Smuzhiyun #define CARMINE_DISP_REG_V_H_W_H_POS		(0x000C)
67*4882a593Smuzhiyun #define CARMINE_DISP_REG_V_TOTAL		(0x0010)
68*4882a593Smuzhiyun #define CARMINE_DISP_REG_V_PERIOD_POS		(0x0014)
69*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0_MODE_W_H		(0x0020)
70*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0_ORG_ADR		(0x0024)
71*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0_DISP_ADR		(0x0028)
72*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0_DISP_POS		(0x002C)
73*4882a593Smuzhiyun #define CARMINE_DISP_REG_L1_WIDTH		(0x0030)
74*4882a593Smuzhiyun #define CARMINE_DISP_REG_L1_ORG_ADR		(0x0034)
75*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2_MODE_W_H		(0x0040)
76*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2_ORG_ADR1		(0x0044)
77*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2_DISP_ADR1		(0x0048)
78*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2_DISP_POS		(0x0054)
79*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3_MODE_W_H		(0x0058)
80*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3_ORG_ADR1		(0x005C)
81*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3_DISP_ADR1		(0x0060)
82*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3_DISP_POS		(0x006C)
83*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4_MODE_W_H		(0x0070)
84*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4_ORG_ADR1		(0x0074)
85*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4_DISP_ADR1		(0x0078)
86*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4_DISP_POS		(0x0084)
87*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5_MODE_W_H		(0x0088)
88*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5_ORG_ADR1		(0x008C)
89*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5_DISP_ADR1		(0x0090)
90*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5_DISP_POS		(0x009C)
91*4882a593Smuzhiyun #define CARMINE_DISP_REG_CURSOR_MODE		(0x00A0)
92*4882a593Smuzhiyun #define CARMINE_DISP_REG_CUR1_POS		(0x00A8)
93*4882a593Smuzhiyun #define CARMINE_DISP_REG_CUR2_POS		(0x00B0)
94*4882a593Smuzhiyun #define CARMINE_DISP_REG_C_TRANS		(0x00BC)
95*4882a593Smuzhiyun #define CARMINE_DISP_REG_MLMR_TRANS		(0x00C0)
96*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0_EXT_MODE		(0x0110)
97*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0_WIN_POS		(0x0114)
98*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0_WIN_SIZE		(0x0118)
99*4882a593Smuzhiyun #define CARMINE_DISP_REG_L1_EXT_MODE		(0x0120)
100*4882a593Smuzhiyun #define CARMINE_DISP_REG_L1_WIN_POS		(0x0124)
101*4882a593Smuzhiyun #define CARMINE_DISP_REG_L1_WIN_SIZE		(0x0128)
102*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2_EXT_MODE		(0x0130)
103*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2_WIN_POS		(0x0134)
104*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2_WIN_SIZE		(0x0138)
105*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3_EXT_MODE		(0x0140)
106*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3_WIN_POS		(0x0144)
107*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3_WIN_SIZE		(0x0148)
108*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4_EXT_MODE		(0x0150)
109*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4_WIN_POS		(0x0154)
110*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4_WIN_SIZE		(0x0158)
111*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5_EXT_MODE		(0x0160)
112*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5_WIN_POS		(0x0164)
113*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5_WIN_SIZE		(0x0168)
114*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6_EXT_MODE		(0x1918)
115*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6_WIN_POS		(0x191c)
116*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6_WIN_SIZE		(0x1920)
117*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7_EXT_MODE		(0x1958)
118*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7_WIN_POS		(0x195c)
119*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7_WIN_SIZE		(0x1960)
120*4882a593Smuzhiyun #define CARMINE_DISP_REG_BLEND_MODE_L0		(0x00B4)
121*4882a593Smuzhiyun #define CARMINE_DISP_REG_BLEND_MODE_L1		(0x0188)
122*4882a593Smuzhiyun #define CARMINE_DISP_REG_BLEND_MODE_L2		(0x018C)
123*4882a593Smuzhiyun #define CARMINE_DISP_REG_BLEND_MODE_L3		(0x0190)
124*4882a593Smuzhiyun #define CARMINE_DISP_REG_BLEND_MODE_L4		(0x0194)
125*4882a593Smuzhiyun #define CARMINE_DISP_REG_BLEND_MODE_L5		(0x0198)
126*4882a593Smuzhiyun #define CARMINE_DISP_REG_BLEND_MODE_L6		(0x1990)
127*4882a593Smuzhiyun #define CARMINE_DISP_REG_BLEND_MODE_L7		(0x1994)
128*4882a593Smuzhiyun #define CARMINE_DISP_REG_L0_TRANS		(0x01A0)
129*4882a593Smuzhiyun #define CARMINE_DISP_REG_L1_TRANS		(0x01A4)
130*4882a593Smuzhiyun #define CARMINE_DISP_REG_L2_TRANS		(0x01A8)
131*4882a593Smuzhiyun #define CARMINE_DISP_REG_L3_TRANS		(0x01AC)
132*4882a593Smuzhiyun #define CARMINE_DISP_REG_L4_TRANS		(0x01B0)
133*4882a593Smuzhiyun #define CARMINE_DISP_REG_L5_TRANS		(0x01B4)
134*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6_TRANS		(0x1998)
135*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7_TRANS		(0x199c)
136*4882a593Smuzhiyun #define CARMINE_EXTEND_MODE_MASK		(0x00000003)
137*4882a593Smuzhiyun #define CARMINE_DISP_DCM_MASK			(0x0000FFFF)
138*4882a593Smuzhiyun #define CARMINE_DISP_REG_DCM1			(0x0100)
139*4882a593Smuzhiyun #define CARMINE_DISP_WIDTH_UNIT			(64)
140*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6_MODE_W_H		(0x1900)
141*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6_ORG_ADR1		(0x1904)
142*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6_DISP_ADR0		(0x1908)
143*4882a593Smuzhiyun #define CARMINE_DISP_REG_L6_DISP_POS		(0x1914)
144*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7_MODE_W_H		(0x1940)
145*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7_ORG_ADR1		(0x1944)
146*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7_DISP_ADR0		(0x1948)
147*4882a593Smuzhiyun #define CARMINE_DISP_REG_L7_DISP_POS		(0x1954)
148*4882a593Smuzhiyun #define CARMINE_CTL_REG_CLOCK_ENABLE		(0x000C)
149*4882a593Smuzhiyun #define CARMINE_CTL_REG_SOFTWARE_RESET		(0x0010)
150*4882a593Smuzhiyun #define CARMINE_CTL_REG_IST_MASK_ALL		(0x07FFFFFF)
151*4882a593Smuzhiyun #define CARMINE_GRAPH_REG_VRINTM		(0x00028064)
152*4882a593Smuzhiyun #define CARMINE_GRAPH_REG_VRERRM		(0x0002806C)
153*4882a593Smuzhiyun #define CARMINE_GRAPH_REG_DC_OFFSET_PX		(0x0004005C)
154*4882a593Smuzhiyun #define CARMINE_GRAPH_REG_DC_OFFSET_PY		(0x00040060)
155*4882a593Smuzhiyun #define CARMINE_GRAPH_REG_DC_OFFSET_LX		(0x00040064)
156*4882a593Smuzhiyun #define CARMINE_GRAPH_REG_DC_OFFSET_LY		(0x00040068)
157*4882a593Smuzhiyun #define CARMINE_GRAPH_REG_DC_OFFSET_TX		(0x0004006C)
158*4882a593Smuzhiyun #define CARMINE_GRAPH_REG_DC_OFFSET_TY		(0x00040070)
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun #endif
161