1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef CARMINE_CARMINE_H 3*4882a593Smuzhiyun #define CARMINE_CARMINE_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define CARMINE_MEMORY_BAR 2 6*4882a593Smuzhiyun #define CARMINE_CONFIG_BAR 3 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define MAX_DISPLAY 2 9*4882a593Smuzhiyun #define CARMINE_DISPLAY_MEM (800 * 600 * 4) 10*4882a593Smuzhiyun #define CARMINE_TOTAL_DIPLAY_MEM (CARMINE_DISPLAY_MEM * MAX_DISPLAY) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CARMINE_USE_DISPLAY0 (1 << 0) 13*4882a593Smuzhiyun #define CARMINE_USE_DISPLAY1 (1 << 1) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * This values work on the eval card. Custom boards may use different timings, 17*4882a593Smuzhiyun * here an example :) 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* DRAM initialization values */ 21*4882a593Smuzhiyun #ifdef CONFIG_FB_CARMINE_DRAM_EVAL 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CARMINE_DFLT_IP_CLOCK_ENABLE (0x03ff) 24*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_ADD (0x05c3) 25*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_MODE (0x0121) 26*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_EMODE (0x8000) 27*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_SET_TIME1 (0x4749) 28*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_SET_TIME2 (0x2a22) 29*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_REFRESH (0x0042) 30*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_STATES (0x0003) 31*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_RESERVE0 (0x0020) 32*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH (0x000f) 33*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_RESERVE2 (0x0000) 34*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_DDRIF1 (0x6646) 35*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_DDRIF2 (0x0055) 36*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST (0x0021) 37*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST (0x0002) 38*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_IO_CONT0 (0x0555) 39*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_IO_CONT1 (0x0555) 40*4882a593Smuzhiyun #define CARMINE_DCTL_DLL_RESET (1) 41*4882a593Smuzhiyun #endif 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #ifdef CONFIG_CARMINE_DRAM_CUSTOM 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CARMINE_DFLT_IP_CLOCK_ENABLE (0x03ff) 46*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_ADD (0x03b2) 47*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_MODE (0x0161) 48*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_EMODE (0x8000) 49*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_SET_TIME1 (0x2628) 50*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_SET_TIME2 (0x1a09) 51*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_REFRESH (0x00fe) 52*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_STATES (0x0003) 53*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_RESERVE0 (0x0020) 54*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_FIFO_DEPTH (0x000f) 55*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_RESERVE2 (0x0000) 56*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_DDRIF1 (0x0646) 57*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_DDRIF2 (0x55aa) 58*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_MODE_AFT_RST (0x0061) 59*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_STATES_AFT_RST (0x0002) 60*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_IO_CONT0 (0x0555) 61*4882a593Smuzhiyun #define CARMINE_DFLT_IP_DCTL_IO_CONT1 (0x0555) 62*4882a593Smuzhiyun #define CARMINE_DCTL_DLL_RESET (1) 63*4882a593Smuzhiyun #endif 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif 66