1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Register definitions for Samsung LTV350QV Quarter VGA LCD Panel 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2006, 2007 Atmel Corporation 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __LTV350QV_H 8*4882a593Smuzhiyun #define __LTV350QV_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define LTV_OPC_INDEX 0x74 11*4882a593Smuzhiyun #define LTV_OPC_DATA 0x76 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define LTV_ID 0x00 /* ID Read */ 14*4882a593Smuzhiyun #define LTV_IFCTL 0x01 /* Display Interface Control */ 15*4882a593Smuzhiyun #define LTV_DATACTL 0x02 /* Display Data Control */ 16*4882a593Smuzhiyun #define LTV_ENTRY_MODE 0x03 /* Entry Mode */ 17*4882a593Smuzhiyun #define LTV_GATECTL1 0x04 /* Gate Control 1 */ 18*4882a593Smuzhiyun #define LTV_GATECTL2 0x05 /* Gate Control 2 */ 19*4882a593Smuzhiyun #define LTV_VBP 0x06 /* Vertical Back Porch */ 20*4882a593Smuzhiyun #define LTV_HBP 0x07 /* Horizontal Back Porch */ 21*4882a593Smuzhiyun #define LTV_SOTCTL 0x08 /* Source Output Timing Control */ 22*4882a593Smuzhiyun #define LTV_PWRCTL1 0x09 /* Power Control 1 */ 23*4882a593Smuzhiyun #define LTV_PWRCTL2 0x0a /* Power Control 2 */ 24*4882a593Smuzhiyun #define LTV_GAMMA(x) (0x10 + (x)) /* Gamma control */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Bit definitions for LTV_IFCTL */ 27*4882a593Smuzhiyun #define LTV_IM (1 << 15) 28*4882a593Smuzhiyun #define LTV_NMD (1 << 14) 29*4882a593Smuzhiyun #define LTV_SSMD (1 << 13) 30*4882a593Smuzhiyun #define LTV_REV (1 << 7) 31*4882a593Smuzhiyun #define LTV_NL(x) (((x) & 0x001f) << 0) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Bit definitions for LTV_DATACTL */ 34*4882a593Smuzhiyun #define LTV_DS_SAME (0 << 12) 35*4882a593Smuzhiyun #define LTV_DS_D_TO_S (1 << 12) 36*4882a593Smuzhiyun #define LTV_DS_S_TO_D (2 << 12) 37*4882a593Smuzhiyun #define LTV_CHS_384 (0 << 9) 38*4882a593Smuzhiyun #define LTV_CHS_480 (1 << 9) 39*4882a593Smuzhiyun #define LTV_CHS_492 (2 << 9) 40*4882a593Smuzhiyun #define LTV_DF_RGB (0 << 6) 41*4882a593Smuzhiyun #define LTV_DF_RGBX (1 << 6) 42*4882a593Smuzhiyun #define LTV_DF_XRGB (2 << 6) 43*4882a593Smuzhiyun #define LTV_RGB_RGB (0 << 2) 44*4882a593Smuzhiyun #define LTV_RGB_BGR (1 << 2) 45*4882a593Smuzhiyun #define LTV_RGB_GRB (2 << 2) 46*4882a593Smuzhiyun #define LTV_RGB_RBG (3 << 2) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Bit definitions for LTV_ENTRY_MODE */ 49*4882a593Smuzhiyun #define LTV_VSPL_ACTIVE_LOW (0 << 15) 50*4882a593Smuzhiyun #define LTV_VSPL_ACTIVE_HIGH (1 << 15) 51*4882a593Smuzhiyun #define LTV_HSPL_ACTIVE_LOW (0 << 14) 52*4882a593Smuzhiyun #define LTV_HSPL_ACTIVE_HIGH (1 << 14) 53*4882a593Smuzhiyun #define LTV_DPL_SAMPLE_RISING (0 << 13) 54*4882a593Smuzhiyun #define LTV_DPL_SAMPLE_FALLING (1 << 13) 55*4882a593Smuzhiyun #define LTV_EPL_ACTIVE_LOW (0 << 12) 56*4882a593Smuzhiyun #define LTV_EPL_ACTIVE_HIGH (1 << 12) 57*4882a593Smuzhiyun #define LTV_SS_LEFT_TO_RIGHT (0 << 8) 58*4882a593Smuzhiyun #define LTV_SS_RIGHT_TO_LEFT (1 << 8) 59*4882a593Smuzhiyun #define LTV_STB (1 << 1) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Bit definitions for LTV_GATECTL1 */ 62*4882a593Smuzhiyun #define LTV_CLW(x) (((x) & 0x0007) << 12) 63*4882a593Smuzhiyun #define LTV_GAON (1 << 5) 64*4882a593Smuzhiyun #define LTV_SDR (1 << 3) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Bit definitions for LTV_GATECTL2 */ 67*4882a593Smuzhiyun #define LTV_NW_INV_FRAME (0 << 14) 68*4882a593Smuzhiyun #define LTV_NW_INV_1LINE (1 << 14) 69*4882a593Smuzhiyun #define LTV_NW_INV_2LINE (2 << 14) 70*4882a593Smuzhiyun #define LTV_DSC (1 << 12) 71*4882a593Smuzhiyun #define LTV_GIF (1 << 8) 72*4882a593Smuzhiyun #define LTV_FHN (1 << 7) 73*4882a593Smuzhiyun #define LTV_FTI(x) (((x) & 0x0003) << 4) 74*4882a593Smuzhiyun #define LTV_FWI(x) (((x) & 0x0003) << 0) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* Bit definitions for LTV_SOTCTL */ 77*4882a593Smuzhiyun #define LTV_SDT(x) (((x) & 0x0007) << 10) 78*4882a593Smuzhiyun #define LTV_EQ(x) (((x) & 0x0007) << 2) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Bit definitions for LTV_PWRCTL1 */ 81*4882a593Smuzhiyun #define LTV_VCOM_DISABLE (1 << 14) 82*4882a593Smuzhiyun #define LTV_VCOMOUT_ENABLE (1 << 11) 83*4882a593Smuzhiyun #define LTV_POWER_ON (1 << 9) 84*4882a593Smuzhiyun #define LTV_DRIVE_CURRENT(x) (((x) & 0x0007) << 4) /* 0=off, 5=max */ 85*4882a593Smuzhiyun #define LTV_SUPPLY_CURRENT(x) (((x) & 0x0007) << 0) /* 0=off, 5=max */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Bit definitions for LTV_PWRCTL2 */ 88*4882a593Smuzhiyun #define LTV_VCOML_ENABLE (1 << 13) 89*4882a593Smuzhiyun #define LTV_VCOML_VOLTAGE(x) (((x) & 0x001f) << 8) /* 0=1V, 31=-1V */ 90*4882a593Smuzhiyun #define LTV_VCOMH_VOLTAGE(x) (((x) & 0x001f) << 0) /* 0=3V, 31=4.5V */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif /* __LTV350QV_H */ 93