1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * VFIO PCI Intel Graphics support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Red Hat, Inc. All rights reserved.
6*4882a593Smuzhiyun * Author: Alex Williamson <alex.williamson@redhat.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Register a device specific region through which to provide read-only
9*4882a593Smuzhiyun * access to the Intel IGD opregion. The register defining the opregion
10*4882a593Smuzhiyun * address is also virtualized to prevent user modification.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/uaccess.h>
16*4882a593Smuzhiyun #include <linux/vfio.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "vfio_pci_private.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define OPREGION_SIGNATURE "IntelGraphicsMem"
21*4882a593Smuzhiyun #define OPREGION_SIZE (8 * 1024)
22*4882a593Smuzhiyun #define OPREGION_PCI_ADDR 0xfc
23*4882a593Smuzhiyun
vfio_pci_igd_rw(struct vfio_pci_device * vdev,char __user * buf,size_t count,loff_t * ppos,bool iswrite)24*4882a593Smuzhiyun static size_t vfio_pci_igd_rw(struct vfio_pci_device *vdev, char __user *buf,
25*4882a593Smuzhiyun size_t count, loff_t *ppos, bool iswrite)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - VFIO_PCI_NUM_REGIONS;
28*4882a593Smuzhiyun void *base = vdev->region[i].data;
29*4882a593Smuzhiyun loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun if (pos >= vdev->region[i].size || iswrite)
32*4882a593Smuzhiyun return -EINVAL;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun count = min(count, (size_t)(vdev->region[i].size - pos));
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (copy_to_user(buf, base + pos, count))
37*4882a593Smuzhiyun return -EFAULT;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun *ppos += count;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return count;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
vfio_pci_igd_release(struct vfio_pci_device * vdev,struct vfio_pci_region * region)44*4882a593Smuzhiyun static void vfio_pci_igd_release(struct vfio_pci_device *vdev,
45*4882a593Smuzhiyun struct vfio_pci_region *region)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun memunmap(region->data);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct vfio_pci_regops vfio_pci_igd_regops = {
51*4882a593Smuzhiyun .rw = vfio_pci_igd_rw,
52*4882a593Smuzhiyun .release = vfio_pci_igd_release,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
vfio_pci_igd_opregion_init(struct vfio_pci_device * vdev)55*4882a593Smuzhiyun static int vfio_pci_igd_opregion_init(struct vfio_pci_device *vdev)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun __le32 *dwordp = (__le32 *)(vdev->vconfig + OPREGION_PCI_ADDR);
58*4882a593Smuzhiyun u32 addr, size;
59*4882a593Smuzhiyun void *base;
60*4882a593Smuzhiyun int ret;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun ret = pci_read_config_dword(vdev->pdev, OPREGION_PCI_ADDR, &addr);
63*4882a593Smuzhiyun if (ret)
64*4882a593Smuzhiyun return ret;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (!addr || !(~addr))
67*4882a593Smuzhiyun return -ENODEV;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);
70*4882a593Smuzhiyun if (!base)
71*4882a593Smuzhiyun return -ENOMEM;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (memcmp(base, OPREGION_SIGNATURE, 16)) {
74*4882a593Smuzhiyun memunmap(base);
75*4882a593Smuzhiyun return -EINVAL;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun size = le32_to_cpu(*(__le32 *)(base + 16));
79*4882a593Smuzhiyun if (!size) {
80*4882a593Smuzhiyun memunmap(base);
81*4882a593Smuzhiyun return -EINVAL;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun size *= 1024; /* In KB */
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if (size != OPREGION_SIZE) {
87*4882a593Smuzhiyun memunmap(base);
88*4882a593Smuzhiyun base = memremap(addr, size, MEMREMAP_WB);
89*4882a593Smuzhiyun if (!base)
90*4882a593Smuzhiyun return -ENOMEM;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun ret = vfio_pci_register_dev_region(vdev,
94*4882a593Smuzhiyun PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
95*4882a593Smuzhiyun VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION,
96*4882a593Smuzhiyun &vfio_pci_igd_regops, size, VFIO_REGION_INFO_FLAG_READ, base);
97*4882a593Smuzhiyun if (ret) {
98*4882a593Smuzhiyun memunmap(base);
99*4882a593Smuzhiyun return ret;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* Fill vconfig with the hw value and virtualize register */
103*4882a593Smuzhiyun *dwordp = cpu_to_le32(addr);
104*4882a593Smuzhiyun memset(vdev->pci_config_map + OPREGION_PCI_ADDR,
105*4882a593Smuzhiyun PCI_CAP_ID_INVALID_VIRT, 4);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return ret;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
vfio_pci_igd_cfg_rw(struct vfio_pci_device * vdev,char __user * buf,size_t count,loff_t * ppos,bool iswrite)110*4882a593Smuzhiyun static size_t vfio_pci_igd_cfg_rw(struct vfio_pci_device *vdev,
111*4882a593Smuzhiyun char __user *buf, size_t count, loff_t *ppos,
112*4882a593Smuzhiyun bool iswrite)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) - VFIO_PCI_NUM_REGIONS;
115*4882a593Smuzhiyun struct pci_dev *pdev = vdev->region[i].data;
116*4882a593Smuzhiyun loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
117*4882a593Smuzhiyun size_t size;
118*4882a593Smuzhiyun int ret;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun if (pos >= vdev->region[i].size || iswrite)
121*4882a593Smuzhiyun return -EINVAL;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun size = count = min(count, (size_t)(vdev->region[i].size - pos));
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun if ((pos & 1) && size) {
126*4882a593Smuzhiyun u8 val;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun ret = pci_user_read_config_byte(pdev, pos, &val);
129*4882a593Smuzhiyun if (ret)
130*4882a593Smuzhiyun return pcibios_err_to_errno(ret);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun if (copy_to_user(buf + count - size, &val, 1))
133*4882a593Smuzhiyun return -EFAULT;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun pos++;
136*4882a593Smuzhiyun size--;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if ((pos & 3) && size > 2) {
140*4882a593Smuzhiyun u16 val;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun ret = pci_user_read_config_word(pdev, pos, &val);
143*4882a593Smuzhiyun if (ret)
144*4882a593Smuzhiyun return pcibios_err_to_errno(ret);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun val = cpu_to_le16(val);
147*4882a593Smuzhiyun if (copy_to_user(buf + count - size, &val, 2))
148*4882a593Smuzhiyun return -EFAULT;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun pos += 2;
151*4882a593Smuzhiyun size -= 2;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun while (size > 3) {
155*4882a593Smuzhiyun u32 val;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun ret = pci_user_read_config_dword(pdev, pos, &val);
158*4882a593Smuzhiyun if (ret)
159*4882a593Smuzhiyun return pcibios_err_to_errno(ret);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun val = cpu_to_le32(val);
162*4882a593Smuzhiyun if (copy_to_user(buf + count - size, &val, 4))
163*4882a593Smuzhiyun return -EFAULT;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun pos += 4;
166*4882a593Smuzhiyun size -= 4;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun while (size >= 2) {
170*4882a593Smuzhiyun u16 val;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun ret = pci_user_read_config_word(pdev, pos, &val);
173*4882a593Smuzhiyun if (ret)
174*4882a593Smuzhiyun return pcibios_err_to_errno(ret);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun val = cpu_to_le16(val);
177*4882a593Smuzhiyun if (copy_to_user(buf + count - size, &val, 2))
178*4882a593Smuzhiyun return -EFAULT;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun pos += 2;
181*4882a593Smuzhiyun size -= 2;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun while (size) {
185*4882a593Smuzhiyun u8 val;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun ret = pci_user_read_config_byte(pdev, pos, &val);
188*4882a593Smuzhiyun if (ret)
189*4882a593Smuzhiyun return pcibios_err_to_errno(ret);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun if (copy_to_user(buf + count - size, &val, 1))
192*4882a593Smuzhiyun return -EFAULT;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun pos++;
195*4882a593Smuzhiyun size--;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun *ppos += count;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return count;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
vfio_pci_igd_cfg_release(struct vfio_pci_device * vdev,struct vfio_pci_region * region)203*4882a593Smuzhiyun static void vfio_pci_igd_cfg_release(struct vfio_pci_device *vdev,
204*4882a593Smuzhiyun struct vfio_pci_region *region)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun struct pci_dev *pdev = region->data;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun pci_dev_put(pdev);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static const struct vfio_pci_regops vfio_pci_igd_cfg_regops = {
212*4882a593Smuzhiyun .rw = vfio_pci_igd_cfg_rw,
213*4882a593Smuzhiyun .release = vfio_pci_igd_cfg_release,
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun
vfio_pci_igd_cfg_init(struct vfio_pci_device * vdev)216*4882a593Smuzhiyun static int vfio_pci_igd_cfg_init(struct vfio_pci_device *vdev)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun struct pci_dev *host_bridge, *lpc_bridge;
219*4882a593Smuzhiyun int ret;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun host_bridge = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
222*4882a593Smuzhiyun if (!host_bridge)
223*4882a593Smuzhiyun return -ENODEV;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun if (host_bridge->vendor != PCI_VENDOR_ID_INTEL ||
226*4882a593Smuzhiyun host_bridge->class != (PCI_CLASS_BRIDGE_HOST << 8)) {
227*4882a593Smuzhiyun pci_dev_put(host_bridge);
228*4882a593Smuzhiyun return -EINVAL;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun ret = vfio_pci_register_dev_region(vdev,
232*4882a593Smuzhiyun PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
233*4882a593Smuzhiyun VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG,
234*4882a593Smuzhiyun &vfio_pci_igd_cfg_regops, host_bridge->cfg_size,
235*4882a593Smuzhiyun VFIO_REGION_INFO_FLAG_READ, host_bridge);
236*4882a593Smuzhiyun if (ret) {
237*4882a593Smuzhiyun pci_dev_put(host_bridge);
238*4882a593Smuzhiyun return ret;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun lpc_bridge = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0x1f, 0));
242*4882a593Smuzhiyun if (!lpc_bridge)
243*4882a593Smuzhiyun return -ENODEV;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (lpc_bridge->vendor != PCI_VENDOR_ID_INTEL ||
246*4882a593Smuzhiyun lpc_bridge->class != (PCI_CLASS_BRIDGE_ISA << 8)) {
247*4882a593Smuzhiyun pci_dev_put(lpc_bridge);
248*4882a593Smuzhiyun return -EINVAL;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun ret = vfio_pci_register_dev_region(vdev,
252*4882a593Smuzhiyun PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
253*4882a593Smuzhiyun VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG,
254*4882a593Smuzhiyun &vfio_pci_igd_cfg_regops, lpc_bridge->cfg_size,
255*4882a593Smuzhiyun VFIO_REGION_INFO_FLAG_READ, lpc_bridge);
256*4882a593Smuzhiyun if (ret) {
257*4882a593Smuzhiyun pci_dev_put(lpc_bridge);
258*4882a593Smuzhiyun return ret;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun return 0;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
vfio_pci_igd_init(struct vfio_pci_device * vdev)264*4882a593Smuzhiyun int vfio_pci_igd_init(struct vfio_pci_device *vdev)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun int ret;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun ret = vfio_pci_igd_opregion_init(vdev);
269*4882a593Smuzhiyun if (ret)
270*4882a593Smuzhiyun return ret;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun ret = vfio_pci_igd_cfg_init(vdev);
273*4882a593Smuzhiyun if (ret)
274*4882a593Smuzhiyun return ret;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun return 0;
277*4882a593Smuzhiyun }
278