1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Intel IFC VF NIC driver for virtio dataplane offloading 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Intel Corporation. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Zhu Lingshan <lingshan.zhu@intel.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _IFCVF_H_ 12*4882a593Smuzhiyun #define _IFCVF_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/pci.h> 15*4882a593Smuzhiyun #include <linux/pci_regs.h> 16*4882a593Smuzhiyun #include <linux/vdpa.h> 17*4882a593Smuzhiyun #include <uapi/linux/virtio_net.h> 18*4882a593Smuzhiyun #include <uapi/linux/virtio_config.h> 19*4882a593Smuzhiyun #include <uapi/linux/virtio_pci.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define IFCVF_VENDOR_ID 0x1AF4 22*4882a593Smuzhiyun #define IFCVF_DEVICE_ID 0x1041 23*4882a593Smuzhiyun #define IFCVF_SUBSYS_VENDOR_ID 0x8086 24*4882a593Smuzhiyun #define IFCVF_SUBSYS_DEVICE_ID 0x001A 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define IFCVF_SUPPORTED_FEATURES \ 27*4882a593Smuzhiyun ((1ULL << VIRTIO_NET_F_MAC) | \ 28*4882a593Smuzhiyun (1ULL << VIRTIO_F_ANY_LAYOUT) | \ 29*4882a593Smuzhiyun (1ULL << VIRTIO_F_VERSION_1) | \ 30*4882a593Smuzhiyun (1ULL << VIRTIO_NET_F_STATUS) | \ 31*4882a593Smuzhiyun (1ULL << VIRTIO_F_ORDER_PLATFORM) | \ 32*4882a593Smuzhiyun (1ULL << VIRTIO_F_ACCESS_PLATFORM) | \ 33*4882a593Smuzhiyun (1ULL << VIRTIO_NET_F_MRG_RXBUF)) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Only one queue pair for now. */ 36*4882a593Smuzhiyun #define IFCVF_MAX_QUEUE_PAIRS 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define IFCVF_QUEUE_ALIGNMENT PAGE_SIZE 39*4882a593Smuzhiyun #define IFCVF_QUEUE_MAX 32768 40*4882a593Smuzhiyun #define IFCVF_MSI_CONFIG_OFF 0 41*4882a593Smuzhiyun #define IFCVF_MSI_QUEUE_OFF 1 42*4882a593Smuzhiyun #define IFCVF_PCI_MAX_RESOURCE 6 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define IFCVF_LM_CFG_SIZE 0x40 45*4882a593Smuzhiyun #define IFCVF_LM_RING_STATE_OFFSET 0x20 46*4882a593Smuzhiyun #define IFCVF_LM_BAR 4 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define IFCVF_ERR(pdev, fmt, ...) dev_err(&pdev->dev, fmt, ##__VA_ARGS__) 49*4882a593Smuzhiyun #define IFCVF_DBG(pdev, fmt, ...) dev_dbg(&pdev->dev, fmt, ##__VA_ARGS__) 50*4882a593Smuzhiyun #define IFCVF_INFO(pdev, fmt, ...) dev_info(&pdev->dev, fmt, ##__VA_ARGS__) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define ifcvf_private_to_vf(adapter) \ 53*4882a593Smuzhiyun (&((struct ifcvf_adapter *)adapter)->vf) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define IFCVF_MAX_INTR (IFCVF_MAX_QUEUE_PAIRS * 2 + 1) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct vring_info { 58*4882a593Smuzhiyun u64 desc; 59*4882a593Smuzhiyun u64 avail; 60*4882a593Smuzhiyun u64 used; 61*4882a593Smuzhiyun u16 size; 62*4882a593Smuzhiyun u16 last_avail_idx; 63*4882a593Smuzhiyun bool ready; 64*4882a593Smuzhiyun void __iomem *notify_addr; 65*4882a593Smuzhiyun u32 irq; 66*4882a593Smuzhiyun struct vdpa_callback cb; 67*4882a593Smuzhiyun char msix_name[256]; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct ifcvf_hw { 71*4882a593Smuzhiyun u8 __iomem *isr; 72*4882a593Smuzhiyun /* Live migration */ 73*4882a593Smuzhiyun u8 __iomem *lm_cfg; 74*4882a593Smuzhiyun u16 nr_vring; 75*4882a593Smuzhiyun /* Notification bar number */ 76*4882a593Smuzhiyun u8 notify_bar; 77*4882a593Smuzhiyun /* Notificaiton bar address */ 78*4882a593Smuzhiyun void __iomem *notify_base; 79*4882a593Smuzhiyun u32 notify_off_multiplier; 80*4882a593Smuzhiyun u64 req_features; 81*4882a593Smuzhiyun struct virtio_pci_common_cfg __iomem *common_cfg; 82*4882a593Smuzhiyun void __iomem *net_cfg; 83*4882a593Smuzhiyun struct vring_info vring[IFCVF_MAX_QUEUE_PAIRS * 2]; 84*4882a593Smuzhiyun void __iomem * const *base; 85*4882a593Smuzhiyun char config_msix_name[256]; 86*4882a593Smuzhiyun struct vdpa_callback config_cb; 87*4882a593Smuzhiyun unsigned int config_irq; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun struct ifcvf_adapter { 91*4882a593Smuzhiyun struct vdpa_device vdpa; 92*4882a593Smuzhiyun struct pci_dev *pdev; 93*4882a593Smuzhiyun struct ifcvf_hw vf; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct ifcvf_vring_lm_cfg { 97*4882a593Smuzhiyun u32 idx_addr[2]; 98*4882a593Smuzhiyun u8 reserved[IFCVF_LM_CFG_SIZE - 8]; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct ifcvf_lm_cfg { 102*4882a593Smuzhiyun u8 reserved[IFCVF_LM_RING_STATE_OFFSET]; 103*4882a593Smuzhiyun struct ifcvf_vring_lm_cfg vring_lm_cfg[IFCVF_MAX_QUEUE_PAIRS]; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun int ifcvf_init_hw(struct ifcvf_hw *hw, struct pci_dev *dev); 107*4882a593Smuzhiyun int ifcvf_start_hw(struct ifcvf_hw *hw); 108*4882a593Smuzhiyun void ifcvf_stop_hw(struct ifcvf_hw *hw); 109*4882a593Smuzhiyun void ifcvf_notify_queue(struct ifcvf_hw *hw, u16 qid); 110*4882a593Smuzhiyun void ifcvf_read_net_config(struct ifcvf_hw *hw, u64 offset, 111*4882a593Smuzhiyun void *dst, int length); 112*4882a593Smuzhiyun void ifcvf_write_net_config(struct ifcvf_hw *hw, u64 offset, 113*4882a593Smuzhiyun const void *src, int length); 114*4882a593Smuzhiyun u8 ifcvf_get_status(struct ifcvf_hw *hw); 115*4882a593Smuzhiyun void ifcvf_set_status(struct ifcvf_hw *hw, u8 status); 116*4882a593Smuzhiyun void io_write64_twopart(u64 val, u32 *lo, u32 *hi); 117*4882a593Smuzhiyun void ifcvf_reset(struct ifcvf_hw *hw); 118*4882a593Smuzhiyun u64 ifcvf_get_features(struct ifcvf_hw *hw); 119*4882a593Smuzhiyun u16 ifcvf_get_vq_state(struct ifcvf_hw *hw, u16 qid); 120*4882a593Smuzhiyun int ifcvf_set_vq_state(struct ifcvf_hw *hw, u16 qid, u16 num); 121*4882a593Smuzhiyun struct ifcvf_adapter *vf_to_adapter(struct ifcvf_hw *hw); 122*4882a593Smuzhiyun #endif /* _IFCVF_H_ */ 123