1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel IFC VF NIC driver for virtio dataplane offloading
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2020 Intel Corporation.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Zhu Lingshan <lingshan.zhu@intel.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "ifcvf_base.h"
12*4882a593Smuzhiyun
ifc_ioread8(u8 __iomem * addr)13*4882a593Smuzhiyun static inline u8 ifc_ioread8(u8 __iomem *addr)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun return ioread8(addr);
16*4882a593Smuzhiyun }
ifc_ioread16(__le16 __iomem * addr)17*4882a593Smuzhiyun static inline u16 ifc_ioread16 (__le16 __iomem *addr)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun return ioread16(addr);
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun
ifc_ioread32(__le32 __iomem * addr)22*4882a593Smuzhiyun static inline u32 ifc_ioread32(__le32 __iomem *addr)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun return ioread32(addr);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
ifc_iowrite8(u8 value,u8 __iomem * addr)27*4882a593Smuzhiyun static inline void ifc_iowrite8(u8 value, u8 __iomem *addr)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun iowrite8(value, addr);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
ifc_iowrite16(u16 value,__le16 __iomem * addr)32*4882a593Smuzhiyun static inline void ifc_iowrite16(u16 value, __le16 __iomem *addr)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun iowrite16(value, addr);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
ifc_iowrite32(u32 value,__le32 __iomem * addr)37*4882a593Smuzhiyun static inline void ifc_iowrite32(u32 value, __le32 __iomem *addr)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun iowrite32(value, addr);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
ifc_iowrite64_twopart(u64 val,__le32 __iomem * lo,__le32 __iomem * hi)42*4882a593Smuzhiyun static void ifc_iowrite64_twopart(u64 val,
43*4882a593Smuzhiyun __le32 __iomem *lo, __le32 __iomem *hi)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun ifc_iowrite32((u32)val, lo);
46*4882a593Smuzhiyun ifc_iowrite32(val >> 32, hi);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
vf_to_adapter(struct ifcvf_hw * hw)49*4882a593Smuzhiyun struct ifcvf_adapter *vf_to_adapter(struct ifcvf_hw *hw)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun return container_of(hw, struct ifcvf_adapter, vf);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
get_cap_addr(struct ifcvf_hw * hw,struct virtio_pci_cap * cap)54*4882a593Smuzhiyun static void __iomem *get_cap_addr(struct ifcvf_hw *hw,
55*4882a593Smuzhiyun struct virtio_pci_cap *cap)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct ifcvf_adapter *ifcvf;
58*4882a593Smuzhiyun struct pci_dev *pdev;
59*4882a593Smuzhiyun u32 length, offset;
60*4882a593Smuzhiyun u8 bar;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun length = le32_to_cpu(cap->length);
63*4882a593Smuzhiyun offset = le32_to_cpu(cap->offset);
64*4882a593Smuzhiyun bar = cap->bar;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun ifcvf= vf_to_adapter(hw);
67*4882a593Smuzhiyun pdev = ifcvf->pdev;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if (bar >= IFCVF_PCI_MAX_RESOURCE) {
70*4882a593Smuzhiyun IFCVF_DBG(pdev,
71*4882a593Smuzhiyun "Invalid bar number %u to get capabilities\n", bar);
72*4882a593Smuzhiyun return NULL;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (offset + length > pci_resource_len(pdev, bar)) {
76*4882a593Smuzhiyun IFCVF_DBG(pdev,
77*4882a593Smuzhiyun "offset(%u) + len(%u) overflows bar%u's capability\n",
78*4882a593Smuzhiyun offset, length, bar);
79*4882a593Smuzhiyun return NULL;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return hw->base[bar] + offset;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
ifcvf_read_config_range(struct pci_dev * dev,uint32_t * val,int size,int where)85*4882a593Smuzhiyun static int ifcvf_read_config_range(struct pci_dev *dev,
86*4882a593Smuzhiyun uint32_t *val, int size, int where)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun int ret, i;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun for (i = 0; i < size; i += 4) {
91*4882a593Smuzhiyun ret = pci_read_config_dword(dev, where + i, val + i / 4);
92*4882a593Smuzhiyun if (ret < 0)
93*4882a593Smuzhiyun return ret;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
ifcvf_init_hw(struct ifcvf_hw * hw,struct pci_dev * pdev)99*4882a593Smuzhiyun int ifcvf_init_hw(struct ifcvf_hw *hw, struct pci_dev *pdev)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct virtio_pci_cap cap;
102*4882a593Smuzhiyun u16 notify_off;
103*4882a593Smuzhiyun int ret;
104*4882a593Smuzhiyun u8 pos;
105*4882a593Smuzhiyun u32 i;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun ret = pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &pos);
108*4882a593Smuzhiyun if (ret < 0) {
109*4882a593Smuzhiyun IFCVF_ERR(pdev, "Failed to read PCI capability list\n");
110*4882a593Smuzhiyun return -EIO;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun while (pos) {
114*4882a593Smuzhiyun ret = ifcvf_read_config_range(pdev, (u32 *)&cap,
115*4882a593Smuzhiyun sizeof(cap), pos);
116*4882a593Smuzhiyun if (ret < 0) {
117*4882a593Smuzhiyun IFCVF_ERR(pdev,
118*4882a593Smuzhiyun "Failed to get PCI capability at %x\n", pos);
119*4882a593Smuzhiyun break;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun if (cap.cap_vndr != PCI_CAP_ID_VNDR)
123*4882a593Smuzhiyun goto next;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun switch (cap.cfg_type) {
126*4882a593Smuzhiyun case VIRTIO_PCI_CAP_COMMON_CFG:
127*4882a593Smuzhiyun hw->common_cfg = get_cap_addr(hw, &cap);
128*4882a593Smuzhiyun IFCVF_DBG(pdev, "hw->common_cfg = %p\n",
129*4882a593Smuzhiyun hw->common_cfg);
130*4882a593Smuzhiyun break;
131*4882a593Smuzhiyun case VIRTIO_PCI_CAP_NOTIFY_CFG:
132*4882a593Smuzhiyun pci_read_config_dword(pdev, pos + sizeof(cap),
133*4882a593Smuzhiyun &hw->notify_off_multiplier);
134*4882a593Smuzhiyun hw->notify_bar = cap.bar;
135*4882a593Smuzhiyun hw->notify_base = get_cap_addr(hw, &cap);
136*4882a593Smuzhiyun IFCVF_DBG(pdev, "hw->notify_base = %p\n",
137*4882a593Smuzhiyun hw->notify_base);
138*4882a593Smuzhiyun break;
139*4882a593Smuzhiyun case VIRTIO_PCI_CAP_ISR_CFG:
140*4882a593Smuzhiyun hw->isr = get_cap_addr(hw, &cap);
141*4882a593Smuzhiyun IFCVF_DBG(pdev, "hw->isr = %p\n", hw->isr);
142*4882a593Smuzhiyun break;
143*4882a593Smuzhiyun case VIRTIO_PCI_CAP_DEVICE_CFG:
144*4882a593Smuzhiyun hw->net_cfg = get_cap_addr(hw, &cap);
145*4882a593Smuzhiyun IFCVF_DBG(pdev, "hw->net_cfg = %p\n", hw->net_cfg);
146*4882a593Smuzhiyun break;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun next:
150*4882a593Smuzhiyun pos = cap.cap_next;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (hw->common_cfg == NULL || hw->notify_base == NULL ||
154*4882a593Smuzhiyun hw->isr == NULL || hw->net_cfg == NULL) {
155*4882a593Smuzhiyun IFCVF_ERR(pdev, "Incomplete PCI capabilities\n");
156*4882a593Smuzhiyun return -EIO;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun for (i = 0; i < IFCVF_MAX_QUEUE_PAIRS * 2; i++) {
160*4882a593Smuzhiyun ifc_iowrite16(i, &hw->common_cfg->queue_select);
161*4882a593Smuzhiyun notify_off = ifc_ioread16(&hw->common_cfg->queue_notify_off);
162*4882a593Smuzhiyun hw->vring[i].notify_addr = hw->notify_base +
163*4882a593Smuzhiyun notify_off * hw->notify_off_multiplier;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun hw->lm_cfg = hw->base[IFCVF_LM_BAR];
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun IFCVF_DBG(pdev,
169*4882a593Smuzhiyun "PCI capability mapping: common cfg: %p, notify base: %p\n, isr cfg: %p, device cfg: %p, multiplier: %u\n",
170*4882a593Smuzhiyun hw->common_cfg, hw->notify_base, hw->isr,
171*4882a593Smuzhiyun hw->net_cfg, hw->notify_off_multiplier);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return 0;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
ifcvf_get_status(struct ifcvf_hw * hw)176*4882a593Smuzhiyun u8 ifcvf_get_status(struct ifcvf_hw *hw)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun return ifc_ioread8(&hw->common_cfg->device_status);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
ifcvf_set_status(struct ifcvf_hw * hw,u8 status)181*4882a593Smuzhiyun void ifcvf_set_status(struct ifcvf_hw *hw, u8 status)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun ifc_iowrite8(status, &hw->common_cfg->device_status);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
ifcvf_reset(struct ifcvf_hw * hw)186*4882a593Smuzhiyun void ifcvf_reset(struct ifcvf_hw *hw)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun hw->config_cb.callback = NULL;
189*4882a593Smuzhiyun hw->config_cb.private = NULL;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun ifcvf_set_status(hw, 0);
192*4882a593Smuzhiyun /* flush set_status, make sure VF is stopped, reset */
193*4882a593Smuzhiyun ifcvf_get_status(hw);
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
ifcvf_add_status(struct ifcvf_hw * hw,u8 status)196*4882a593Smuzhiyun static void ifcvf_add_status(struct ifcvf_hw *hw, u8 status)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun if (status != 0)
199*4882a593Smuzhiyun status |= ifcvf_get_status(hw);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun ifcvf_set_status(hw, status);
202*4882a593Smuzhiyun ifcvf_get_status(hw);
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
ifcvf_get_features(struct ifcvf_hw * hw)205*4882a593Smuzhiyun u64 ifcvf_get_features(struct ifcvf_hw *hw)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
208*4882a593Smuzhiyun u32 features_lo, features_hi;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun ifc_iowrite32(0, &cfg->device_feature_select);
211*4882a593Smuzhiyun features_lo = ifc_ioread32(&cfg->device_feature);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun ifc_iowrite32(1, &cfg->device_feature_select);
214*4882a593Smuzhiyun features_hi = ifc_ioread32(&cfg->device_feature);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun return ((u64)features_hi << 32) | features_lo;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
ifcvf_read_net_config(struct ifcvf_hw * hw,u64 offset,void * dst,int length)219*4882a593Smuzhiyun void ifcvf_read_net_config(struct ifcvf_hw *hw, u64 offset,
220*4882a593Smuzhiyun void *dst, int length)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun u8 old_gen, new_gen, *p;
223*4882a593Smuzhiyun int i;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun WARN_ON(offset + length > sizeof(struct virtio_net_config));
226*4882a593Smuzhiyun do {
227*4882a593Smuzhiyun old_gen = ifc_ioread8(&hw->common_cfg->config_generation);
228*4882a593Smuzhiyun p = dst;
229*4882a593Smuzhiyun for (i = 0; i < length; i++)
230*4882a593Smuzhiyun *p++ = ifc_ioread8(hw->net_cfg + offset + i);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun new_gen = ifc_ioread8(&hw->common_cfg->config_generation);
233*4882a593Smuzhiyun } while (old_gen != new_gen);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun
ifcvf_write_net_config(struct ifcvf_hw * hw,u64 offset,const void * src,int length)236*4882a593Smuzhiyun void ifcvf_write_net_config(struct ifcvf_hw *hw, u64 offset,
237*4882a593Smuzhiyun const void *src, int length)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun const u8 *p;
240*4882a593Smuzhiyun int i;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun p = src;
243*4882a593Smuzhiyun WARN_ON(offset + length > sizeof(struct virtio_net_config));
244*4882a593Smuzhiyun for (i = 0; i < length; i++)
245*4882a593Smuzhiyun ifc_iowrite8(*p++, hw->net_cfg + offset + i);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
ifcvf_set_features(struct ifcvf_hw * hw,u64 features)248*4882a593Smuzhiyun static void ifcvf_set_features(struct ifcvf_hw *hw, u64 features)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun struct virtio_pci_common_cfg __iomem *cfg = hw->common_cfg;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun ifc_iowrite32(0, &cfg->guest_feature_select);
253*4882a593Smuzhiyun ifc_iowrite32((u32)features, &cfg->guest_feature);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun ifc_iowrite32(1, &cfg->guest_feature_select);
256*4882a593Smuzhiyun ifc_iowrite32(features >> 32, &cfg->guest_feature);
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
ifcvf_config_features(struct ifcvf_hw * hw)259*4882a593Smuzhiyun static int ifcvf_config_features(struct ifcvf_hw *hw)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun struct ifcvf_adapter *ifcvf;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun ifcvf = vf_to_adapter(hw);
264*4882a593Smuzhiyun ifcvf_set_features(hw, hw->req_features);
265*4882a593Smuzhiyun ifcvf_add_status(hw, VIRTIO_CONFIG_S_FEATURES_OK);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if (!(ifcvf_get_status(hw) & VIRTIO_CONFIG_S_FEATURES_OK)) {
268*4882a593Smuzhiyun IFCVF_ERR(ifcvf->pdev, "Failed to set FEATURES_OK status\n");
269*4882a593Smuzhiyun return -EIO;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun return 0;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
ifcvf_get_vq_state(struct ifcvf_hw * hw,u16 qid)275*4882a593Smuzhiyun u16 ifcvf_get_vq_state(struct ifcvf_hw *hw, u16 qid)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun struct ifcvf_lm_cfg __iomem *ifcvf_lm;
278*4882a593Smuzhiyun void __iomem *avail_idx_addr;
279*4882a593Smuzhiyun u16 last_avail_idx;
280*4882a593Smuzhiyun u32 q_pair_id;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun ifcvf_lm = (struct ifcvf_lm_cfg __iomem *)hw->lm_cfg;
283*4882a593Smuzhiyun q_pair_id = qid / (IFCVF_MAX_QUEUE_PAIRS * 2);
284*4882a593Smuzhiyun avail_idx_addr = &ifcvf_lm->vring_lm_cfg[q_pair_id].idx_addr[qid % 2];
285*4882a593Smuzhiyun last_avail_idx = ifc_ioread16(avail_idx_addr);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun return last_avail_idx;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
ifcvf_set_vq_state(struct ifcvf_hw * hw,u16 qid,u16 num)290*4882a593Smuzhiyun int ifcvf_set_vq_state(struct ifcvf_hw *hw, u16 qid, u16 num)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun struct ifcvf_lm_cfg __iomem *ifcvf_lm;
293*4882a593Smuzhiyun void __iomem *avail_idx_addr;
294*4882a593Smuzhiyun u32 q_pair_id;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun ifcvf_lm = (struct ifcvf_lm_cfg __iomem *)hw->lm_cfg;
297*4882a593Smuzhiyun q_pair_id = qid / (IFCVF_MAX_QUEUE_PAIRS * 2);
298*4882a593Smuzhiyun avail_idx_addr = &ifcvf_lm->vring_lm_cfg[q_pair_id].idx_addr[qid % 2];
299*4882a593Smuzhiyun hw->vring[qid].last_avail_idx = num;
300*4882a593Smuzhiyun ifc_iowrite16(num, avail_idx_addr);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun return 0;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
ifcvf_hw_enable(struct ifcvf_hw * hw)305*4882a593Smuzhiyun static int ifcvf_hw_enable(struct ifcvf_hw *hw)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun struct virtio_pci_common_cfg __iomem *cfg;
308*4882a593Smuzhiyun struct ifcvf_adapter *ifcvf;
309*4882a593Smuzhiyun u32 i;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun ifcvf = vf_to_adapter(hw);
312*4882a593Smuzhiyun cfg = hw->common_cfg;
313*4882a593Smuzhiyun ifc_iowrite16(IFCVF_MSI_CONFIG_OFF, &cfg->msix_config);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun if (ifc_ioread16(&cfg->msix_config) == VIRTIO_MSI_NO_VECTOR) {
316*4882a593Smuzhiyun IFCVF_ERR(ifcvf->pdev, "No msix vector for device config\n");
317*4882a593Smuzhiyun return -EINVAL;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun for (i = 0; i < hw->nr_vring; i++) {
321*4882a593Smuzhiyun if (!hw->vring[i].ready)
322*4882a593Smuzhiyun break;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun ifc_iowrite16(i, &cfg->queue_select);
325*4882a593Smuzhiyun ifc_iowrite64_twopart(hw->vring[i].desc, &cfg->queue_desc_lo,
326*4882a593Smuzhiyun &cfg->queue_desc_hi);
327*4882a593Smuzhiyun ifc_iowrite64_twopart(hw->vring[i].avail, &cfg->queue_avail_lo,
328*4882a593Smuzhiyun &cfg->queue_avail_hi);
329*4882a593Smuzhiyun ifc_iowrite64_twopart(hw->vring[i].used, &cfg->queue_used_lo,
330*4882a593Smuzhiyun &cfg->queue_used_hi);
331*4882a593Smuzhiyun ifc_iowrite16(hw->vring[i].size, &cfg->queue_size);
332*4882a593Smuzhiyun ifc_iowrite16(i + IFCVF_MSI_QUEUE_OFF, &cfg->queue_msix_vector);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun if (ifc_ioread16(&cfg->queue_msix_vector) ==
335*4882a593Smuzhiyun VIRTIO_MSI_NO_VECTOR) {
336*4882a593Smuzhiyun IFCVF_ERR(ifcvf->pdev,
337*4882a593Smuzhiyun "No msix vector for queue %u\n", i);
338*4882a593Smuzhiyun return -EINVAL;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun ifcvf_set_vq_state(hw, i, hw->vring[i].last_avail_idx);
342*4882a593Smuzhiyun ifc_iowrite16(1, &cfg->queue_enable);
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun return 0;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
ifcvf_hw_disable(struct ifcvf_hw * hw)348*4882a593Smuzhiyun static void ifcvf_hw_disable(struct ifcvf_hw *hw)
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun struct virtio_pci_common_cfg __iomem *cfg;
351*4882a593Smuzhiyun u32 i;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun cfg = hw->common_cfg;
354*4882a593Smuzhiyun ifc_iowrite16(VIRTIO_MSI_NO_VECTOR, &cfg->msix_config);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun for (i = 0; i < hw->nr_vring; i++) {
357*4882a593Smuzhiyun ifc_iowrite16(i, &cfg->queue_select);
358*4882a593Smuzhiyun ifc_iowrite16(VIRTIO_MSI_NO_VECTOR, &cfg->queue_msix_vector);
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun ifc_ioread16(&cfg->queue_msix_vector);
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
ifcvf_start_hw(struct ifcvf_hw * hw)364*4882a593Smuzhiyun int ifcvf_start_hw(struct ifcvf_hw *hw)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun ifcvf_reset(hw);
367*4882a593Smuzhiyun ifcvf_add_status(hw, VIRTIO_CONFIG_S_ACKNOWLEDGE);
368*4882a593Smuzhiyun ifcvf_add_status(hw, VIRTIO_CONFIG_S_DRIVER);
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (ifcvf_config_features(hw) < 0)
371*4882a593Smuzhiyun return -EINVAL;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun if (ifcvf_hw_enable(hw) < 0)
374*4882a593Smuzhiyun return -EINVAL;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun ifcvf_add_status(hw, VIRTIO_CONFIG_S_DRIVER_OK);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun return 0;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
ifcvf_stop_hw(struct ifcvf_hw * hw)381*4882a593Smuzhiyun void ifcvf_stop_hw(struct ifcvf_hw *hw)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun ifcvf_hw_disable(hw);
384*4882a593Smuzhiyun ifcvf_reset(hw);
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
ifcvf_notify_queue(struct ifcvf_hw * hw,u16 qid)387*4882a593Smuzhiyun void ifcvf_notify_queue(struct ifcvf_hw *hw, u16 qid)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun ifc_iowrite16(qid, hw->vring[qid].notify_addr);
390*4882a593Smuzhiyun }
391