1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 3*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 4*4882a593Smuzhiyun * the Free Software Foundation; either version 2 of the License, or 5*4882a593Smuzhiyun * (at your option) any later version. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 8*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 9*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10*4882a593Smuzhiyun * GNU General Public License for more details. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 13*4882a593Smuzhiyun * along with this program; if not, write to the Free Software 14*4882a593Smuzhiyun * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * CMSPAR, some architectures can't have space and mark parity. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef CMSPAR 22*4882a593Smuzhiyun #define CMSPAR 0 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Major and minor numbers. 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define XR_USB_SERIAL_TTY_MAJOR 266 30*4882a593Smuzhiyun #define XR_USB_SERIAL_TTY_MINORS 32 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * Requests. 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define USB_RT_XR_USB_SERIAL (USB_TYPE_CLASS | USB_RECIP_INTERFACE) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Output control lines. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define XR_USB_SERIAL_CTRL_DTR 0x01 43*4882a593Smuzhiyun #define XR_USB_SERIAL_CTRL_RTS 0x02 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * Input control lines and line errors. 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define XR_USB_SERIAL_CTRL_DCD 0x01 50*4882a593Smuzhiyun #define XR_USB_SERIAL_CTRL_DSR 0x02 51*4882a593Smuzhiyun #define XR_USB_SERIAL_CTRL_BRK 0x04 52*4882a593Smuzhiyun #define XR_USB_SERIAL_CTRL_RI 0x08 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define XR_USB_SERIAL_CTRL_FRAMING 0x10 55*4882a593Smuzhiyun #define XR_USB_SERIAL_CTRL_PARITY 0x20 56*4882a593Smuzhiyun #define XR_USB_SERIAL_CTRL_OVERRUN 0x40 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * Internal driver structures. 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * The only reason to have several buffers is to accommodate assumptions 64*4882a593Smuzhiyun * in line disciplines. They ask for empty space amount, receive our URB size, 65*4882a593Smuzhiyun * and proceed to issue several 1-character writes, assuming they will fit. 66*4882a593Smuzhiyun * The very first write takes a complete URB. Fortunately, this only happens 67*4882a593Smuzhiyun * when processing onlcr, so we only need 2 buffers. These values must be 68*4882a593Smuzhiyun * powers of 2. 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun #define XR_USB_SERIAL_NW 16 71*4882a593Smuzhiyun #define XR_USB_SERIAL_NR 16 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define RAMCTL_BUFFER_PARITY 0x1 74*4882a593Smuzhiyun #define RAMCTL_BUFFER_BREAK 0x2 75*4882a593Smuzhiyun #define RAMCTL_BUFFER_FRAME 0x4 76*4882a593Smuzhiyun #define RAMCTL_BUFFER_OVERRUN 0x8 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct xr_usb_serial_wb { 79*4882a593Smuzhiyun unsigned char *buf; 80*4882a593Smuzhiyun dma_addr_t dmah; 81*4882a593Smuzhiyun int len; 82*4882a593Smuzhiyun int use; 83*4882a593Smuzhiyun struct urb *urb; 84*4882a593Smuzhiyun struct xr_usb_serial *instance; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun struct xr_usb_serial_rb { 88*4882a593Smuzhiyun int size; 89*4882a593Smuzhiyun unsigned char *base; 90*4882a593Smuzhiyun dma_addr_t dma; 91*4882a593Smuzhiyun int index; 92*4882a593Smuzhiyun struct xr_usb_serial *instance; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct reg_addr_map { 96*4882a593Smuzhiyun unsigned int uart_enable_addr; 97*4882a593Smuzhiyun unsigned int uart_format_addr; 98*4882a593Smuzhiyun unsigned int uart_flow_addr; 99*4882a593Smuzhiyun unsigned int uart_loopback_addr; 100*4882a593Smuzhiyun unsigned int uart_xon_char_addr; 101*4882a593Smuzhiyun unsigned int uart_xoff_char_addr; 102*4882a593Smuzhiyun unsigned int uart_gpio_mode_addr; 103*4882a593Smuzhiyun unsigned int uart_gpio_dir_addr; 104*4882a593Smuzhiyun unsigned int uart_gpio_set_addr; 105*4882a593Smuzhiyun unsigned int uart_gpio_clr_addr; 106*4882a593Smuzhiyun unsigned int uart_gpio_status_addr; 107*4882a593Smuzhiyun unsigned int tx_break_addr; 108*4882a593Smuzhiyun unsigned int uart_custom_driver; 109*4882a593Smuzhiyun unsigned int uart_low_latency; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct xr_usb_serial { 113*4882a593Smuzhiyun struct usb_device *dev; /* the corresponding usb device */ 114*4882a593Smuzhiyun struct usb_interface *control; /* control interface */ 115*4882a593Smuzhiyun struct usb_interface *data; /* data interface */ 116*4882a593Smuzhiyun struct tty_port port; /* our tty port data */ 117*4882a593Smuzhiyun struct urb *ctrlurb; /* urbs */ 118*4882a593Smuzhiyun u8 *ctrl_buffer; /* buffers of urbs */ 119*4882a593Smuzhiyun dma_addr_t ctrl_dma; /* dma handles of buffers */ 120*4882a593Smuzhiyun u8 *country_codes; /* country codes from device */ 121*4882a593Smuzhiyun unsigned int country_code_size; /* size of this buffer */ 122*4882a593Smuzhiyun unsigned int country_rel_date; /* release date of version */ 123*4882a593Smuzhiyun struct xr_usb_serial_wb wb[XR_USB_SERIAL_NW]; 124*4882a593Smuzhiyun unsigned long read_urbs_free; 125*4882a593Smuzhiyun struct urb *read_urbs[XR_USB_SERIAL_NR]; 126*4882a593Smuzhiyun struct xr_usb_serial_rb read_buffers[XR_USB_SERIAL_NR]; 127*4882a593Smuzhiyun int rx_buflimit; 128*4882a593Smuzhiyun int rx_endpoint; 129*4882a593Smuzhiyun spinlock_t read_lock; 130*4882a593Smuzhiyun int write_used; /* number of non-empty write buffers */ 131*4882a593Smuzhiyun int transmitting; 132*4882a593Smuzhiyun spinlock_t write_lock; 133*4882a593Smuzhiyun struct mutex mutex; 134*4882a593Smuzhiyun bool disconnected; 135*4882a593Smuzhiyun struct usb_cdc_line_coding line; /* bits, stop, parity */ 136*4882a593Smuzhiyun struct work_struct work; /* work queue entry for line discipline waking up */ 137*4882a593Smuzhiyun unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */ 138*4882a593Smuzhiyun unsigned int ctrlout; /* output control lines (DTR, RTS) */ 139*4882a593Smuzhiyun unsigned int writesize; /* max packet size for the output bulk endpoint */ 140*4882a593Smuzhiyun unsigned int readsize,ctrlsize; /* buffer sizes for freeing */ 141*4882a593Smuzhiyun unsigned int minor; /* xr_usb_serial minor number */ 142*4882a593Smuzhiyun unsigned char clocal; /* termios CLOCAL */ 143*4882a593Smuzhiyun unsigned int ctrl_caps; /* control capabilities from the class specific header */ 144*4882a593Smuzhiyun unsigned int susp_count; /* number of suspended interfaces */ 145*4882a593Smuzhiyun unsigned int combined_interfaces:1; /* control and data collapsed */ 146*4882a593Smuzhiyun unsigned int is_int_ep:1; /* interrupt endpoints contrary to spec used */ 147*4882a593Smuzhiyun unsigned int throttled:1; /* actually throttled */ 148*4882a593Smuzhiyun unsigned int throttle_req:1; /* throttle requested */ 149*4882a593Smuzhiyun u8 bInterval; 150*4882a593Smuzhiyun struct xr_usb_serial_wb *delayed_wb; /* write queued for a device about to be woken */ 151*4882a593Smuzhiyun unsigned int channel; 152*4882a593Smuzhiyun int preciseflags; /* USB: wide mode, TTY: flags per character */ 153*4882a593Smuzhiyun int trans9; /* USB: wide mode, serial 9N1 */ 154*4882a593Smuzhiyun int have_extra_byte; 155*4882a593Smuzhiyun int extra_byte; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun unsigned short DeviceVendor; 158*4882a593Smuzhiyun unsigned short DeviceProduct; 159*4882a593Smuzhiyun struct reg_addr_map reg_map; 160*4882a593Smuzhiyun #ifdef CONFIG_GPIOLIB 161*4882a593Smuzhiyun struct gpio_chip xr_gpio; 162*4882a593Smuzhiyun int rv_gpio_created; 163*4882a593Smuzhiyun #endif 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define CDC_DATA_INTERFACE_TYPE 0x0a 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* constants describing various quirks and errors */ 169*4882a593Smuzhiyun #define NO_UNION_NORMAL 1 170*4882a593Smuzhiyun #define SINGLE_RX_URB 2 171*4882a593Smuzhiyun #define NO_CAP_LINE 4 172*4882a593Smuzhiyun #define NOT_A_MODEM 8 173*4882a593Smuzhiyun #define NO_DATA_INTERFACE 16 174*4882a593Smuzhiyun #define IGNORE_DEVICE 32 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define UART_ENABLE_TX 1 178*4882a593Smuzhiyun #define UART_ENABLE_RX 2 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #define UART_GPIO_CLR_DTR 0x8 181*4882a593Smuzhiyun #define UART_GPIO_SET_DTR 0x8 182*4882a593Smuzhiyun #define UART_GPIO_CLR_RTS 0x20 183*4882a593Smuzhiyun #define UART_GPIO_SET_RTS 0x20 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define LOOPBACK_ENABLE_TX_RX 1 186*4882a593Smuzhiyun #define LOOPBACK_ENABLE_RTS_CTS 2 187*4882a593Smuzhiyun #define LOOPBACK_ENABLE_DTR_DSR 4 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #define UART_FLOW_MODE_NONE 0x0 190*4882a593Smuzhiyun #define UART_FLOW_MODE_HW 0x1 191*4882a593Smuzhiyun #define UART_FLOW_MODE_SW 0x2 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define UART_GPIO_MODE_SEL_GPIO 0x0 194*4882a593Smuzhiyun #define UART_GPIO_MODE_SEL_RTS_CTS 0x1 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define XR2280x_FUNC_MGR_OFFSET 0x40 197*4882a593Smuzhiyun 198