xref: /OK3568_Linux_fs/kernel/drivers/usb/serial/whiteheat.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * USB ConnectTech WhiteHEAT driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *      Copyright (C) 2002
6*4882a593Smuzhiyun  *          Connect Tech Inc.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  *      Copyright (C) 1999, 2000
9*4882a593Smuzhiyun  *          Greg Kroah-Hartman (greg@kroah.com)
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * See Documentation/usb/usb-serial.rst for more information on using this
12*4882a593Smuzhiyun  * driver
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #ifndef __LINUX_USB_SERIAL_WHITEHEAT_H
17*4882a593Smuzhiyun #define __LINUX_USB_SERIAL_WHITEHEAT_H
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /* WhiteHEAT commands */
21*4882a593Smuzhiyun #define WHITEHEAT_OPEN			1	/* open the port */
22*4882a593Smuzhiyun #define WHITEHEAT_CLOSE			2	/* close the port */
23*4882a593Smuzhiyun #define WHITEHEAT_SETUP_PORT		3	/* change port settings */
24*4882a593Smuzhiyun #define WHITEHEAT_SET_RTS		4	/* turn RTS on or off */
25*4882a593Smuzhiyun #define WHITEHEAT_SET_DTR		5	/* turn DTR on or off */
26*4882a593Smuzhiyun #define WHITEHEAT_SET_BREAK		6	/* turn BREAK on or off */
27*4882a593Smuzhiyun #define WHITEHEAT_DUMP			7	/* dump memory */
28*4882a593Smuzhiyun #define WHITEHEAT_STATUS		8	/* get status */
29*4882a593Smuzhiyun #define WHITEHEAT_PURGE			9	/* clear the UART fifos */
30*4882a593Smuzhiyun #define WHITEHEAT_GET_DTR_RTS		10	/* get the state of DTR and RTS
31*4882a593Smuzhiyun 							for a port */
32*4882a593Smuzhiyun #define WHITEHEAT_GET_HW_INFO		11	/* get EEPROM info and
33*4882a593Smuzhiyun 							hardware ID */
34*4882a593Smuzhiyun #define WHITEHEAT_REPORT_TX_DONE	12	/* get the next TX done */
35*4882a593Smuzhiyun #define WHITEHEAT_EVENT			13	/* unsolicited status events */
36*4882a593Smuzhiyun #define WHITEHEAT_ECHO			14	/* send data to the indicated
37*4882a593Smuzhiyun 						   IN endpoint */
38*4882a593Smuzhiyun #define WHITEHEAT_DO_TEST		15	/* perform specified test */
39*4882a593Smuzhiyun #define WHITEHEAT_CMD_COMPLETE		16	/* reply for some commands */
40*4882a593Smuzhiyun #define WHITEHEAT_CMD_FAILURE		17	/* reply for failed commands */
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun  * Commands to the firmware
45*4882a593Smuzhiyun  */
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun  * WHITEHEAT_OPEN
50*4882a593Smuzhiyun  * WHITEHEAT_CLOSE
51*4882a593Smuzhiyun  * WHITEHEAT_STATUS
52*4882a593Smuzhiyun  * WHITEHEAT_GET_DTR_RTS
53*4882a593Smuzhiyun  * WHITEHEAT_REPORT_TX_DONE
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun struct whiteheat_simple {
56*4882a593Smuzhiyun 	__u8	port;	/* port number (1 to N) */
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun  * WHITEHEAT_SETUP_PORT
62*4882a593Smuzhiyun  */
63*4882a593Smuzhiyun #define WHITEHEAT_PAR_NONE	'n'	/* no parity */
64*4882a593Smuzhiyun #define WHITEHEAT_PAR_EVEN	'e'	/* even parity */
65*4882a593Smuzhiyun #define WHITEHEAT_PAR_ODD	'o'	/* odd parity */
66*4882a593Smuzhiyun #define WHITEHEAT_PAR_SPACE	'0'	/* space (force 0) parity */
67*4882a593Smuzhiyun #define WHITEHEAT_PAR_MARK	'1'	/* mark (force 1) parity */
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define WHITEHEAT_SFLOW_NONE	'n'	/* no software flow control */
70*4882a593Smuzhiyun #define WHITEHEAT_SFLOW_RX	'r'	/* XOFF/ON is sent when RX
71*4882a593Smuzhiyun 					   fills/empties */
72*4882a593Smuzhiyun #define WHITEHEAT_SFLOW_TX	't'	/* when received XOFF/ON will
73*4882a593Smuzhiyun 					   stop/start TX */
74*4882a593Smuzhiyun #define WHITEHEAT_SFLOW_RXTX	'b'	/* both SFLOW_RX and SFLOW_TX */
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define WHITEHEAT_HFLOW_NONE		0x00	/* no hardware flow control */
77*4882a593Smuzhiyun #define WHITEHEAT_HFLOW_RTS_TOGGLE	0x01	/* RTS is on during transmit,
78*4882a593Smuzhiyun 						   off otherwise */
79*4882a593Smuzhiyun #define WHITEHEAT_HFLOW_DTR		0x02	/* DTR is off/on when RX
80*4882a593Smuzhiyun 						   fills/empties */
81*4882a593Smuzhiyun #define WHITEHEAT_HFLOW_CTS		0x08	/* when received CTS off/on
82*4882a593Smuzhiyun 						   will stop/start TX */
83*4882a593Smuzhiyun #define WHITEHEAT_HFLOW_DSR		0x10	/* when received DSR off/on
84*4882a593Smuzhiyun 						   will stop/start TX */
85*4882a593Smuzhiyun #define WHITEHEAT_HFLOW_RTS		0x80	/* RTS is off/on when RX
86*4882a593Smuzhiyun 						   fills/empties */
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun struct whiteheat_port_settings {
89*4882a593Smuzhiyun 	__u8	port;		/* port number (1 to N) */
90*4882a593Smuzhiyun 	__le32	baud;		/* any value 7 - 460800, firmware calculates
91*4882a593Smuzhiyun 				   best fit; arrives little endian */
92*4882a593Smuzhiyun 	__u8	bits;		/* 5, 6, 7, or 8 */
93*4882a593Smuzhiyun 	__u8	stop;		/* 1 or 2, default 1 (2 = 1.5 if bits = 5) */
94*4882a593Smuzhiyun 	__u8	parity;		/* see WHITEHEAT_PAR_* above */
95*4882a593Smuzhiyun 	__u8	sflow;		/* see WHITEHEAT_SFLOW_* above */
96*4882a593Smuzhiyun 	__u8	xoff;		/* XOFF byte value */
97*4882a593Smuzhiyun 	__u8	xon;		/* XON byte value */
98*4882a593Smuzhiyun 	__u8	hflow;		/* see WHITEHEAT_HFLOW_* above */
99*4882a593Smuzhiyun 	__u8	lloop;		/* 0/1 turns local loopback mode off/on */
100*4882a593Smuzhiyun } __attribute__ ((packed));
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /*
104*4882a593Smuzhiyun  * WHITEHEAT_SET_RTS
105*4882a593Smuzhiyun  * WHITEHEAT_SET_DTR
106*4882a593Smuzhiyun  * WHITEHEAT_SET_BREAK
107*4882a593Smuzhiyun  */
108*4882a593Smuzhiyun #define WHITEHEAT_RTS_OFF	0x00
109*4882a593Smuzhiyun #define WHITEHEAT_RTS_ON	0x01
110*4882a593Smuzhiyun #define WHITEHEAT_DTR_OFF	0x00
111*4882a593Smuzhiyun #define WHITEHEAT_DTR_ON	0x01
112*4882a593Smuzhiyun #define WHITEHEAT_BREAK_OFF	0x00
113*4882a593Smuzhiyun #define WHITEHEAT_BREAK_ON	0x01
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun struct whiteheat_set_rdb {
116*4882a593Smuzhiyun 	__u8	port;		/* port number (1 to N) */
117*4882a593Smuzhiyun 	__u8	state;		/* 0/1 turns signal off/on */
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /*
122*4882a593Smuzhiyun  * WHITEHEAT_DUMP
123*4882a593Smuzhiyun  */
124*4882a593Smuzhiyun #define WHITEHEAT_DUMP_MEM_DATA		'd'  /* data */
125*4882a593Smuzhiyun #define WHITEHEAT_DUMP_MEM_IDATA	'i'  /* idata */
126*4882a593Smuzhiyun #define WHITEHEAT_DUMP_MEM_BDATA	'b'  /* bdata */
127*4882a593Smuzhiyun #define WHITEHEAT_DUMP_MEM_XDATA	'x'  /* xdata */
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun  * Allowable address ranges (firmware checks address):
131*4882a593Smuzhiyun  * Type DATA:  0x00 - 0xff
132*4882a593Smuzhiyun  * Type IDATA: 0x80 - 0xff
133*4882a593Smuzhiyun  * Type BDATA: 0x20 - 0x2f
134*4882a593Smuzhiyun  * Type XDATA: 0x0000 - 0xffff
135*4882a593Smuzhiyun  *
136*4882a593Smuzhiyun  * B/I/DATA all read the local memory space
137*4882a593Smuzhiyun  * XDATA reads the external memory space
138*4882a593Smuzhiyun  * BDATA returns bits as bytes
139*4882a593Smuzhiyun  *
140*4882a593Smuzhiyun  * NOTE: 0x80 - 0xff (local space) are the Special Function Registers
141*4882a593Smuzhiyun  *       of the 8051, and some have on-read side-effects.
142*4882a593Smuzhiyun  */
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun struct whiteheat_dump {
145*4882a593Smuzhiyun 	__u8	mem_type;	/* see WHITEHEAT_DUMP_* above */
146*4882a593Smuzhiyun 	__u16	addr;		/* address, see restrictions above */
147*4882a593Smuzhiyun 	__u16	length;		/* number of bytes to dump, max 63 bytes */
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun /*
152*4882a593Smuzhiyun  * WHITEHEAT_PURGE
153*4882a593Smuzhiyun  */
154*4882a593Smuzhiyun #define WHITEHEAT_PURGE_RX	0x01	/* purge rx fifos */
155*4882a593Smuzhiyun #define WHITEHEAT_PURGE_TX	0x02	/* purge tx fifos */
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun struct whiteheat_purge {
158*4882a593Smuzhiyun 	__u8	port;		/* port number (1 to N) */
159*4882a593Smuzhiyun 	__u8	what;		/* bit pattern of what to purge */
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun /*
164*4882a593Smuzhiyun  * WHITEHEAT_ECHO
165*4882a593Smuzhiyun  */
166*4882a593Smuzhiyun struct whiteheat_echo {
167*4882a593Smuzhiyun 	__u8	port;		/* port number (1 to N) */
168*4882a593Smuzhiyun 	__u8	length;		/* length of message to echo, max 61 bytes */
169*4882a593Smuzhiyun 	__u8	echo_data[61];	/* data to echo */
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /*
174*4882a593Smuzhiyun  * WHITEHEAT_DO_TEST
175*4882a593Smuzhiyun  */
176*4882a593Smuzhiyun #define WHITEHEAT_TEST_UART_RW		0x01  /* read/write uart registers */
177*4882a593Smuzhiyun #define WHITEHEAT_TEST_UART_INTR	0x02  /* uart interrupt */
178*4882a593Smuzhiyun #define WHITEHEAT_TEST_SETUP_CONT	0x03  /* setup for
179*4882a593Smuzhiyun 						PORT_CONT/PORT_DISCONT */
180*4882a593Smuzhiyun #define WHITEHEAT_TEST_PORT_CONT	0x04  /* port connect */
181*4882a593Smuzhiyun #define WHITEHEAT_TEST_PORT_DISCONT	0x05  /* port disconnect */
182*4882a593Smuzhiyun #define WHITEHEAT_TEST_UART_CLK_START	0x06  /* uart clock test start */
183*4882a593Smuzhiyun #define WHITEHEAT_TEST_UART_CLK_STOP	0x07  /* uart clock test stop */
184*4882a593Smuzhiyun #define WHITEHEAT_TEST_MODEM_FT		0x08  /* modem signals, requires a
185*4882a593Smuzhiyun 						loopback cable/connector */
186*4882a593Smuzhiyun #define WHITEHEAT_TEST_ERASE_EEPROM	0x09  /* erase eeprom */
187*4882a593Smuzhiyun #define WHITEHEAT_TEST_READ_EEPROM	0x0a  /* read eeprom */
188*4882a593Smuzhiyun #define WHITEHEAT_TEST_PROGRAM_EEPROM	0x0b  /* program eeprom */
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun struct whiteheat_test {
191*4882a593Smuzhiyun 	__u8	port;		/* port number (1 to n) */
192*4882a593Smuzhiyun 	__u8	test;		/* see WHITEHEAT_TEST_* above*/
193*4882a593Smuzhiyun 	__u8	info[32];	/* additional info */
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun /*
198*4882a593Smuzhiyun  * Replies from the firmware
199*4882a593Smuzhiyun  */
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun /*
203*4882a593Smuzhiyun  * WHITEHEAT_STATUS
204*4882a593Smuzhiyun  */
205*4882a593Smuzhiyun #define WHITEHEAT_EVENT_MODEM		0x01	/* modem field is valid */
206*4882a593Smuzhiyun #define WHITEHEAT_EVENT_ERROR		0x02	/* error field is valid */
207*4882a593Smuzhiyun #define WHITEHEAT_EVENT_FLOW		0x04	/* flow field is valid */
208*4882a593Smuzhiyun #define WHITEHEAT_EVENT_CONNECT		0x08	/* connect field is valid */
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun #define WHITEHEAT_FLOW_NONE		0x00	/* no flow control active */
211*4882a593Smuzhiyun #define WHITEHEAT_FLOW_HARD_OUT		0x01	/* TX is stopped by CTS
212*4882a593Smuzhiyun 						  (waiting for CTS to go on) */
213*4882a593Smuzhiyun #define WHITEHEAT_FLOW_HARD_IN		0x02	/* remote TX is stopped
214*4882a593Smuzhiyun 						  by RTS */
215*4882a593Smuzhiyun #define WHITEHEAT_FLOW_SOFT_OUT		0x04	/* TX is stopped by XOFF
216*4882a593Smuzhiyun 						  received (waiting for XON) */
217*4882a593Smuzhiyun #define WHITEHEAT_FLOW_SOFT_IN		0x08	/* remote TX is stopped by XOFF
218*4882a593Smuzhiyun 						  transmitted */
219*4882a593Smuzhiyun #define WHITEHEAT_FLOW_TX_DONE		0x80	/* TX has completed */
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun struct whiteheat_status_info {
222*4882a593Smuzhiyun 	__u8	port;		/* port number (1 to N) */
223*4882a593Smuzhiyun 	__u8	event;		/* indicates what the current event is,
224*4882a593Smuzhiyun 					see WHITEHEAT_EVENT_* above */
225*4882a593Smuzhiyun 	__u8	modem;		/* modem signal status (copy of uart's
226*4882a593Smuzhiyun 					MSR register) */
227*4882a593Smuzhiyun 	__u8	error;		/* line status (copy of uart's LSR register) */
228*4882a593Smuzhiyun 	__u8	flow;		/* flow control state, see WHITEHEAT_FLOW_*
229*4882a593Smuzhiyun 					above */
230*4882a593Smuzhiyun 	__u8	connect;	/* 0 means not connected, non-zero means
231*4882a593Smuzhiyun 					connected */
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun /*
236*4882a593Smuzhiyun  * WHITEHEAT_GET_DTR_RTS
237*4882a593Smuzhiyun  */
238*4882a593Smuzhiyun struct whiteheat_dr_info {
239*4882a593Smuzhiyun 	__u8	mcr;		/* copy of uart's MCR register */
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun /*
244*4882a593Smuzhiyun  * WHITEHEAT_GET_HW_INFO
245*4882a593Smuzhiyun  */
246*4882a593Smuzhiyun struct whiteheat_hw_info {
247*4882a593Smuzhiyun 	__u8	hw_id;		/* hardware id number, WhiteHEAT = 0 */
248*4882a593Smuzhiyun 	__u8	sw_major_rev;	/* major version number */
249*4882a593Smuzhiyun 	__u8	sw_minor_rev;	/* minor version number */
250*4882a593Smuzhiyun 	struct whiteheat_hw_eeprom_info {
251*4882a593Smuzhiyun 		__u8	b0;			/* B0 */
252*4882a593Smuzhiyun 		__u8	vendor_id_low;		/* vendor id (low byte) */
253*4882a593Smuzhiyun 		__u8	vendor_id_high;		/* vendor id (high byte) */
254*4882a593Smuzhiyun 		__u8	product_id_low;		/* product id (low byte) */
255*4882a593Smuzhiyun 		__u8	product_id_high;	/* product id (high byte) */
256*4882a593Smuzhiyun 		__u8	device_id_low;		/* device id (low byte) */
257*4882a593Smuzhiyun 		__u8	device_id_high;		/* device id (high byte) */
258*4882a593Smuzhiyun 		__u8	not_used_1;
259*4882a593Smuzhiyun 		__u8	serial_number_0;	/* serial number (low byte) */
260*4882a593Smuzhiyun 		__u8	serial_number_1;	/* serial number */
261*4882a593Smuzhiyun 		__u8	serial_number_2;	/* serial number */
262*4882a593Smuzhiyun 		__u8	serial_number_3;	/* serial number (high byte) */
263*4882a593Smuzhiyun 		__u8	not_used_2;
264*4882a593Smuzhiyun 		__u8	not_used_3;
265*4882a593Smuzhiyun 		__u8	checksum_low;		/* checksum (low byte) */
266*4882a593Smuzhiyun 		__u8	checksum_high;		/* checksum (high byte */
267*4882a593Smuzhiyun 	} hw_eeprom_info;	/* EEPROM contents */
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun /*
272*4882a593Smuzhiyun  * WHITEHEAT_EVENT
273*4882a593Smuzhiyun  */
274*4882a593Smuzhiyun struct whiteheat_event_info {
275*4882a593Smuzhiyun 	__u8	port;		/* port number (1 to N) */
276*4882a593Smuzhiyun 	__u8	event;		/* see whiteheat_status_info.event */
277*4882a593Smuzhiyun 	__u8	info;		/* see whiteheat_status_info.modem, .error,
278*4882a593Smuzhiyun 					.flow, .connect */
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun /*
283*4882a593Smuzhiyun  * WHITEHEAT_DO_TEST
284*4882a593Smuzhiyun  */
285*4882a593Smuzhiyun #define WHITEHEAT_TEST_FAIL	0x00  /* test failed */
286*4882a593Smuzhiyun #define WHITEHEAT_TEST_UNKNOWN	0x01  /* unknown test requested */
287*4882a593Smuzhiyun #define WHITEHEAT_TEST_PASS	0xff  /* test passed */
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun struct whiteheat_test_info {
290*4882a593Smuzhiyun 	__u8	port;		/* port number (1 to N) */
291*4882a593Smuzhiyun 	__u8	test;		/* indicates which test this is a response for,
292*4882a593Smuzhiyun 				   see WHITEHEAT_DO_TEST above */
293*4882a593Smuzhiyun 	__u8	status;		/* see WHITEHEAT_TEST_* above */
294*4882a593Smuzhiyun 	__u8	results[32];	/* test-dependent results */
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun #endif
299