xref: /OK3568_Linux_fs/kernel/drivers/usb/serial/io_ti.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*****************************************************************************
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *	Copyright (C) 1997-2002 Inside Out Networks, Inc.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  *	Feb-16-2001	DMI	Added I2C structure definitions
7*4882a593Smuzhiyun  *	May-29-2002	gkh	Ported to Linux
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  ******************************************************************************/
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #ifndef _IO_TI_H_
13*4882a593Smuzhiyun #define _IO_TI_H_
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /* Address Space */
16*4882a593Smuzhiyun #define DTK_ADDR_SPACE_XDATA		0x03	/* Addr is placed in XDATA space */
17*4882a593Smuzhiyun #define DTK_ADDR_SPACE_I2C_TYPE_II	0x82	/* Addr is placed in I2C area */
18*4882a593Smuzhiyun #define DTK_ADDR_SPACE_I2C_TYPE_III	0x83	/* Addr is placed in I2C area */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /* UART Defines */
21*4882a593Smuzhiyun #define UMPMEM_BASE_UART1		0xFFA0	/* UMP UART1 base address */
22*4882a593Smuzhiyun #define UMPMEM_BASE_UART2		0xFFB0	/* UMP UART2 base address */
23*4882a593Smuzhiyun #define UMPMEM_OFFS_UART_LSR		0x05	/* UMP UART LSR register offset */
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /* Bits per character */
26*4882a593Smuzhiyun #define UMP_UART_CHAR5BITS		0x00
27*4882a593Smuzhiyun #define UMP_UART_CHAR6BITS		0x01
28*4882a593Smuzhiyun #define UMP_UART_CHAR7BITS		0x02
29*4882a593Smuzhiyun #define UMP_UART_CHAR8BITS		0x03
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /* Parity */
32*4882a593Smuzhiyun #define UMP_UART_NOPARITY		0x00
33*4882a593Smuzhiyun #define UMP_UART_ODDPARITY		0x01
34*4882a593Smuzhiyun #define UMP_UART_EVENPARITY		0x02
35*4882a593Smuzhiyun #define UMP_UART_MARKPARITY		0x03
36*4882a593Smuzhiyun #define UMP_UART_SPACEPARITY		0x04
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Stop bits */
39*4882a593Smuzhiyun #define UMP_UART_STOPBIT1		0x00
40*4882a593Smuzhiyun #define UMP_UART_STOPBIT15		0x01
41*4882a593Smuzhiyun #define UMP_UART_STOPBIT2		0x02
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /* Line status register masks */
44*4882a593Smuzhiyun #define UMP_UART_LSR_OV_MASK		0x01
45*4882a593Smuzhiyun #define UMP_UART_LSR_PE_MASK		0x02
46*4882a593Smuzhiyun #define UMP_UART_LSR_FE_MASK		0x04
47*4882a593Smuzhiyun #define UMP_UART_LSR_BR_MASK		0x08
48*4882a593Smuzhiyun #define UMP_UART_LSR_ER_MASK		0x0F
49*4882a593Smuzhiyun #define UMP_UART_LSR_RX_MASK		0x10
50*4882a593Smuzhiyun #define UMP_UART_LSR_TX_MASK		0x20
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define UMP_UART_LSR_DATA_MASK		(LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK)
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* Port Settings Constants) */
55*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_RTS_FLOW		0x0001
56*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_RTS_DISABLE		0x0002
57*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_PARITY		0x0008
58*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW	0x0010
59*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW	0x0020
60*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_OUT_X		0x0040
61*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_OUT_XA		0x0080
62*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_IN_X		0x0100
63*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_DTR_FLOW		0x0800
64*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_DTR_DISABLE		0x1000
65*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_RECEIVE_MS_INT	0x2000
66*4882a593Smuzhiyun #define UMP_MASK_UART_FLAGS_AUTO_START_ON_ERR	0x4000
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define UMP_DMA_MODE_CONTINOUS			0x01
69*4882a593Smuzhiyun #define UMP_PIPE_TRANS_TIMEOUT_ENA		0x80
70*4882a593Smuzhiyun #define UMP_PIPE_TRANSFER_MODE_MASK		0x03
71*4882a593Smuzhiyun #define UMP_PIPE_TRANS_TIMEOUT_MASK		0x7C
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun /* Purge port Direction Mask Bits */
74*4882a593Smuzhiyun #define UMP_PORT_DIR_OUT			0x01
75*4882a593Smuzhiyun #define UMP_PORT_DIR_IN				0x02
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /* Address of Port 0 */
78*4882a593Smuzhiyun #define UMPM_UART1_PORT				0x03
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* Commands */
81*4882a593Smuzhiyun #define	UMPC_SET_CONFIG			0x05
82*4882a593Smuzhiyun #define	UMPC_OPEN_PORT			0x06
83*4882a593Smuzhiyun #define	UMPC_CLOSE_PORT			0x07
84*4882a593Smuzhiyun #define	UMPC_START_PORT			0x08
85*4882a593Smuzhiyun #define	UMPC_STOP_PORT			0x09
86*4882a593Smuzhiyun #define	UMPC_TEST_PORT			0x0A
87*4882a593Smuzhiyun #define	UMPC_PURGE_PORT			0x0B
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun /* Force the Firmware to complete the current Read */
90*4882a593Smuzhiyun #define	UMPC_COMPLETE_READ		0x80
91*4882a593Smuzhiyun /* Force UMP back into BOOT Mode */
92*4882a593Smuzhiyun #define	UMPC_HARDWARE_RESET		0x81
93*4882a593Smuzhiyun /*
94*4882a593Smuzhiyun  * Copy current download image to type 0xf2 record in 16k I2C
95*4882a593Smuzhiyun  * firmware will change 0xff record to type 2 record when complete
96*4882a593Smuzhiyun  */
97*4882a593Smuzhiyun #define	UMPC_COPY_DNLD_TO_I2C		0x82
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /*
100*4882a593Smuzhiyun  * Special function register commands
101*4882a593Smuzhiyun  * wIndex is register address
102*4882a593Smuzhiyun  * wValue is MSB/LSB mask/data
103*4882a593Smuzhiyun  */
104*4882a593Smuzhiyun #define	UMPC_WRITE_SFR			0x83	/* Write SFR Register */
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /* wIndex is register address */
107*4882a593Smuzhiyun #define	UMPC_READ_SFR			0x84	/* Read SRF Register */
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun /* Set or Clear DTR (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
110*4882a593Smuzhiyun #define	UMPC_SET_CLR_DTR		0x85
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /* Set or Clear RTS (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
113*4882a593Smuzhiyun #define	UMPC_SET_CLR_RTS		0x86
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
116*4882a593Smuzhiyun #define	UMPC_SET_CLR_LOOPBACK		0x87
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun /* Set or Clear BREAK (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
119*4882a593Smuzhiyun #define	UMPC_SET_CLR_BREAK		0x88
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /* Read MSR wIndex ModuleID (port) */
122*4882a593Smuzhiyun #define	UMPC_READ_MSR			0x89
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun /* Toolkit commands */
125*4882a593Smuzhiyun /* Read-write group */
126*4882a593Smuzhiyun #define	UMPC_MEMORY_READ		0x92
127*4882a593Smuzhiyun #define	UMPC_MEMORY_WRITE		0x93
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun  *	UMP DMA Definitions
131*4882a593Smuzhiyun  */
132*4882a593Smuzhiyun #define UMPD_OEDB1_ADDRESS		0xFF08
133*4882a593Smuzhiyun #define UMPD_OEDB2_ADDRESS		0xFF10
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun struct out_endpoint_desc_block {
136*4882a593Smuzhiyun 	__u8 Configuration;
137*4882a593Smuzhiyun 	__u8 XBufAddr;
138*4882a593Smuzhiyun 	__u8 XByteCount;
139*4882a593Smuzhiyun 	__u8 Unused1;
140*4882a593Smuzhiyun 	__u8 Unused2;
141*4882a593Smuzhiyun 	__u8 YBufAddr;
142*4882a593Smuzhiyun 	__u8 YByteCount;
143*4882a593Smuzhiyun 	__u8 BufferSize;
144*4882a593Smuzhiyun } __attribute__((packed));
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun  * TYPE DEFINITIONS
149*4882a593Smuzhiyun  * Structures for Firmware commands
150*4882a593Smuzhiyun  */
151*4882a593Smuzhiyun /* UART settings */
152*4882a593Smuzhiyun struct ump_uart_config {
153*4882a593Smuzhiyun 	__u16 wBaudRate;	/* Baud rate                        */
154*4882a593Smuzhiyun 	__u16 wFlags;		/* Bitmap mask of flags             */
155*4882a593Smuzhiyun 	__u8 bDataBits;		/* 5..8 - data bits per character   */
156*4882a593Smuzhiyun 	__u8 bParity;		/* Parity settings                  */
157*4882a593Smuzhiyun 	__u8 bStopBits;		/* Stop bits settings               */
158*4882a593Smuzhiyun 	char cXon;		/* XON character                    */
159*4882a593Smuzhiyun 	char cXoff;		/* XOFF character                   */
160*4882a593Smuzhiyun 	__u8 bUartMode;		/* Will be updated when a user      */
161*4882a593Smuzhiyun 				/* interface is defined             */
162*4882a593Smuzhiyun } __attribute__((packed));
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun  * TYPE DEFINITIONS
167*4882a593Smuzhiyun  * Structures for USB interrupts
168*4882a593Smuzhiyun  */
169*4882a593Smuzhiyun /* Interrupt packet structure */
170*4882a593Smuzhiyun struct ump_interrupt {
171*4882a593Smuzhiyun 	__u8 bICode;			/* Interrupt code (interrupt num)   */
172*4882a593Smuzhiyun 	__u8 bIInfo;			/* Interrupt information            */
173*4882a593Smuzhiyun }  __attribute__((packed));
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun #define TIUMP_GET_PORT_FROM_CODE(c)	(((c) >> 6) & 0x01)
177*4882a593Smuzhiyun #define TIUMP_GET_FUNC_FROM_CODE(c)	((c) & 0x0f)
178*4882a593Smuzhiyun #define TIUMP_INTERRUPT_CODE_LSR	0x03
179*4882a593Smuzhiyun #define TIUMP_INTERRUPT_CODE_MSR	0x04
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun #endif
182