1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /************************************************************************ 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * IONSP.H Definitions for I/O Networks Serial Protocol 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1997-1998 Inside Out Networks, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * These definitions are used by both kernel-mode driver and the 9*4882a593Smuzhiyun * peripheral firmware and MUST be kept in sync. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun ************************************************************************/ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /************************************************************************ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun The data to and from all ports on the peripheral is multiplexed 16*4882a593Smuzhiyun through a single endpoint pair (EP1 since it supports 64-byte 17*4882a593Smuzhiyun MaxPacketSize). Therefore, the data, commands, and status for 18*4882a593Smuzhiyun each port must be preceded by a short header identifying the 19*4882a593Smuzhiyun destination port. The header also identifies the bytes that follow 20*4882a593Smuzhiyun as data or as command/status info. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun Header format, first byte: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun CLLLLPPP 25*4882a593Smuzhiyun -------- 26*4882a593Smuzhiyun | | |------ Port Number: 0-7 27*4882a593Smuzhiyun | |--------- Length: MSB bits of length 28*4882a593Smuzhiyun |----------- Data/Command: 0 = Data header 29*4882a593Smuzhiyun 1 = Cmd / Status (Cmd if OUT, Status if IN) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun This gives 2 possible formats: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun Data header: 0LLLLPPP LLLLLLLL 35*4882a593Smuzhiyun ============ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun Where (LLLL,LLLLLLL) is 12-bit length of data that follows for 38*4882a593Smuzhiyun port number (PPP). The length is 0-based (0-FFF means 0-4095 39*4882a593Smuzhiyun bytes). The ~4K limit allows the host driver (which deals in 40*4882a593Smuzhiyun transfer requests instead of individual packets) to write a 41*4882a593Smuzhiyun large chunk of data in a single request. Note, however, that 42*4882a593Smuzhiyun the length must always be <= the current TxCredits for a given 43*4882a593Smuzhiyun port due to buffering limitations on the peripheral. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun Cmd/Status header: 1ccccPPP [ CCCCCCCC, Params ]... 47*4882a593Smuzhiyun ================== 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun Where (cccc) or (cccc,CCCCCCCC) is the cmd or status identifier. 50*4882a593Smuzhiyun Frequently-used values are encoded as (cccc), longer ones using 51*4882a593Smuzhiyun (cccc,CCCCCCCC). Subsequent bytes are optional parameters and are 52*4882a593Smuzhiyun specific to the cmd or status code. This may include a length 53*4882a593Smuzhiyun for command and status codes that need variable-length parameters. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun In addition, we use another interrupt pipe (endpoint) which the host polls 57*4882a593Smuzhiyun periodically for flow control information. The peripheral, when there has 58*4882a593Smuzhiyun been a change, sends the following 10-byte packet: 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun RRRRRRRRRRRRRRRR 61*4882a593Smuzhiyun T0T0T0T0T0T0T0T0 62*4882a593Smuzhiyun T1T1T1T1T1T1T1T1 63*4882a593Smuzhiyun T2T2T2T2T2T2T2T2 64*4882a593Smuzhiyun T3T3T3T3T3T3T3T3 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun The first field is the 16-bit RxBytesAvail field, which indicates the 67*4882a593Smuzhiyun number of bytes which may be read by the host from EP1. This is necessary: 68*4882a593Smuzhiyun (a) because OSR2.1 has a bug which causes data loss if the peripheral returns 69*4882a593Smuzhiyun fewer bytes than the host expects to read, and (b) because, on Microsoft 70*4882a593Smuzhiyun platforms at least, an outstanding read posted on EP1 consumes about 35% of 71*4882a593Smuzhiyun the CPU just polling the device for data. 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun The next 4 fields are the 16-bit TxCredits for each port, which indicate how 74*4882a593Smuzhiyun many bytes the host is allowed to send on EP1 for transmit to a given port. 75*4882a593Smuzhiyun After an OPEN_PORT command, the Edgeport sends the initial TxCredits for that 76*4882a593Smuzhiyun port. 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun All 16-bit fields are sent in little-endian (Intel) format. 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun ************************************************************************/ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun // 83*4882a593Smuzhiyun // Define format of InterruptStatus packet returned from the 84*4882a593Smuzhiyun // Interrupt pipe 85*4882a593Smuzhiyun // 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun struct int_status_pkt { 88*4882a593Smuzhiyun __u16 RxBytesAvail; // Additional bytes available to 89*4882a593Smuzhiyun // be read from Bulk IN pipe 90*4882a593Smuzhiyun __u16 TxCredits[MAX_RS232_PORTS]; // Additional space available in 91*4882a593Smuzhiyun // given port's TxBuffer 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define GET_INT_STATUS_SIZE(NumPorts) (sizeof(__u16) + (sizeof(__u16) * (NumPorts))) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun // 100*4882a593Smuzhiyun // Define cmd/status header values and macros to extract them. 101*4882a593Smuzhiyun // 102*4882a593Smuzhiyun // Data: 0LLLLPPP LLLLLLLL 103*4882a593Smuzhiyun // Cmd/Stat: 1ccccPPP CCCCCCCC 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define IOSP_DATA_HDR_SIZE 2 106*4882a593Smuzhiyun #define IOSP_CMD_HDR_SIZE 2 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define IOSP_MAX_DATA_LENGTH 0x0FFF // 12 bits -> 4K 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define IOSP_PORT_MASK 0x07 // Mask to isolate port number 111*4882a593Smuzhiyun #define IOSP_CMD_STAT_BIT 0x80 // If set, this is command/status header 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define IS_CMD_STAT_HDR(Byte1) ((Byte1) & IOSP_CMD_STAT_BIT) 114*4882a593Smuzhiyun #define IS_DATA_HDR(Byte1) (!IS_CMD_STAT_HDR(Byte1)) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define IOSP_GET_HDR_PORT(Byte1) ((__u8) ((Byte1) & IOSP_PORT_MASK)) 117*4882a593Smuzhiyun #define IOSP_GET_HDR_DATA_LEN(Byte1, Byte2) ((__u16) (((__u16)((Byte1) & 0x78)) << 5) | (Byte2)) 118*4882a593Smuzhiyun #define IOSP_GET_STATUS_CODE(Byte1) ((__u8) (((Byte1) & 0x78) >> 3)) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun // 122*4882a593Smuzhiyun // These macros build the 1st and 2nd bytes for a data header 123*4882a593Smuzhiyun // 124*4882a593Smuzhiyun #define IOSP_BUILD_DATA_HDR1(Port, Len) ((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78)))) 125*4882a593Smuzhiyun #define IOSP_BUILD_DATA_HDR2(Port, Len) ((__u8) (Len)) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun // 129*4882a593Smuzhiyun // These macros build the 1st and 2nd bytes for a command header 130*4882a593Smuzhiyun // 131*4882a593Smuzhiyun #define IOSP_BUILD_CMD_HDR1(Port, Cmd) ((__u8) (IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3)))) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun //-------------------------------------------------------------- 135*4882a593Smuzhiyun // 136*4882a593Smuzhiyun // Define values for commands and command parameters 137*4882a593Smuzhiyun // (sent from Host to Edgeport) 138*4882a593Smuzhiyun // 139*4882a593Smuzhiyun // 1ccccPPP P1P1P1P1 [ P2P2P2P2P2 ]... 140*4882a593Smuzhiyun // 141*4882a593Smuzhiyun // cccc: 00-07 2-byte commands. Write UART register 0-7 with 142*4882a593Smuzhiyun // value in P1. See 16650.H for definitions of 143*4882a593Smuzhiyun // UART register numbers and contents. 144*4882a593Smuzhiyun // 145*4882a593Smuzhiyun // 08-0B 3-byte commands: ==== P1 ==== ==== P2 ==== 146*4882a593Smuzhiyun // 08 available for expansion 147*4882a593Smuzhiyun // 09 1-param commands Command Code Param 148*4882a593Smuzhiyun // 0A available for expansion 149*4882a593Smuzhiyun // 0B available for expansion 150*4882a593Smuzhiyun // 151*4882a593Smuzhiyun // 0C-0D 4-byte commands. P1 = extended cmd and P2,P3 = params 152*4882a593Smuzhiyun // Currently unimplemented. 153*4882a593Smuzhiyun // 154*4882a593Smuzhiyun // 0E-0F N-byte commands: P1 = num bytes after P1 (ie, TotalLen - 2) 155*4882a593Smuzhiyun // P2 = extended cmd, P3..Pn = parameters. 156*4882a593Smuzhiyun // Currently unimplemented. 157*4882a593Smuzhiyun // 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define IOSP_WRITE_UART_REG(n) ((n) & 0x07) // UartReg[ n ] := P1 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun // Register numbers and contents 162*4882a593Smuzhiyun // defined in 16554.H. 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun // 0x08 // Available for expansion. 165*4882a593Smuzhiyun #define IOSP_EXT_CMD 0x09 // P1 = Command code (defined below) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun // P2 = Parameter 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun // 170*4882a593Smuzhiyun // Extended Command values, used with IOSP_EXT_CMD, may 171*4882a593Smuzhiyun // or may not use parameter P2. 172*4882a593Smuzhiyun // 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define IOSP_CMD_OPEN_PORT 0x00 // Enable ints, init UART. (NO PARAM) 175*4882a593Smuzhiyun #define IOSP_CMD_CLOSE_PORT 0x01 // Disable ints, flush buffers. (NO PARAM) 176*4882a593Smuzhiyun #define IOSP_CMD_CHASE_PORT 0x02 // Wait for Edgeport TX buffers to empty. (NO PARAM) 177*4882a593Smuzhiyun #define IOSP_CMD_SET_RX_FLOW 0x03 // Set Rx Flow Control in Edgeport 178*4882a593Smuzhiyun #define IOSP_CMD_SET_TX_FLOW 0x04 // Set Tx Flow Control in Edgeport 179*4882a593Smuzhiyun #define IOSP_CMD_SET_XON_CHAR 0x05 // Set XON Character in Edgeport 180*4882a593Smuzhiyun #define IOSP_CMD_SET_XOFF_CHAR 0x06 // Set XOFF Character in Edgeport 181*4882a593Smuzhiyun #define IOSP_CMD_RX_CHECK_REQ 0x07 // Request Edgeport to insert a Checkpoint into 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun // the receive data stream (Parameter = 1 byte sequence number) 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define IOSP_CMD_SET_BREAK 0x08 // Turn on the BREAK (LCR bit 6) 186*4882a593Smuzhiyun #define IOSP_CMD_CLEAR_BREAK 0x09 // Turn off the BREAK (LCR bit 6) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun // 190*4882a593Smuzhiyun // Define macros to simplify building of IOSP cmds 191*4882a593Smuzhiyun // 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val) \ 194*4882a593Smuzhiyun do { \ 195*4882a593Smuzhiyun (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), \ 196*4882a593Smuzhiyun IOSP_WRITE_UART_REG(Reg)); \ 197*4882a593Smuzhiyun (*(ppBuf))[1] = (Val); \ 198*4882a593Smuzhiyun \ 199*4882a593Smuzhiyun *ppBuf += 2; \ 200*4882a593Smuzhiyun *pLen += 2; \ 201*4882a593Smuzhiyun } while (0) 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param) \ 204*4882a593Smuzhiyun do { \ 205*4882a593Smuzhiyun (*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), IOSP_EXT_CMD); \ 206*4882a593Smuzhiyun (*(ppBuf))[1] = (ExtCmd); \ 207*4882a593Smuzhiyun (*(ppBuf))[2] = (Param); \ 208*4882a593Smuzhiyun \ 209*4882a593Smuzhiyun *ppBuf += 3; \ 210*4882a593Smuzhiyun *pLen += 3; \ 211*4882a593Smuzhiyun } while (0) 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun //-------------------------------------------------------------- 216*4882a593Smuzhiyun // 217*4882a593Smuzhiyun // Define format of flow control commands 218*4882a593Smuzhiyun // (sent from Host to Edgeport) 219*4882a593Smuzhiyun // 220*4882a593Smuzhiyun // 11001PPP FlowCmd FlowTypes 221*4882a593Smuzhiyun // 222*4882a593Smuzhiyun // Note that the 'FlowTypes' parameter is a bit mask; that is, 223*4882a593Smuzhiyun // more than one flow control type can be active at the same time. 224*4882a593Smuzhiyun // FlowTypes = 0 means 'no flow control'. 225*4882a593Smuzhiyun // 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun // 228*4882a593Smuzhiyun // IOSP_CMD_SET_RX_FLOW 229*4882a593Smuzhiyun // 230*4882a593Smuzhiyun // Tells Edgeport how it can stop incoming UART data 231*4882a593Smuzhiyun // 232*4882a593Smuzhiyun // Example for Port 0 233*4882a593Smuzhiyun // P0 = 11001000 234*4882a593Smuzhiyun // P1 = IOSP_CMD_SET_RX_FLOW 235*4882a593Smuzhiyun // P2 = Bit mask as follows: 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #define IOSP_RX_FLOW_RTS 0x01 // Edgeport drops RTS to stop incoming data 238*4882a593Smuzhiyun #define IOSP_RX_FLOW_DTR 0x02 // Edgeport drops DTR to stop incoming data 239*4882a593Smuzhiyun #define IOSP_RX_FLOW_DSR_SENSITIVITY 0x04 // Ignores Rx data unless DSR high 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun // Not currently implemented by firmware. 242*4882a593Smuzhiyun #define IOSP_RX_FLOW_XON_XOFF 0x08 // Edgeport sends XOFF char to stop incoming data. 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun // Host must have previously programmed the 245*4882a593Smuzhiyun // XON/XOFF values with SET_XON/SET_XOFF 246*4882a593Smuzhiyun // before enabling this bit. 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun // 249*4882a593Smuzhiyun // IOSP_CMD_SET_TX_FLOW 250*4882a593Smuzhiyun // 251*4882a593Smuzhiyun // Tells Edgeport what signal(s) will stop it from transmitting UART data 252*4882a593Smuzhiyun // 253*4882a593Smuzhiyun // Example for Port 0 254*4882a593Smuzhiyun // P0 = 11001000 255*4882a593Smuzhiyun // P1 = IOSP_CMD_SET_TX_FLOW 256*4882a593Smuzhiyun // P2 = Bit mask as follows: 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun #define IOSP_TX_FLOW_CTS 0x01 // Edgeport stops Tx if CTS low 259*4882a593Smuzhiyun #define IOSP_TX_FLOW_DSR 0x02 // Edgeport stops Tx if DSR low 260*4882a593Smuzhiyun #define IOSP_TX_FLOW_DCD 0x04 // Edgeport stops Tx if DCD low 261*4882a593Smuzhiyun #define IOSP_TX_FLOW_XON_XOFF 0x08 // Edgeport stops Tx upon receiving XOFF char. 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun // Host must have previously programmed the 264*4882a593Smuzhiyun // XON/XOFF values with SET_XON/SET_XOFF 265*4882a593Smuzhiyun // before enabling this bit. 266*4882a593Smuzhiyun #define IOSP_TX_FLOW_XOFF_CONTINUE 0x10 // If not set, Edgeport stops Tx when 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun // sending XOFF in order to fix broken 269*4882a593Smuzhiyun // systems that interpret the next 270*4882a593Smuzhiyun // received char as XON. 271*4882a593Smuzhiyun // If set, Edgeport continues Tx 272*4882a593Smuzhiyun // normally after transmitting XOFF. 273*4882a593Smuzhiyun // Not currently implemented by firmware. 274*4882a593Smuzhiyun #define IOSP_TX_TOGGLE_RTS 0x20 // Edgeport drives RTS as a true half-duplex 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun // Request-to-Send signal: it is raised before 277*4882a593Smuzhiyun // beginning transmission and lowered after 278*4882a593Smuzhiyun // the last Tx char leaves the UART. 279*4882a593Smuzhiyun // Not currently implemented by firmware. 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun // 282*4882a593Smuzhiyun // IOSP_CMD_SET_XON_CHAR 283*4882a593Smuzhiyun // 284*4882a593Smuzhiyun // Sets the character which Edgeport transmits/interprets as XON. 285*4882a593Smuzhiyun // Note: This command MUST be sent before sending a SET_RX_FLOW or 286*4882a593Smuzhiyun // SET_TX_FLOW with the XON_XOFF bit set. 287*4882a593Smuzhiyun // 288*4882a593Smuzhiyun // Example for Port 0 289*4882a593Smuzhiyun // P0 = 11001000 290*4882a593Smuzhiyun // P1 = IOSP_CMD_SET_XON_CHAR 291*4882a593Smuzhiyun // P2 = 0x11 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun // 295*4882a593Smuzhiyun // IOSP_CMD_SET_XOFF_CHAR 296*4882a593Smuzhiyun // 297*4882a593Smuzhiyun // Sets the character which Edgeport transmits/interprets as XOFF. 298*4882a593Smuzhiyun // Note: This command must be sent before sending a SET_RX_FLOW or 299*4882a593Smuzhiyun // SET_TX_FLOW with the XON_XOFF bit set. 300*4882a593Smuzhiyun // 301*4882a593Smuzhiyun // Example for Port 0 302*4882a593Smuzhiyun // P0 = 11001000 303*4882a593Smuzhiyun // P1 = IOSP_CMD_SET_XOFF_CHAR 304*4882a593Smuzhiyun // P2 = 0x13 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun // 308*4882a593Smuzhiyun // IOSP_CMD_RX_CHECK_REQ 309*4882a593Smuzhiyun // 310*4882a593Smuzhiyun // This command is used to assist in the implementation of the 311*4882a593Smuzhiyun // IOCTL_SERIAL_PURGE Windows IOCTL. 312*4882a593Smuzhiyun // This IOSP command tries to place a marker at the end of the RX 313*4882a593Smuzhiyun // queue in the Edgeport. If the Edgeport RX queue is full then 314*4882a593Smuzhiyun // the Check will be discarded. 315*4882a593Smuzhiyun // It is up to the device driver to timeout waiting for the 316*4882a593Smuzhiyun // RX_CHECK_RSP. If a RX_CHECK_RSP is received, the driver is 317*4882a593Smuzhiyun // sure that all data has been received from the edgeport and 318*4882a593Smuzhiyun // may now purge any internal RX buffers. 319*4882a593Smuzhiyun // Note tat the sequence numbers may be used to detect lost 320*4882a593Smuzhiyun // CHECK_REQs. 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun // Example for Port 0 323*4882a593Smuzhiyun // P0 = 11001000 324*4882a593Smuzhiyun // P1 = IOSP_CMD_RX_CHECK_REQ 325*4882a593Smuzhiyun // P2 = Sequence number 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun // Response will be: 329*4882a593Smuzhiyun // P1 = IOSP_EXT_RX_CHECK_RSP 330*4882a593Smuzhiyun // P2 = Request Sequence number 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun //-------------------------------------------------------------- 335*4882a593Smuzhiyun // 336*4882a593Smuzhiyun // Define values for status and status parameters 337*4882a593Smuzhiyun // (received by Host from Edgeport) 338*4882a593Smuzhiyun // 339*4882a593Smuzhiyun // 1ssssPPP P1P1P1P1 [ P2P2P2P2P2 ]... 340*4882a593Smuzhiyun // 341*4882a593Smuzhiyun // ssss: 00-07 2-byte status. ssss identifies which UART register 342*4882a593Smuzhiyun // has changed value, and the new value is in P1. 343*4882a593Smuzhiyun // Note that the ssss values do not correspond to the 344*4882a593Smuzhiyun // 16554 register numbers given in 16554.H. Instead, 345*4882a593Smuzhiyun // see below for definitions of the ssss numbers 346*4882a593Smuzhiyun // used in this status message. 347*4882a593Smuzhiyun // 348*4882a593Smuzhiyun // 08-0B 3-byte status: ==== P1 ==== ==== P2 ==== 349*4882a593Smuzhiyun // 08 LSR_DATA: New LSR Errored byte 350*4882a593Smuzhiyun // 09 1-param responses Response Code Param 351*4882a593Smuzhiyun // 0A OPEN_RSP: InitialMsr TxBufferSize 352*4882a593Smuzhiyun // 0B available for expansion 353*4882a593Smuzhiyun // 354*4882a593Smuzhiyun // 0C-0D 4-byte status. P1 = extended status code and P2,P3 = params 355*4882a593Smuzhiyun // Not currently implemented. 356*4882a593Smuzhiyun // 357*4882a593Smuzhiyun // 0E-0F N-byte status: P1 = num bytes after P1 (ie, TotalLen - 2) 358*4882a593Smuzhiyun // P2 = extended status, P3..Pn = parameters. 359*4882a593Smuzhiyun // Not currently implemented. 360*4882a593Smuzhiyun // 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun /**************************************************** 363*4882a593Smuzhiyun * SSSS values for 2-byte status messages (0-8) 364*4882a593Smuzhiyun ****************************************************/ 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun #define IOSP_STATUS_LSR 0x00 // P1 is new value of LSR register. 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun // Bits defined in 16554.H. Edgeport 369*4882a593Smuzhiyun // returns this in order to report 370*4882a593Smuzhiyun // line status errors (overrun, 371*4882a593Smuzhiyun // parity, framing, break). This form 372*4882a593Smuzhiyun // is used when a errored receive data 373*4882a593Smuzhiyun // character was NOT present in the 374*4882a593Smuzhiyun // UART when the LSR error occurred 375*4882a593Smuzhiyun // (ie, when LSR bit 0 = 0). 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun #define IOSP_STATUS_MSR 0x01 // P1 is new value of MSR register. 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun // Bits defined in 16554.H. Edgeport 380*4882a593Smuzhiyun // returns this in order to report 381*4882a593Smuzhiyun // changes in modem status lines 382*4882a593Smuzhiyun // (CTS, DSR, RI, CD) 383*4882a593Smuzhiyun // 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun // 0x02 // Available for future expansion 386*4882a593Smuzhiyun // 0x03 // 387*4882a593Smuzhiyun // 0x04 // 388*4882a593Smuzhiyun // 0x05 // 389*4882a593Smuzhiyun // 0x06 // 390*4882a593Smuzhiyun // 0x07 // 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun /**************************************************** 394*4882a593Smuzhiyun * SSSS values for 3-byte status messages (8-A) 395*4882a593Smuzhiyun ****************************************************/ 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun #define IOSP_STATUS_LSR_DATA 0x08 // P1 is new value of LSR register (same as STATUS_LSR) 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun // P2 is errored character read from 400*4882a593Smuzhiyun // RxFIFO after LSR reported an error. 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun #define IOSP_EXT_STATUS 0x09 // P1 is status/response code, param in P2. 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun // Response Codes (P1 values) for 3-byte status messages 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun #define IOSP_EXT_STATUS_CHASE_RSP 0 // Reply to CHASE_PORT cmd. P2 is outcome: 408*4882a593Smuzhiyun #define IOSP_EXT_STATUS_CHASE_PASS 0 // P2 = 0: All Tx data drained successfully 409*4882a593Smuzhiyun #define IOSP_EXT_STATUS_CHASE_FAIL 1 // P2 = 1: Timed out (stuck due to flow 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun // control from remote device). 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun #define IOSP_EXT_STATUS_RX_CHECK_RSP 1 // Reply to RX_CHECK cmd. P2 is sequence number 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun #define IOSP_STATUS_OPEN_RSP 0x0A // Reply to OPEN_PORT cmd. 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun // P1 is Initial MSR value 419*4882a593Smuzhiyun // P2 is encoded TxBuffer Size: 420*4882a593Smuzhiyun // TxBufferSize = (P2 + 1) * 64 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun // 0x0B // Available for future expansion 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun #define GET_TX_BUFFER_SIZE(P2) (((P2) + 1) * 64) 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun /**************************************************** 430*4882a593Smuzhiyun * SSSS values for 4-byte status messages 431*4882a593Smuzhiyun ****************************************************/ 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun #define IOSP_EXT4_STATUS 0x0C // Extended status code in P1, 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun // Params in P2, P3 436*4882a593Smuzhiyun // Currently unimplemented. 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun // 0x0D // Currently unused, available. 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun // 443*4882a593Smuzhiyun // Macros to parse status messages 444*4882a593Smuzhiyun // 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun #define IOSP_GET_STATUS_LEN(code) ((code) < 8 ? 2 : ((code) < 0x0A ? 3 : 4)) 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun #define IOSP_STATUS_IS_2BYTE(code) ((code) < 0x08) 449*4882a593Smuzhiyun #define IOSP_STATUS_IS_3BYTE(code) (((code) >= 0x08) && ((code) <= 0x0B)) 450*4882a593Smuzhiyun #define IOSP_STATUS_IS_4BYTE(code) (((code) >= 0x0C) && ((code) <= 0x0D)) 451*4882a593Smuzhiyun 452