1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Renesas USB driver RZ/A initialization and power control
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018 Chris Brandt
6*4882a593Smuzhiyun * Copyright (C) 2018-2019 Renesas Electronics Corporation
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/of_device.h>
12*4882a593Smuzhiyun #include "common.h"
13*4882a593Smuzhiyun #include "rza.h"
14*4882a593Smuzhiyun
usbhs_rza1_hardware_init(struct platform_device * pdev)15*4882a593Smuzhiyun static int usbhs_rza1_hardware_init(struct platform_device *pdev)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
18*4882a593Smuzhiyun struct device_node *usb_x1_clk, *extal_clk;
19*4882a593Smuzhiyun u32 freq_usb = 0, freq_extal = 0;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Input Clock Selection (NOTE: ch0 controls both ch0 and ch1) */
22*4882a593Smuzhiyun usb_x1_clk = of_find_node_by_name(NULL, "usb_x1");
23*4882a593Smuzhiyun extal_clk = of_find_node_by_name(NULL, "extal");
24*4882a593Smuzhiyun of_property_read_u32(usb_x1_clk, "clock-frequency", &freq_usb);
25*4882a593Smuzhiyun of_property_read_u32(extal_clk, "clock-frequency", &freq_extal);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun of_node_put(usb_x1_clk);
28*4882a593Smuzhiyun of_node_put(extal_clk);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun if (freq_usb == 0) {
31*4882a593Smuzhiyun if (freq_extal == 12000000) {
32*4882a593Smuzhiyun /* Select 12MHz XTAL */
33*4882a593Smuzhiyun usbhs_bset(priv, SYSCFG, UCKSEL, UCKSEL);
34*4882a593Smuzhiyun } else {
35*4882a593Smuzhiyun dev_err(usbhs_priv_to_dev(priv), "A 48MHz USB clock or 12MHz main clock is required.\n");
36*4882a593Smuzhiyun return -EIO;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Enable USB PLL (NOTE: ch0 controls both ch0 and ch1) */
41*4882a593Smuzhiyun usbhs_bset(priv, SYSCFG, UPLLE, UPLLE);
42*4882a593Smuzhiyun usleep_range(1000, 2000);
43*4882a593Smuzhiyun usbhs_bset(priv, SUSPMODE, SUSPM, SUSPM);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun const struct renesas_usbhs_platform_info usbhs_rza1_plat_info = {
49*4882a593Smuzhiyun .platform_callback = {
50*4882a593Smuzhiyun .hardware_init = usbhs_rza1_hardware_init,
51*4882a593Smuzhiyun .get_id = usbhs_get_id_as_gadget,
52*4882a593Smuzhiyun },
53*4882a593Smuzhiyun .driver_param = {
54*4882a593Smuzhiyun .has_new_pipe_configs = 1,
55*4882a593Smuzhiyun },
56*4882a593Smuzhiyun };
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