1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2011 Marvell International Ltd. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __MV_USB_OTG_CONTROLLER__ 7*4882a593Smuzhiyun #define __MV_USB_OTG_CONTROLLER__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Command Register Bit Masks */ 12*4882a593Smuzhiyun #define USBCMD_RUN_STOP (0x00000001) 13*4882a593Smuzhiyun #define USBCMD_CTRL_RESET (0x00000002) 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* otgsc Register Bit Masks */ 16*4882a593Smuzhiyun #define OTGSC_CTRL_VUSB_DISCHARGE 0x00000001 17*4882a593Smuzhiyun #define OTGSC_CTRL_VUSB_CHARGE 0x00000002 18*4882a593Smuzhiyun #define OTGSC_CTRL_OTG_TERM 0x00000008 19*4882a593Smuzhiyun #define OTGSC_CTRL_DATA_PULSING 0x00000010 20*4882a593Smuzhiyun #define OTGSC_STS_USB_ID 0x00000100 21*4882a593Smuzhiyun #define OTGSC_STS_A_VBUS_VALID 0x00000200 22*4882a593Smuzhiyun #define OTGSC_STS_A_SESSION_VALID 0x00000400 23*4882a593Smuzhiyun #define OTGSC_STS_B_SESSION_VALID 0x00000800 24*4882a593Smuzhiyun #define OTGSC_STS_B_SESSION_END 0x00001000 25*4882a593Smuzhiyun #define OTGSC_STS_1MS_TOGGLE 0x00002000 26*4882a593Smuzhiyun #define OTGSC_STS_DATA_PULSING 0x00004000 27*4882a593Smuzhiyun #define OTGSC_INTSTS_USB_ID 0x00010000 28*4882a593Smuzhiyun #define OTGSC_INTSTS_A_VBUS_VALID 0x00020000 29*4882a593Smuzhiyun #define OTGSC_INTSTS_A_SESSION_VALID 0x00040000 30*4882a593Smuzhiyun #define OTGSC_INTSTS_B_SESSION_VALID 0x00080000 31*4882a593Smuzhiyun #define OTGSC_INTSTS_B_SESSION_END 0x00100000 32*4882a593Smuzhiyun #define OTGSC_INTSTS_1MS 0x00200000 33*4882a593Smuzhiyun #define OTGSC_INTSTS_DATA_PULSING 0x00400000 34*4882a593Smuzhiyun #define OTGSC_INTR_USB_ID 0x01000000 35*4882a593Smuzhiyun #define OTGSC_INTR_A_VBUS_VALID 0x02000000 36*4882a593Smuzhiyun #define OTGSC_INTR_A_SESSION_VALID 0x04000000 37*4882a593Smuzhiyun #define OTGSC_INTR_B_SESSION_VALID 0x08000000 38*4882a593Smuzhiyun #define OTGSC_INTR_B_SESSION_END 0x10000000 39*4882a593Smuzhiyun #define OTGSC_INTR_1MS_TIMER 0x20000000 40*4882a593Smuzhiyun #define OTGSC_INTR_DATA_PULSING 0x40000000 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define CAPLENGTH_MASK (0xff) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Timer's interval, unit 10ms */ 45*4882a593Smuzhiyun #define T_A_WAIT_VRISE 100 46*4882a593Smuzhiyun #define T_A_WAIT_BCON 2000 47*4882a593Smuzhiyun #define T_A_AIDL_BDIS 100 48*4882a593Smuzhiyun #define T_A_BIDL_ADIS 20 49*4882a593Smuzhiyun #define T_B_ASE0_BRST 400 50*4882a593Smuzhiyun #define T_B_SE0_SRP 300 51*4882a593Smuzhiyun #define T_B_SRP_FAIL 2000 52*4882a593Smuzhiyun #define T_B_DATA_PLS 10 53*4882a593Smuzhiyun #define T_B_SRP_INIT 100 54*4882a593Smuzhiyun #define T_A_SRP_RSPNS 10 55*4882a593Smuzhiyun #define T_A_DRV_RSM 5 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun enum otg_function { 58*4882a593Smuzhiyun OTG_B_DEVICE = 0, 59*4882a593Smuzhiyun OTG_A_DEVICE 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun enum mv_otg_timer { 63*4882a593Smuzhiyun A_WAIT_BCON_TIMER = 0, 64*4882a593Smuzhiyun OTG_TIMER_NUM 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* PXA OTG state machine */ 68*4882a593Smuzhiyun struct mv_otg_ctrl { 69*4882a593Smuzhiyun /* internal variables */ 70*4882a593Smuzhiyun u8 a_set_b_hnp_en; /* A-Device set b_hnp_en */ 71*4882a593Smuzhiyun u8 b_srp_done; 72*4882a593Smuzhiyun u8 b_hnp_en; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* OTG inputs */ 75*4882a593Smuzhiyun u8 a_bus_drop; 76*4882a593Smuzhiyun u8 a_bus_req; 77*4882a593Smuzhiyun u8 a_clr_err; 78*4882a593Smuzhiyun u8 a_bus_resume; 79*4882a593Smuzhiyun u8 a_bus_suspend; 80*4882a593Smuzhiyun u8 a_conn; 81*4882a593Smuzhiyun u8 a_sess_vld; 82*4882a593Smuzhiyun u8 a_srp_det; 83*4882a593Smuzhiyun u8 a_vbus_vld; 84*4882a593Smuzhiyun u8 b_bus_req; /* B-Device Require Bus */ 85*4882a593Smuzhiyun u8 b_bus_resume; 86*4882a593Smuzhiyun u8 b_bus_suspend; 87*4882a593Smuzhiyun u8 b_conn; 88*4882a593Smuzhiyun u8 b_se0_srp; 89*4882a593Smuzhiyun u8 b_sess_end; 90*4882a593Smuzhiyun u8 b_sess_vld; 91*4882a593Smuzhiyun u8 id; 92*4882a593Smuzhiyun u8 a_suspend_req; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /*Timer event */ 95*4882a593Smuzhiyun u8 a_aidl_bdis_timeout; 96*4882a593Smuzhiyun u8 b_ase0_brst_timeout; 97*4882a593Smuzhiyun u8 a_bidl_adis_timeout; 98*4882a593Smuzhiyun u8 a_wait_bcon_timeout; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct timer_list timer[OTG_TIMER_NUM]; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define VUSBHS_MAX_PORTS 8 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun struct mv_otg_regs { 106*4882a593Smuzhiyun u32 usbcmd; /* Command register */ 107*4882a593Smuzhiyun u32 usbsts; /* Status register */ 108*4882a593Smuzhiyun u32 usbintr; /* Interrupt enable */ 109*4882a593Smuzhiyun u32 frindex; /* Frame index */ 110*4882a593Smuzhiyun u32 reserved1[1]; 111*4882a593Smuzhiyun u32 deviceaddr; /* Device Address */ 112*4882a593Smuzhiyun u32 eplistaddr; /* Endpoint List Address */ 113*4882a593Smuzhiyun u32 ttctrl; /* HOST TT status and control */ 114*4882a593Smuzhiyun u32 burstsize; /* Programmable Burst Size */ 115*4882a593Smuzhiyun u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */ 116*4882a593Smuzhiyun u32 reserved[4]; 117*4882a593Smuzhiyun u32 epnak; /* Endpoint NAK */ 118*4882a593Smuzhiyun u32 epnaken; /* Endpoint NAK Enable */ 119*4882a593Smuzhiyun u32 configflag; /* Configured Flag register */ 120*4882a593Smuzhiyun u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */ 121*4882a593Smuzhiyun u32 otgsc; 122*4882a593Smuzhiyun u32 usbmode; /* USB Host/Device mode */ 123*4882a593Smuzhiyun u32 epsetupstat; /* Endpoint Setup Status */ 124*4882a593Smuzhiyun u32 epprime; /* Endpoint Initialize */ 125*4882a593Smuzhiyun u32 epflush; /* Endpoint De-initialize */ 126*4882a593Smuzhiyun u32 epstatus; /* Endpoint Status */ 127*4882a593Smuzhiyun u32 epcomplete; /* Endpoint Interrupt On Complete */ 128*4882a593Smuzhiyun u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */ 129*4882a593Smuzhiyun u32 mcr; /* Mux Control */ 130*4882a593Smuzhiyun u32 isr; /* Interrupt Status */ 131*4882a593Smuzhiyun u32 ier; /* Interrupt Enable */ 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun struct mv_otg { 135*4882a593Smuzhiyun struct usb_phy phy; 136*4882a593Smuzhiyun struct mv_otg_ctrl otg_ctrl; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* base address */ 139*4882a593Smuzhiyun void __iomem *phy_regs; 140*4882a593Smuzhiyun void __iomem *cap_regs; 141*4882a593Smuzhiyun struct mv_otg_regs __iomem *op_regs; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun struct platform_device *pdev; 144*4882a593Smuzhiyun int irq; 145*4882a593Smuzhiyun u32 irq_status; 146*4882a593Smuzhiyun u32 irq_en; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun struct delayed_work work; 149*4882a593Smuzhiyun struct workqueue_struct *qwork; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun spinlock_t wq_lock; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun struct mv_usb_platform_data *pdata; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun unsigned int active; 156*4882a593Smuzhiyun unsigned int clock_gating; 157*4882a593Smuzhiyun struct clk *clk; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #endif 161