1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
4*4882a593Smuzhiyun * Author: Chao Xie <chao.xie@marvell.com>
5*4882a593Smuzhiyun * Neil Zhang <zhangwm@marvell.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/iopoll.h>
12*4882a593Smuzhiyun #include <linux/uaccess.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/proc_fs.h>
15*4882a593Smuzhiyun #include <linux/clk.h>
16*4882a593Smuzhiyun #include <linux/workqueue.h>
17*4882a593Smuzhiyun #include <linux/platform_device.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/usb.h>
20*4882a593Smuzhiyun #include <linux/usb/ch9.h>
21*4882a593Smuzhiyun #include <linux/usb/otg.h>
22*4882a593Smuzhiyun #include <linux/usb/gadget.h>
23*4882a593Smuzhiyun #include <linux/usb/hcd.h>
24*4882a593Smuzhiyun #include <linux/platform_data/mv_usb.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "phy-mv-usb.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define DRIVER_DESC "Marvell USB OTG transceiver driver"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun MODULE_DESCRIPTION(DRIVER_DESC);
31*4882a593Smuzhiyun MODULE_LICENSE("GPL");
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun static const char driver_name[] = "mv-otg";
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static char *state_string[] = {
36*4882a593Smuzhiyun "undefined",
37*4882a593Smuzhiyun "b_idle",
38*4882a593Smuzhiyun "b_srp_init",
39*4882a593Smuzhiyun "b_peripheral",
40*4882a593Smuzhiyun "b_wait_acon",
41*4882a593Smuzhiyun "b_host",
42*4882a593Smuzhiyun "a_idle",
43*4882a593Smuzhiyun "a_wait_vrise",
44*4882a593Smuzhiyun "a_wait_bcon",
45*4882a593Smuzhiyun "a_host",
46*4882a593Smuzhiyun "a_suspend",
47*4882a593Smuzhiyun "a_peripheral",
48*4882a593Smuzhiyun "a_wait_vfall",
49*4882a593Smuzhiyun "a_vbus_err"
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
mv_otg_set_vbus(struct usb_otg * otg,bool on)52*4882a593Smuzhiyun static int mv_otg_set_vbus(struct usb_otg *otg, bool on)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun struct mv_otg *mvotg = container_of(otg->usb_phy, struct mv_otg, phy);
55*4882a593Smuzhiyun if (mvotg->pdata->set_vbus == NULL)
56*4882a593Smuzhiyun return -ENODEV;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return mvotg->pdata->set_vbus(on);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
mv_otg_set_host(struct usb_otg * otg,struct usb_bus * host)61*4882a593Smuzhiyun static int mv_otg_set_host(struct usb_otg *otg,
62*4882a593Smuzhiyun struct usb_bus *host)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun otg->host = host;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
mv_otg_set_peripheral(struct usb_otg * otg,struct usb_gadget * gadget)69*4882a593Smuzhiyun static int mv_otg_set_peripheral(struct usb_otg *otg,
70*4882a593Smuzhiyun struct usb_gadget *gadget)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun otg->gadget = gadget;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
mv_otg_run_state_machine(struct mv_otg * mvotg,unsigned long delay)77*4882a593Smuzhiyun static void mv_otg_run_state_machine(struct mv_otg *mvotg,
78*4882a593Smuzhiyun unsigned long delay)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev, "transceiver is updated\n");
81*4882a593Smuzhiyun if (!mvotg->qwork)
82*4882a593Smuzhiyun return;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun queue_delayed_work(mvotg->qwork, &mvotg->work, delay);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
mv_otg_timer_await_bcon(struct timer_list * t)87*4882a593Smuzhiyun static void mv_otg_timer_await_bcon(struct timer_list *t)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct mv_otg *mvotg = from_timer(mvotg, t,
90*4882a593Smuzhiyun otg_ctrl.timer[A_WAIT_BCON_TIMER]);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun mvotg->otg_ctrl.a_wait_bcon_timeout = 1;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun dev_info(&mvotg->pdev->dev, "B Device No Response!\n");
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun if (spin_trylock(&mvotg->wq_lock)) {
97*4882a593Smuzhiyun mv_otg_run_state_machine(mvotg, 0);
98*4882a593Smuzhiyun spin_unlock(&mvotg->wq_lock);
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
mv_otg_cancel_timer(struct mv_otg * mvotg,unsigned int id)102*4882a593Smuzhiyun static int mv_otg_cancel_timer(struct mv_otg *mvotg, unsigned int id)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct timer_list *timer;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (id >= OTG_TIMER_NUM)
107*4882a593Smuzhiyun return -EINVAL;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun timer = &mvotg->otg_ctrl.timer[id];
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun if (timer_pending(timer))
112*4882a593Smuzhiyun del_timer(timer);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
mv_otg_set_timer(struct mv_otg * mvotg,unsigned int id,unsigned long interval)117*4882a593Smuzhiyun static int mv_otg_set_timer(struct mv_otg *mvotg, unsigned int id,
118*4882a593Smuzhiyun unsigned long interval)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun struct timer_list *timer;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun if (id >= OTG_TIMER_NUM)
123*4882a593Smuzhiyun return -EINVAL;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun timer = &mvotg->otg_ctrl.timer[id];
126*4882a593Smuzhiyun if (timer_pending(timer)) {
127*4882a593Smuzhiyun dev_err(&mvotg->pdev->dev, "Timer%d is already running\n", id);
128*4882a593Smuzhiyun return -EBUSY;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun timer->expires = jiffies + interval;
132*4882a593Smuzhiyun add_timer(timer);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun return 0;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
mv_otg_reset(struct mv_otg * mvotg)137*4882a593Smuzhiyun static int mv_otg_reset(struct mv_otg *mvotg)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun u32 tmp;
140*4882a593Smuzhiyun int ret;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* Stop the controller */
143*4882a593Smuzhiyun tmp = readl(&mvotg->op_regs->usbcmd);
144*4882a593Smuzhiyun tmp &= ~USBCMD_RUN_STOP;
145*4882a593Smuzhiyun writel(tmp, &mvotg->op_regs->usbcmd);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* Reset the controller to get default values */
148*4882a593Smuzhiyun writel(USBCMD_CTRL_RESET, &mvotg->op_regs->usbcmd);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun ret = readl_poll_timeout_atomic(&mvotg->op_regs->usbcmd, tmp,
151*4882a593Smuzhiyun (tmp & USBCMD_CTRL_RESET), 10, 10000);
152*4882a593Smuzhiyun if (ret < 0) {
153*4882a593Smuzhiyun dev_err(&mvotg->pdev->dev,
154*4882a593Smuzhiyun "Wait for RESET completed TIMEOUT\n");
155*4882a593Smuzhiyun return ret;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun writel(0x0, &mvotg->op_regs->usbintr);
159*4882a593Smuzhiyun tmp = readl(&mvotg->op_regs->usbsts);
160*4882a593Smuzhiyun writel(tmp, &mvotg->op_regs->usbsts);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return 0;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
mv_otg_init_irq(struct mv_otg * mvotg)165*4882a593Smuzhiyun static void mv_otg_init_irq(struct mv_otg *mvotg)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun u32 otgsc;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun mvotg->irq_en = OTGSC_INTR_A_SESSION_VALID
170*4882a593Smuzhiyun | OTGSC_INTR_A_VBUS_VALID;
171*4882a593Smuzhiyun mvotg->irq_status = OTGSC_INTSTS_A_SESSION_VALID
172*4882a593Smuzhiyun | OTGSC_INTSTS_A_VBUS_VALID;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun if (mvotg->pdata->vbus == NULL) {
175*4882a593Smuzhiyun mvotg->irq_en |= OTGSC_INTR_B_SESSION_VALID
176*4882a593Smuzhiyun | OTGSC_INTR_B_SESSION_END;
177*4882a593Smuzhiyun mvotg->irq_status |= OTGSC_INTSTS_B_SESSION_VALID
178*4882a593Smuzhiyun | OTGSC_INTSTS_B_SESSION_END;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun if (mvotg->pdata->id == NULL) {
182*4882a593Smuzhiyun mvotg->irq_en |= OTGSC_INTR_USB_ID;
183*4882a593Smuzhiyun mvotg->irq_status |= OTGSC_INTSTS_USB_ID;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun otgsc = readl(&mvotg->op_regs->otgsc);
187*4882a593Smuzhiyun otgsc |= mvotg->irq_en;
188*4882a593Smuzhiyun writel(otgsc, &mvotg->op_regs->otgsc);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
mv_otg_start_host(struct mv_otg * mvotg,int on)191*4882a593Smuzhiyun static void mv_otg_start_host(struct mv_otg *mvotg, int on)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun #ifdef CONFIG_USB
194*4882a593Smuzhiyun struct usb_otg *otg = mvotg->phy.otg;
195*4882a593Smuzhiyun struct usb_hcd *hcd;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun if (!otg->host)
198*4882a593Smuzhiyun return;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun dev_info(&mvotg->pdev->dev, "%s host\n", on ? "start" : "stop");
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun hcd = bus_to_hcd(otg->host);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun if (on) {
205*4882a593Smuzhiyun usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
206*4882a593Smuzhiyun device_wakeup_enable(hcd->self.controller);
207*4882a593Smuzhiyun } else {
208*4882a593Smuzhiyun usb_remove_hcd(hcd);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun #endif /* CONFIG_USB */
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
mv_otg_start_periphrals(struct mv_otg * mvotg,int on)213*4882a593Smuzhiyun static void mv_otg_start_periphrals(struct mv_otg *mvotg, int on)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun struct usb_otg *otg = mvotg->phy.otg;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun if (!otg->gadget)
218*4882a593Smuzhiyun return;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun dev_info(mvotg->phy.dev, "gadget %s\n", on ? "on" : "off");
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (on)
223*4882a593Smuzhiyun usb_gadget_vbus_connect(otg->gadget);
224*4882a593Smuzhiyun else
225*4882a593Smuzhiyun usb_gadget_vbus_disconnect(otg->gadget);
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
otg_clock_enable(struct mv_otg * mvotg)228*4882a593Smuzhiyun static void otg_clock_enable(struct mv_otg *mvotg)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun clk_prepare_enable(mvotg->clk);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
otg_clock_disable(struct mv_otg * mvotg)233*4882a593Smuzhiyun static void otg_clock_disable(struct mv_otg *mvotg)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun clk_disable_unprepare(mvotg->clk);
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
mv_otg_enable_internal(struct mv_otg * mvotg)238*4882a593Smuzhiyun static int mv_otg_enable_internal(struct mv_otg *mvotg)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun int retval = 0;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun if (mvotg->active)
243*4882a593Smuzhiyun return 0;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun otg_clock_enable(mvotg);
248*4882a593Smuzhiyun if (mvotg->pdata->phy_init) {
249*4882a593Smuzhiyun retval = mvotg->pdata->phy_init(mvotg->phy_regs);
250*4882a593Smuzhiyun if (retval) {
251*4882a593Smuzhiyun dev_err(&mvotg->pdev->dev,
252*4882a593Smuzhiyun "init phy error %d\n", retval);
253*4882a593Smuzhiyun otg_clock_disable(mvotg);
254*4882a593Smuzhiyun return retval;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun mvotg->active = 1;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun return 0;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
mv_otg_enable(struct mv_otg * mvotg)263*4882a593Smuzhiyun static int mv_otg_enable(struct mv_otg *mvotg)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun if (mvotg->clock_gating)
266*4882a593Smuzhiyun return mv_otg_enable_internal(mvotg);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun return 0;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
mv_otg_disable_internal(struct mv_otg * mvotg)271*4882a593Smuzhiyun static void mv_otg_disable_internal(struct mv_otg *mvotg)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun if (mvotg->active) {
274*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev, "otg disabled\n");
275*4882a593Smuzhiyun if (mvotg->pdata->phy_deinit)
276*4882a593Smuzhiyun mvotg->pdata->phy_deinit(mvotg->phy_regs);
277*4882a593Smuzhiyun otg_clock_disable(mvotg);
278*4882a593Smuzhiyun mvotg->active = 0;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
mv_otg_disable(struct mv_otg * mvotg)282*4882a593Smuzhiyun static void mv_otg_disable(struct mv_otg *mvotg)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun if (mvotg->clock_gating)
285*4882a593Smuzhiyun mv_otg_disable_internal(mvotg);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
mv_otg_update_inputs(struct mv_otg * mvotg)288*4882a593Smuzhiyun static void mv_otg_update_inputs(struct mv_otg *mvotg)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
291*4882a593Smuzhiyun u32 otgsc;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun otgsc = readl(&mvotg->op_regs->otgsc);
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun if (mvotg->pdata->vbus) {
296*4882a593Smuzhiyun if (mvotg->pdata->vbus->poll() == VBUS_HIGH) {
297*4882a593Smuzhiyun otg_ctrl->b_sess_vld = 1;
298*4882a593Smuzhiyun otg_ctrl->b_sess_end = 0;
299*4882a593Smuzhiyun } else {
300*4882a593Smuzhiyun otg_ctrl->b_sess_vld = 0;
301*4882a593Smuzhiyun otg_ctrl->b_sess_end = 1;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun } else {
304*4882a593Smuzhiyun otg_ctrl->b_sess_vld = !!(otgsc & OTGSC_STS_B_SESSION_VALID);
305*4882a593Smuzhiyun otg_ctrl->b_sess_end = !!(otgsc & OTGSC_STS_B_SESSION_END);
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun if (mvotg->pdata->id)
309*4882a593Smuzhiyun otg_ctrl->id = !!mvotg->pdata->id->poll();
310*4882a593Smuzhiyun else
311*4882a593Smuzhiyun otg_ctrl->id = !!(otgsc & OTGSC_STS_USB_ID);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun if (mvotg->pdata->otg_force_a_bus_req && !otg_ctrl->id)
314*4882a593Smuzhiyun otg_ctrl->a_bus_req = 1;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun otg_ctrl->a_sess_vld = !!(otgsc & OTGSC_STS_A_SESSION_VALID);
317*4882a593Smuzhiyun otg_ctrl->a_vbus_vld = !!(otgsc & OTGSC_STS_A_VBUS_VALID);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev, "%s: ", __func__);
320*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev, "id %d\n", otg_ctrl->id);
321*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev, "b_sess_vld %d\n", otg_ctrl->b_sess_vld);
322*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev, "b_sess_end %d\n", otg_ctrl->b_sess_end);
323*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev, "a_vbus_vld %d\n", otg_ctrl->a_vbus_vld);
324*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev, "a_sess_vld %d\n", otg_ctrl->a_sess_vld);
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
mv_otg_update_state(struct mv_otg * mvotg)327*4882a593Smuzhiyun static void mv_otg_update_state(struct mv_otg *mvotg)
328*4882a593Smuzhiyun {
329*4882a593Smuzhiyun struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
330*4882a593Smuzhiyun int old_state = mvotg->phy.otg->state;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun switch (old_state) {
333*4882a593Smuzhiyun case OTG_STATE_UNDEFINED:
334*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_B_IDLE;
335*4882a593Smuzhiyun fallthrough;
336*4882a593Smuzhiyun case OTG_STATE_B_IDLE:
337*4882a593Smuzhiyun if (otg_ctrl->id == 0)
338*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_IDLE;
339*4882a593Smuzhiyun else if (otg_ctrl->b_sess_vld)
340*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_B_PERIPHERAL;
341*4882a593Smuzhiyun break;
342*4882a593Smuzhiyun case OTG_STATE_B_PERIPHERAL:
343*4882a593Smuzhiyun if (!otg_ctrl->b_sess_vld || otg_ctrl->id == 0)
344*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_B_IDLE;
345*4882a593Smuzhiyun break;
346*4882a593Smuzhiyun case OTG_STATE_A_IDLE:
347*4882a593Smuzhiyun if (otg_ctrl->id)
348*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_B_IDLE;
349*4882a593Smuzhiyun else if (!(otg_ctrl->a_bus_drop) &&
350*4882a593Smuzhiyun (otg_ctrl->a_bus_req || otg_ctrl->a_srp_det))
351*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_WAIT_VRISE;
352*4882a593Smuzhiyun break;
353*4882a593Smuzhiyun case OTG_STATE_A_WAIT_VRISE:
354*4882a593Smuzhiyun if (otg_ctrl->a_vbus_vld)
355*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_WAIT_BCON;
356*4882a593Smuzhiyun break;
357*4882a593Smuzhiyun case OTG_STATE_A_WAIT_BCON:
358*4882a593Smuzhiyun if (otg_ctrl->id || otg_ctrl->a_bus_drop
359*4882a593Smuzhiyun || otg_ctrl->a_wait_bcon_timeout) {
360*4882a593Smuzhiyun mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
361*4882a593Smuzhiyun mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
362*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
363*4882a593Smuzhiyun otg_ctrl->a_bus_req = 0;
364*4882a593Smuzhiyun } else if (!otg_ctrl->a_vbus_vld) {
365*4882a593Smuzhiyun mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
366*4882a593Smuzhiyun mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
367*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_VBUS_ERR;
368*4882a593Smuzhiyun } else if (otg_ctrl->b_conn) {
369*4882a593Smuzhiyun mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
370*4882a593Smuzhiyun mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
371*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_HOST;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun break;
374*4882a593Smuzhiyun case OTG_STATE_A_HOST:
375*4882a593Smuzhiyun if (otg_ctrl->id || !otg_ctrl->b_conn
376*4882a593Smuzhiyun || otg_ctrl->a_bus_drop)
377*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_WAIT_BCON;
378*4882a593Smuzhiyun else if (!otg_ctrl->a_vbus_vld)
379*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_VBUS_ERR;
380*4882a593Smuzhiyun break;
381*4882a593Smuzhiyun case OTG_STATE_A_WAIT_VFALL:
382*4882a593Smuzhiyun if (otg_ctrl->id
383*4882a593Smuzhiyun || (!otg_ctrl->b_conn && otg_ctrl->a_sess_vld)
384*4882a593Smuzhiyun || otg_ctrl->a_bus_req)
385*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_IDLE;
386*4882a593Smuzhiyun break;
387*4882a593Smuzhiyun case OTG_STATE_A_VBUS_ERR:
388*4882a593Smuzhiyun if (otg_ctrl->id || otg_ctrl->a_clr_err
389*4882a593Smuzhiyun || otg_ctrl->a_bus_drop) {
390*4882a593Smuzhiyun otg_ctrl->a_clr_err = 0;
391*4882a593Smuzhiyun mvotg->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun break;
394*4882a593Smuzhiyun default:
395*4882a593Smuzhiyun break;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
mv_otg_work(struct work_struct * work)399*4882a593Smuzhiyun static void mv_otg_work(struct work_struct *work)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun struct mv_otg *mvotg;
402*4882a593Smuzhiyun struct usb_otg *otg;
403*4882a593Smuzhiyun int old_state;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun mvotg = container_of(to_delayed_work(work), struct mv_otg, work);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun run:
408*4882a593Smuzhiyun /* work queue is single thread, or we need spin_lock to protect */
409*4882a593Smuzhiyun otg = mvotg->phy.otg;
410*4882a593Smuzhiyun old_state = otg->state;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun if (!mvotg->active)
413*4882a593Smuzhiyun return;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun mv_otg_update_inputs(mvotg);
416*4882a593Smuzhiyun mv_otg_update_state(mvotg);
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (old_state != mvotg->phy.otg->state) {
419*4882a593Smuzhiyun dev_info(&mvotg->pdev->dev, "change from state %s to %s\n",
420*4882a593Smuzhiyun state_string[old_state],
421*4882a593Smuzhiyun state_string[mvotg->phy.otg->state]);
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun switch (mvotg->phy.otg->state) {
424*4882a593Smuzhiyun case OTG_STATE_B_IDLE:
425*4882a593Smuzhiyun otg->default_a = 0;
426*4882a593Smuzhiyun if (old_state == OTG_STATE_B_PERIPHERAL)
427*4882a593Smuzhiyun mv_otg_start_periphrals(mvotg, 0);
428*4882a593Smuzhiyun mv_otg_reset(mvotg);
429*4882a593Smuzhiyun mv_otg_disable(mvotg);
430*4882a593Smuzhiyun usb_phy_set_event(&mvotg->phy, USB_EVENT_NONE);
431*4882a593Smuzhiyun break;
432*4882a593Smuzhiyun case OTG_STATE_B_PERIPHERAL:
433*4882a593Smuzhiyun mv_otg_enable(mvotg);
434*4882a593Smuzhiyun mv_otg_start_periphrals(mvotg, 1);
435*4882a593Smuzhiyun usb_phy_set_event(&mvotg->phy, USB_EVENT_ENUMERATED);
436*4882a593Smuzhiyun break;
437*4882a593Smuzhiyun case OTG_STATE_A_IDLE:
438*4882a593Smuzhiyun otg->default_a = 1;
439*4882a593Smuzhiyun mv_otg_enable(mvotg);
440*4882a593Smuzhiyun if (old_state == OTG_STATE_A_WAIT_VFALL)
441*4882a593Smuzhiyun mv_otg_start_host(mvotg, 0);
442*4882a593Smuzhiyun mv_otg_reset(mvotg);
443*4882a593Smuzhiyun break;
444*4882a593Smuzhiyun case OTG_STATE_A_WAIT_VRISE:
445*4882a593Smuzhiyun mv_otg_set_vbus(otg, 1);
446*4882a593Smuzhiyun break;
447*4882a593Smuzhiyun case OTG_STATE_A_WAIT_BCON:
448*4882a593Smuzhiyun if (old_state != OTG_STATE_A_HOST)
449*4882a593Smuzhiyun mv_otg_start_host(mvotg, 1);
450*4882a593Smuzhiyun mv_otg_set_timer(mvotg, A_WAIT_BCON_TIMER,
451*4882a593Smuzhiyun T_A_WAIT_BCON);
452*4882a593Smuzhiyun /*
453*4882a593Smuzhiyun * Now, we directly enter A_HOST. So set b_conn = 1
454*4882a593Smuzhiyun * here. In fact, it need host driver to notify us.
455*4882a593Smuzhiyun */
456*4882a593Smuzhiyun mvotg->otg_ctrl.b_conn = 1;
457*4882a593Smuzhiyun break;
458*4882a593Smuzhiyun case OTG_STATE_A_HOST:
459*4882a593Smuzhiyun break;
460*4882a593Smuzhiyun case OTG_STATE_A_WAIT_VFALL:
461*4882a593Smuzhiyun /*
462*4882a593Smuzhiyun * Now, we has exited A_HOST. So set b_conn = 0
463*4882a593Smuzhiyun * here. In fact, it need host driver to notify us.
464*4882a593Smuzhiyun */
465*4882a593Smuzhiyun mvotg->otg_ctrl.b_conn = 0;
466*4882a593Smuzhiyun mv_otg_set_vbus(otg, 0);
467*4882a593Smuzhiyun break;
468*4882a593Smuzhiyun case OTG_STATE_A_VBUS_ERR:
469*4882a593Smuzhiyun break;
470*4882a593Smuzhiyun default:
471*4882a593Smuzhiyun break;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun goto run;
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun
mv_otg_irq(int irq,void * dev)477*4882a593Smuzhiyun static irqreturn_t mv_otg_irq(int irq, void *dev)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun struct mv_otg *mvotg = dev;
480*4882a593Smuzhiyun u32 otgsc;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun otgsc = readl(&mvotg->op_regs->otgsc);
483*4882a593Smuzhiyun writel(otgsc, &mvotg->op_regs->otgsc);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun /*
486*4882a593Smuzhiyun * if we have vbus, then the vbus detection for B-device
487*4882a593Smuzhiyun * will be done by mv_otg_inputs_irq().
488*4882a593Smuzhiyun */
489*4882a593Smuzhiyun if (mvotg->pdata->vbus)
490*4882a593Smuzhiyun if ((otgsc & OTGSC_STS_USB_ID) &&
491*4882a593Smuzhiyun !(otgsc & OTGSC_INTSTS_USB_ID))
492*4882a593Smuzhiyun return IRQ_NONE;
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun if ((otgsc & mvotg->irq_status) == 0)
495*4882a593Smuzhiyun return IRQ_NONE;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun mv_otg_run_state_machine(mvotg, 0);
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun return IRQ_HANDLED;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
mv_otg_inputs_irq(int irq,void * dev)502*4882a593Smuzhiyun static irqreturn_t mv_otg_inputs_irq(int irq, void *dev)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun struct mv_otg *mvotg = dev;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun /* The clock may disabled at this time */
507*4882a593Smuzhiyun if (!mvotg->active) {
508*4882a593Smuzhiyun mv_otg_enable(mvotg);
509*4882a593Smuzhiyun mv_otg_init_irq(mvotg);
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun mv_otg_run_state_machine(mvotg, 0);
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun return IRQ_HANDLED;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun static ssize_t
a_bus_req_show(struct device * dev,struct device_attribute * attr,char * buf)518*4882a593Smuzhiyun a_bus_req_show(struct device *dev, struct device_attribute *attr, char *buf)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun struct mv_otg *mvotg = dev_get_drvdata(dev);
521*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%d\n",
522*4882a593Smuzhiyun mvotg->otg_ctrl.a_bus_req);
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun static ssize_t
a_bus_req_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)526*4882a593Smuzhiyun a_bus_req_store(struct device *dev, struct device_attribute *attr,
527*4882a593Smuzhiyun const char *buf, size_t count)
528*4882a593Smuzhiyun {
529*4882a593Smuzhiyun struct mv_otg *mvotg = dev_get_drvdata(dev);
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun if (count > 2)
532*4882a593Smuzhiyun return -1;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun /* We will use this interface to change to A device */
535*4882a593Smuzhiyun if (mvotg->phy.otg->state != OTG_STATE_B_IDLE
536*4882a593Smuzhiyun && mvotg->phy.otg->state != OTG_STATE_A_IDLE)
537*4882a593Smuzhiyun return -1;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun /* The clock may disabled and we need to set irq for ID detected */
540*4882a593Smuzhiyun mv_otg_enable(mvotg);
541*4882a593Smuzhiyun mv_otg_init_irq(mvotg);
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun if (buf[0] == '1') {
544*4882a593Smuzhiyun mvotg->otg_ctrl.a_bus_req = 1;
545*4882a593Smuzhiyun mvotg->otg_ctrl.a_bus_drop = 0;
546*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev,
547*4882a593Smuzhiyun "User request: a_bus_req = 1\n");
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun if (spin_trylock(&mvotg->wq_lock)) {
550*4882a593Smuzhiyun mv_otg_run_state_machine(mvotg, 0);
551*4882a593Smuzhiyun spin_unlock(&mvotg->wq_lock);
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun return count;
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun static DEVICE_ATTR_RW(a_bus_req);
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun static ssize_t
a_clr_err_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)561*4882a593Smuzhiyun a_clr_err_store(struct device *dev, struct device_attribute *attr,
562*4882a593Smuzhiyun const char *buf, size_t count)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun struct mv_otg *mvotg = dev_get_drvdata(dev);
565*4882a593Smuzhiyun if (!mvotg->phy.otg->default_a)
566*4882a593Smuzhiyun return -1;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun if (count > 2)
569*4882a593Smuzhiyun return -1;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun if (buf[0] == '1') {
572*4882a593Smuzhiyun mvotg->otg_ctrl.a_clr_err = 1;
573*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev,
574*4882a593Smuzhiyun "User request: a_clr_err = 1\n");
575*4882a593Smuzhiyun }
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun if (spin_trylock(&mvotg->wq_lock)) {
578*4882a593Smuzhiyun mv_otg_run_state_machine(mvotg, 0);
579*4882a593Smuzhiyun spin_unlock(&mvotg->wq_lock);
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun return count;
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun static DEVICE_ATTR_WO(a_clr_err);
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun static ssize_t
a_bus_drop_show(struct device * dev,struct device_attribute * attr,char * buf)588*4882a593Smuzhiyun a_bus_drop_show(struct device *dev, struct device_attribute *attr,
589*4882a593Smuzhiyun char *buf)
590*4882a593Smuzhiyun {
591*4882a593Smuzhiyun struct mv_otg *mvotg = dev_get_drvdata(dev);
592*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%d\n",
593*4882a593Smuzhiyun mvotg->otg_ctrl.a_bus_drop);
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun static ssize_t
a_bus_drop_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)597*4882a593Smuzhiyun a_bus_drop_store(struct device *dev, struct device_attribute *attr,
598*4882a593Smuzhiyun const char *buf, size_t count)
599*4882a593Smuzhiyun {
600*4882a593Smuzhiyun struct mv_otg *mvotg = dev_get_drvdata(dev);
601*4882a593Smuzhiyun if (!mvotg->phy.otg->default_a)
602*4882a593Smuzhiyun return -1;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun if (count > 2)
605*4882a593Smuzhiyun return -1;
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun if (buf[0] == '0') {
608*4882a593Smuzhiyun mvotg->otg_ctrl.a_bus_drop = 0;
609*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev,
610*4882a593Smuzhiyun "User request: a_bus_drop = 0\n");
611*4882a593Smuzhiyun } else if (buf[0] == '1') {
612*4882a593Smuzhiyun mvotg->otg_ctrl.a_bus_drop = 1;
613*4882a593Smuzhiyun mvotg->otg_ctrl.a_bus_req = 0;
614*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev,
615*4882a593Smuzhiyun "User request: a_bus_drop = 1\n");
616*4882a593Smuzhiyun dev_dbg(&mvotg->pdev->dev,
617*4882a593Smuzhiyun "User request: and a_bus_req = 0\n");
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun if (spin_trylock(&mvotg->wq_lock)) {
621*4882a593Smuzhiyun mv_otg_run_state_machine(mvotg, 0);
622*4882a593Smuzhiyun spin_unlock(&mvotg->wq_lock);
623*4882a593Smuzhiyun }
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun return count;
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun static DEVICE_ATTR_RW(a_bus_drop);
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun static struct attribute *inputs_attrs[] = {
631*4882a593Smuzhiyun &dev_attr_a_bus_req.attr,
632*4882a593Smuzhiyun &dev_attr_a_clr_err.attr,
633*4882a593Smuzhiyun &dev_attr_a_bus_drop.attr,
634*4882a593Smuzhiyun NULL,
635*4882a593Smuzhiyun };
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun static const struct attribute_group inputs_attr_group = {
638*4882a593Smuzhiyun .name = "inputs",
639*4882a593Smuzhiyun .attrs = inputs_attrs,
640*4882a593Smuzhiyun };
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun static const struct attribute_group *mv_otg_groups[] = {
643*4882a593Smuzhiyun &inputs_attr_group,
644*4882a593Smuzhiyun NULL,
645*4882a593Smuzhiyun };
646*4882a593Smuzhiyun
mv_otg_remove(struct platform_device * pdev)647*4882a593Smuzhiyun static int mv_otg_remove(struct platform_device *pdev)
648*4882a593Smuzhiyun {
649*4882a593Smuzhiyun struct mv_otg *mvotg = platform_get_drvdata(pdev);
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun if (mvotg->qwork) {
652*4882a593Smuzhiyun flush_workqueue(mvotg->qwork);
653*4882a593Smuzhiyun destroy_workqueue(mvotg->qwork);
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun mv_otg_disable(mvotg);
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun usb_remove_phy(&mvotg->phy);
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun return 0;
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun
mv_otg_probe(struct platform_device * pdev)663*4882a593Smuzhiyun static int mv_otg_probe(struct platform_device *pdev)
664*4882a593Smuzhiyun {
665*4882a593Smuzhiyun struct mv_usb_platform_data *pdata = dev_get_platdata(&pdev->dev);
666*4882a593Smuzhiyun struct mv_otg *mvotg;
667*4882a593Smuzhiyun struct usb_otg *otg;
668*4882a593Smuzhiyun struct resource *r;
669*4882a593Smuzhiyun int retval = 0, i;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun if (pdata == NULL) {
672*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get platform data\n");
673*4882a593Smuzhiyun return -ENODEV;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun mvotg = devm_kzalloc(&pdev->dev, sizeof(*mvotg), GFP_KERNEL);
677*4882a593Smuzhiyun if (!mvotg)
678*4882a593Smuzhiyun return -ENOMEM;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
681*4882a593Smuzhiyun if (!otg)
682*4882a593Smuzhiyun return -ENOMEM;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun platform_set_drvdata(pdev, mvotg);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun mvotg->pdev = pdev;
687*4882a593Smuzhiyun mvotg->pdata = pdata;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun mvotg->clk = devm_clk_get(&pdev->dev, NULL);
690*4882a593Smuzhiyun if (IS_ERR(mvotg->clk))
691*4882a593Smuzhiyun return PTR_ERR(mvotg->clk);
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun mvotg->qwork = create_singlethread_workqueue("mv_otg_queue");
694*4882a593Smuzhiyun if (!mvotg->qwork) {
695*4882a593Smuzhiyun dev_dbg(&pdev->dev, "cannot create workqueue for OTG\n");
696*4882a593Smuzhiyun return -ENOMEM;
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun INIT_DELAYED_WORK(&mvotg->work, mv_otg_work);
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun /* OTG common part */
702*4882a593Smuzhiyun mvotg->pdev = pdev;
703*4882a593Smuzhiyun mvotg->phy.dev = &pdev->dev;
704*4882a593Smuzhiyun mvotg->phy.otg = otg;
705*4882a593Smuzhiyun mvotg->phy.label = driver_name;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun otg->state = OTG_STATE_UNDEFINED;
708*4882a593Smuzhiyun otg->usb_phy = &mvotg->phy;
709*4882a593Smuzhiyun otg->set_host = mv_otg_set_host;
710*4882a593Smuzhiyun otg->set_peripheral = mv_otg_set_peripheral;
711*4882a593Smuzhiyun otg->set_vbus = mv_otg_set_vbus;
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun for (i = 0; i < OTG_TIMER_NUM; i++)
714*4882a593Smuzhiyun timer_setup(&mvotg->otg_ctrl.timer[i],
715*4882a593Smuzhiyun mv_otg_timer_await_bcon, 0);
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun r = platform_get_resource_byname(mvotg->pdev,
718*4882a593Smuzhiyun IORESOURCE_MEM, "phyregs");
719*4882a593Smuzhiyun if (r == NULL) {
720*4882a593Smuzhiyun dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
721*4882a593Smuzhiyun retval = -ENODEV;
722*4882a593Smuzhiyun goto err_destroy_workqueue;
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun mvotg->phy_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
726*4882a593Smuzhiyun if (mvotg->phy_regs == NULL) {
727*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to map phy I/O memory\n");
728*4882a593Smuzhiyun retval = -EFAULT;
729*4882a593Smuzhiyun goto err_destroy_workqueue;
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun r = platform_get_resource_byname(mvotg->pdev,
733*4882a593Smuzhiyun IORESOURCE_MEM, "capregs");
734*4882a593Smuzhiyun if (r == NULL) {
735*4882a593Smuzhiyun dev_err(&pdev->dev, "no I/O memory resource defined\n");
736*4882a593Smuzhiyun retval = -ENODEV;
737*4882a593Smuzhiyun goto err_destroy_workqueue;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun mvotg->cap_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
741*4882a593Smuzhiyun if (mvotg->cap_regs == NULL) {
742*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to map I/O memory\n");
743*4882a593Smuzhiyun retval = -EFAULT;
744*4882a593Smuzhiyun goto err_destroy_workqueue;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun /* we will acces controller register, so enable the udc controller */
748*4882a593Smuzhiyun retval = mv_otg_enable_internal(mvotg);
749*4882a593Smuzhiyun if (retval) {
750*4882a593Smuzhiyun dev_err(&pdev->dev, "mv otg enable error %d\n", retval);
751*4882a593Smuzhiyun goto err_destroy_workqueue;
752*4882a593Smuzhiyun }
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun mvotg->op_regs =
755*4882a593Smuzhiyun (struct mv_otg_regs __iomem *) ((unsigned long) mvotg->cap_regs
756*4882a593Smuzhiyun + (readl(mvotg->cap_regs) & CAPLENGTH_MASK));
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun if (pdata->id) {
759*4882a593Smuzhiyun retval = devm_request_threaded_irq(&pdev->dev, pdata->id->irq,
760*4882a593Smuzhiyun NULL, mv_otg_inputs_irq,
761*4882a593Smuzhiyun IRQF_ONESHOT, "id", mvotg);
762*4882a593Smuzhiyun if (retval) {
763*4882a593Smuzhiyun dev_info(&pdev->dev,
764*4882a593Smuzhiyun "Failed to request irq for ID\n");
765*4882a593Smuzhiyun pdata->id = NULL;
766*4882a593Smuzhiyun }
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun if (pdata->vbus) {
770*4882a593Smuzhiyun mvotg->clock_gating = 1;
771*4882a593Smuzhiyun retval = devm_request_threaded_irq(&pdev->dev, pdata->vbus->irq,
772*4882a593Smuzhiyun NULL, mv_otg_inputs_irq,
773*4882a593Smuzhiyun IRQF_ONESHOT, "vbus", mvotg);
774*4882a593Smuzhiyun if (retval) {
775*4882a593Smuzhiyun dev_info(&pdev->dev,
776*4882a593Smuzhiyun "Failed to request irq for VBUS, "
777*4882a593Smuzhiyun "disable clock gating\n");
778*4882a593Smuzhiyun mvotg->clock_gating = 0;
779*4882a593Smuzhiyun pdata->vbus = NULL;
780*4882a593Smuzhiyun }
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun if (pdata->disable_otg_clock_gating)
784*4882a593Smuzhiyun mvotg->clock_gating = 0;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun mv_otg_reset(mvotg);
787*4882a593Smuzhiyun mv_otg_init_irq(mvotg);
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun r = platform_get_resource(mvotg->pdev, IORESOURCE_IRQ, 0);
790*4882a593Smuzhiyun if (r == NULL) {
791*4882a593Smuzhiyun dev_err(&pdev->dev, "no IRQ resource defined\n");
792*4882a593Smuzhiyun retval = -ENODEV;
793*4882a593Smuzhiyun goto err_disable_clk;
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun mvotg->irq = r->start;
797*4882a593Smuzhiyun if (devm_request_irq(&pdev->dev, mvotg->irq, mv_otg_irq, IRQF_SHARED,
798*4882a593Smuzhiyun driver_name, mvotg)) {
799*4882a593Smuzhiyun dev_err(&pdev->dev, "Request irq %d for OTG failed\n",
800*4882a593Smuzhiyun mvotg->irq);
801*4882a593Smuzhiyun mvotg->irq = 0;
802*4882a593Smuzhiyun retval = -ENODEV;
803*4882a593Smuzhiyun goto err_disable_clk;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun retval = usb_add_phy(&mvotg->phy, USB_PHY_TYPE_USB2);
807*4882a593Smuzhiyun if (retval < 0) {
808*4882a593Smuzhiyun dev_err(&pdev->dev, "can't register transceiver, %d\n",
809*4882a593Smuzhiyun retval);
810*4882a593Smuzhiyun goto err_disable_clk;
811*4882a593Smuzhiyun }
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun spin_lock_init(&mvotg->wq_lock);
814*4882a593Smuzhiyun if (spin_trylock(&mvotg->wq_lock)) {
815*4882a593Smuzhiyun mv_otg_run_state_machine(mvotg, 2 * HZ);
816*4882a593Smuzhiyun spin_unlock(&mvotg->wq_lock);
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun dev_info(&pdev->dev,
820*4882a593Smuzhiyun "successful probe OTG device %s clock gating.\n",
821*4882a593Smuzhiyun mvotg->clock_gating ? "with" : "without");
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun return 0;
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun err_disable_clk:
826*4882a593Smuzhiyun mv_otg_disable_internal(mvotg);
827*4882a593Smuzhiyun err_destroy_workqueue:
828*4882a593Smuzhiyun flush_workqueue(mvotg->qwork);
829*4882a593Smuzhiyun destroy_workqueue(mvotg->qwork);
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun return retval;
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun #ifdef CONFIG_PM
mv_otg_suspend(struct platform_device * pdev,pm_message_t state)835*4882a593Smuzhiyun static int mv_otg_suspend(struct platform_device *pdev, pm_message_t state)
836*4882a593Smuzhiyun {
837*4882a593Smuzhiyun struct mv_otg *mvotg = platform_get_drvdata(pdev);
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun if (mvotg->phy.otg->state != OTG_STATE_B_IDLE) {
840*4882a593Smuzhiyun dev_info(&pdev->dev,
841*4882a593Smuzhiyun "OTG state is not B_IDLE, it is %d!\n",
842*4882a593Smuzhiyun mvotg->phy.otg->state);
843*4882a593Smuzhiyun return -EAGAIN;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun if (!mvotg->clock_gating)
847*4882a593Smuzhiyun mv_otg_disable_internal(mvotg);
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun return 0;
850*4882a593Smuzhiyun }
851*4882a593Smuzhiyun
mv_otg_resume(struct platform_device * pdev)852*4882a593Smuzhiyun static int mv_otg_resume(struct platform_device *pdev)
853*4882a593Smuzhiyun {
854*4882a593Smuzhiyun struct mv_otg *mvotg = platform_get_drvdata(pdev);
855*4882a593Smuzhiyun u32 otgsc;
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun if (!mvotg->clock_gating) {
858*4882a593Smuzhiyun mv_otg_enable_internal(mvotg);
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun otgsc = readl(&mvotg->op_regs->otgsc);
861*4882a593Smuzhiyun otgsc |= mvotg->irq_en;
862*4882a593Smuzhiyun writel(otgsc, &mvotg->op_regs->otgsc);
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun if (spin_trylock(&mvotg->wq_lock)) {
865*4882a593Smuzhiyun mv_otg_run_state_machine(mvotg, 0);
866*4882a593Smuzhiyun spin_unlock(&mvotg->wq_lock);
867*4882a593Smuzhiyun }
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun return 0;
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun #endif
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun static struct platform_driver mv_otg_driver = {
874*4882a593Smuzhiyun .probe = mv_otg_probe,
875*4882a593Smuzhiyun .remove = mv_otg_remove,
876*4882a593Smuzhiyun .driver = {
877*4882a593Smuzhiyun .name = driver_name,
878*4882a593Smuzhiyun .dev_groups = mv_otg_groups,
879*4882a593Smuzhiyun },
880*4882a593Smuzhiyun #ifdef CONFIG_PM
881*4882a593Smuzhiyun .suspend = mv_otg_suspend,
882*4882a593Smuzhiyun .resume = mv_otg_resume,
883*4882a593Smuzhiyun #endif
884*4882a593Smuzhiyun };
885*4882a593Smuzhiyun module_platform_driver(mv_otg_driver);
886