xref: /OK3568_Linux_fs/kernel/drivers/usb/musb/omap2430.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2005-2007 by Texas Instruments
4*4882a593Smuzhiyun  * Some code has been taken from tusb6010.c
5*4882a593Smuzhiyun  * Copyrights for that are attributable to:
6*4882a593Smuzhiyun  * Copyright (C) 2006 Nokia Corporation
7*4882a593Smuzhiyun  * Tony Lindgren <tony@atomide.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This file is part of the Inventra Controller Driver for Linux.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/sched.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/list.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/dma-mapping.h>
20*4882a593Smuzhiyun #include <linux/pm_runtime.h>
21*4882a593Smuzhiyun #include <linux/err.h>
22*4882a593Smuzhiyun #include <linux/delay.h>
23*4882a593Smuzhiyun #include <linux/usb/musb.h>
24*4882a593Smuzhiyun #include <linux/phy/omap_control_phy.h>
25*4882a593Smuzhiyun #include <linux/of_platform.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "musb_core.h"
28*4882a593Smuzhiyun #include "omap2430.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct omap2430_glue {
31*4882a593Smuzhiyun 	struct device		*dev;
32*4882a593Smuzhiyun 	struct platform_device	*musb;
33*4882a593Smuzhiyun 	enum musb_vbus_id_status status;
34*4882a593Smuzhiyun 	struct work_struct	omap_musb_mailbox_work;
35*4882a593Smuzhiyun 	struct device		*control_otghs;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun #define glue_to_musb(g)		platform_get_drvdata(g->musb)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun static struct omap2430_glue	*_glue;
40*4882a593Smuzhiyun 
omap2430_low_level_exit(struct musb * musb)41*4882a593Smuzhiyun static inline void omap2430_low_level_exit(struct musb *musb)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	u32 l;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	/* in any role */
46*4882a593Smuzhiyun 	l = musb_readl(musb->mregs, OTG_FORCESTDBY);
47*4882a593Smuzhiyun 	l |= ENABLEFORCE;	/* enable MSTANDBY */
48*4882a593Smuzhiyun 	musb_writel(musb->mregs, OTG_FORCESTDBY, l);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
omap2430_low_level_init(struct musb * musb)51*4882a593Smuzhiyun static inline void omap2430_low_level_init(struct musb *musb)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	u32 l;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	l = musb_readl(musb->mregs, OTG_FORCESTDBY);
56*4882a593Smuzhiyun 	l &= ~ENABLEFORCE;	/* disable MSTANDBY */
57*4882a593Smuzhiyun 	musb_writel(musb->mregs, OTG_FORCESTDBY, l);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
omap2430_musb_mailbox(enum musb_vbus_id_status status)60*4882a593Smuzhiyun static int omap2430_musb_mailbox(enum musb_vbus_id_status status)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	struct omap2430_glue	*glue = _glue;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	if (!glue) {
65*4882a593Smuzhiyun 		pr_err("%s: musb core is not yet initialized\n", __func__);
66*4882a593Smuzhiyun 		return -EPROBE_DEFER;
67*4882a593Smuzhiyun 	}
68*4882a593Smuzhiyun 	glue->status = status;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	if (!glue_to_musb(glue)) {
71*4882a593Smuzhiyun 		pr_err("%s: musb core is not yet ready\n", __func__);
72*4882a593Smuzhiyun 		return -EPROBE_DEFER;
73*4882a593Smuzhiyun 	}
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	schedule_work(&glue->omap_musb_mailbox_work);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun  * HDRC controls CPEN, but beware current surges during device connect.
82*4882a593Smuzhiyun  * They can trigger transient overcurrent conditions that must be ignored.
83*4882a593Smuzhiyun  *
84*4882a593Smuzhiyun  * Note that we're skipping A_WAIT_VFALL -> A_IDLE and jumping right to B_IDLE
85*4882a593Smuzhiyun  * as set by musb_set_peripheral().
86*4882a593Smuzhiyun  */
omap_musb_set_mailbox(struct omap2430_glue * glue)87*4882a593Smuzhiyun static void omap_musb_set_mailbox(struct omap2430_glue *glue)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	struct musb *musb = glue_to_musb(glue);
90*4882a593Smuzhiyun 	int error;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	pm_runtime_get_sync(musb->controller);
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	dev_dbg(musb->controller, "VBUS %s, devctl %02x\n",
95*4882a593Smuzhiyun 		usb_otg_state_string(musb->xceiv->otg->state),
96*4882a593Smuzhiyun 		musb_readb(musb->mregs, MUSB_DEVCTL));
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	switch (glue->status) {
99*4882a593Smuzhiyun 	case MUSB_ID_GROUND:
100*4882a593Smuzhiyun 		dev_dbg(musb->controller, "ID GND\n");
101*4882a593Smuzhiyun 		switch (musb->xceiv->otg->state) {
102*4882a593Smuzhiyun 		case OTG_STATE_A_IDLE:
103*4882a593Smuzhiyun 			error = musb_set_host(musb);
104*4882a593Smuzhiyun 			if (error)
105*4882a593Smuzhiyun 				break;
106*4882a593Smuzhiyun 			musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
107*4882a593Smuzhiyun 			fallthrough;
108*4882a593Smuzhiyun 		case OTG_STATE_A_WAIT_VRISE:
109*4882a593Smuzhiyun 		case OTG_STATE_A_WAIT_BCON:
110*4882a593Smuzhiyun 		case OTG_STATE_A_HOST:
111*4882a593Smuzhiyun 			/*
112*4882a593Smuzhiyun 			 * On multiple ID ground interrupts just keep enabling
113*4882a593Smuzhiyun 			 * VBUS. At least cpcap VBUS shuts down otherwise.
114*4882a593Smuzhiyun 			 */
115*4882a593Smuzhiyun 			otg_set_vbus(musb->xceiv->otg, 1);
116*4882a593Smuzhiyun 			break;
117*4882a593Smuzhiyun 		default:
118*4882a593Smuzhiyun 			musb->xceiv->otg->state = OTG_STATE_A_IDLE;
119*4882a593Smuzhiyun 			musb->xceiv->last_event = USB_EVENT_ID;
120*4882a593Smuzhiyun 			if (musb->gadget_driver) {
121*4882a593Smuzhiyun 				omap_control_usb_set_mode(glue->control_otghs,
122*4882a593Smuzhiyun 							  USB_MODE_HOST);
123*4882a593Smuzhiyun 				otg_set_vbus(musb->xceiv->otg, 1);
124*4882a593Smuzhiyun 			}
125*4882a593Smuzhiyun 			break;
126*4882a593Smuzhiyun 		}
127*4882a593Smuzhiyun 		break;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	case MUSB_VBUS_VALID:
130*4882a593Smuzhiyun 		dev_dbg(musb->controller, "VBUS Connect\n");
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 		musb->xceiv->otg->state = OTG_STATE_B_IDLE;
133*4882a593Smuzhiyun 		musb->xceiv->last_event = USB_EVENT_VBUS;
134*4882a593Smuzhiyun 		omap_control_usb_set_mode(glue->control_otghs, USB_MODE_DEVICE);
135*4882a593Smuzhiyun 		break;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	case MUSB_ID_FLOAT:
138*4882a593Smuzhiyun 	case MUSB_VBUS_OFF:
139*4882a593Smuzhiyun 		dev_dbg(musb->controller, "VBUS Disconnect\n");
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 		musb->xceiv->last_event = USB_EVENT_NONE;
142*4882a593Smuzhiyun 		musb_set_peripheral(musb);
143*4882a593Smuzhiyun 		otg_set_vbus(musb->xceiv->otg, 0);
144*4882a593Smuzhiyun 		omap_control_usb_set_mode(glue->control_otghs,
145*4882a593Smuzhiyun 			USB_MODE_DISCONNECT);
146*4882a593Smuzhiyun 		break;
147*4882a593Smuzhiyun 	default:
148*4882a593Smuzhiyun 		dev_dbg(musb->controller, "ID float\n");
149*4882a593Smuzhiyun 	}
150*4882a593Smuzhiyun 	pm_runtime_mark_last_busy(musb->controller);
151*4882a593Smuzhiyun 	pm_runtime_put_autosuspend(musb->controller);
152*4882a593Smuzhiyun 	atomic_notifier_call_chain(&musb->xceiv->notifier,
153*4882a593Smuzhiyun 			musb->xceiv->last_event, NULL);
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 
omap_musb_mailbox_work(struct work_struct * mailbox_work)157*4882a593Smuzhiyun static void omap_musb_mailbox_work(struct work_struct *mailbox_work)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	struct omap2430_glue *glue = container_of(mailbox_work,
160*4882a593Smuzhiyun 				struct omap2430_glue, omap_musb_mailbox_work);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	omap_musb_set_mailbox(glue);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
omap2430_musb_interrupt(int irq,void * __hci)165*4882a593Smuzhiyun static irqreturn_t omap2430_musb_interrupt(int irq, void *__hci)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	unsigned long   flags;
168*4882a593Smuzhiyun 	irqreturn_t     retval = IRQ_NONE;
169*4882a593Smuzhiyun 	struct musb     *musb = __hci;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	spin_lock_irqsave(&musb->lock, flags);
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
174*4882a593Smuzhiyun 	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
175*4882a593Smuzhiyun 	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	if (musb->int_usb || musb->int_tx || musb->int_rx)
178*4882a593Smuzhiyun 		retval = musb_interrupt(musb);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	spin_unlock_irqrestore(&musb->lock, flags);
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	return retval;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun 
omap2430_musb_init(struct musb * musb)185*4882a593Smuzhiyun static int omap2430_musb_init(struct musb *musb)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	u32 l;
188*4882a593Smuzhiyun 	int status = 0;
189*4882a593Smuzhiyun 	struct device *dev = musb->controller;
190*4882a593Smuzhiyun 	struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
191*4882a593Smuzhiyun 	struct omap_musb_board_data *data = plat->board_data;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	/* We require some kind of external transceiver, hooked
194*4882a593Smuzhiyun 	 * up through ULPI.  TWL4030-family PMICs include one,
195*4882a593Smuzhiyun 	 * which needs a driver, drivers aren't always needed.
196*4882a593Smuzhiyun 	 */
197*4882a593Smuzhiyun 	musb->phy = devm_phy_get(dev->parent, "usb2-phy");
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	/* We can't totally remove musb->xceiv as of now because
200*4882a593Smuzhiyun 	 * musb core uses xceiv.state and xceiv.otg. Once we have
201*4882a593Smuzhiyun 	 * a separate state machine to handle otg, these can be moved
202*4882a593Smuzhiyun 	 * out of xceiv and then we can start using the generic PHY
203*4882a593Smuzhiyun 	 * framework
204*4882a593Smuzhiyun 	 */
205*4882a593Smuzhiyun 	musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "usb-phy", 0);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	if (IS_ERR(musb->xceiv)) {
208*4882a593Smuzhiyun 		status = PTR_ERR(musb->xceiv);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 		if (status == -ENXIO)
211*4882a593Smuzhiyun 			return status;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 		dev_dbg(dev, "HS USB OTG: no transceiver configured\n");
214*4882a593Smuzhiyun 		return -EPROBE_DEFER;
215*4882a593Smuzhiyun 	}
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	if (IS_ERR(musb->phy)) {
218*4882a593Smuzhiyun 		dev_err(dev, "HS USB OTG: no PHY configured\n");
219*4882a593Smuzhiyun 		return PTR_ERR(musb->phy);
220*4882a593Smuzhiyun 	}
221*4882a593Smuzhiyun 	musb->isr = omap2430_musb_interrupt;
222*4882a593Smuzhiyun 	phy_init(musb->phy);
223*4882a593Smuzhiyun 	phy_power_on(musb->phy);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	l = musb_readl(musb->mregs, OTG_INTERFSEL);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	if (data->interface_type == MUSB_INTERFACE_UTMI) {
228*4882a593Smuzhiyun 		/* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
229*4882a593Smuzhiyun 		l &= ~ULPI_12PIN;       /* Disable ULPI */
230*4882a593Smuzhiyun 		l |= UTMI_8BIT;         /* Enable UTMI  */
231*4882a593Smuzhiyun 	} else {
232*4882a593Smuzhiyun 		l |= ULPI_12PIN;
233*4882a593Smuzhiyun 	}
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	musb_writel(musb->mregs, OTG_INTERFSEL, l);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	dev_dbg(dev, "HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
238*4882a593Smuzhiyun 			"sysstatus 0x%x, intrfsel 0x%x, simenable  0x%x\n",
239*4882a593Smuzhiyun 			musb_readl(musb->mregs, OTG_REVISION),
240*4882a593Smuzhiyun 			musb_readl(musb->mregs, OTG_SYSCONFIG),
241*4882a593Smuzhiyun 			musb_readl(musb->mregs, OTG_SYSSTATUS),
242*4882a593Smuzhiyun 			musb_readl(musb->mregs, OTG_INTERFSEL),
243*4882a593Smuzhiyun 			musb_readl(musb->mregs, OTG_SIMENABLE));
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	return 0;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun 
omap2430_musb_enable(struct musb * musb)248*4882a593Smuzhiyun static void omap2430_musb_enable(struct musb *musb)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun 	struct device *dev = musb->controller;
251*4882a593Smuzhiyun 	struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	if (glue->status == MUSB_UNKNOWN)
254*4882a593Smuzhiyun 		glue->status = MUSB_VBUS_OFF;
255*4882a593Smuzhiyun 	omap_musb_set_mailbox(glue);
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun 
omap2430_musb_disable(struct musb * musb)258*4882a593Smuzhiyun static void omap2430_musb_disable(struct musb *musb)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	struct device *dev = musb->controller;
261*4882a593Smuzhiyun 	struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	if (glue->status != MUSB_UNKNOWN)
264*4882a593Smuzhiyun 		omap_control_usb_set_mode(glue->control_otghs,
265*4882a593Smuzhiyun 			USB_MODE_DISCONNECT);
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun 
omap2430_musb_exit(struct musb * musb)268*4882a593Smuzhiyun static int omap2430_musb_exit(struct musb *musb)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun 	struct device *dev = musb->controller;
271*4882a593Smuzhiyun 	struct omap2430_glue *glue = dev_get_drvdata(dev->parent);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	omap2430_low_level_exit(musb);
274*4882a593Smuzhiyun 	phy_power_off(musb->phy);
275*4882a593Smuzhiyun 	phy_exit(musb->phy);
276*4882a593Smuzhiyun 	musb->phy = NULL;
277*4882a593Smuzhiyun 	cancel_work_sync(&glue->omap_musb_mailbox_work);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	return 0;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun static const struct musb_platform_ops omap2430_ops = {
283*4882a593Smuzhiyun 	.quirks		= MUSB_DMA_INVENTRA,
284*4882a593Smuzhiyun #ifdef CONFIG_USB_INVENTRA_DMA
285*4882a593Smuzhiyun 	.dma_init	= musbhs_dma_controller_create,
286*4882a593Smuzhiyun 	.dma_exit	= musbhs_dma_controller_destroy,
287*4882a593Smuzhiyun #endif
288*4882a593Smuzhiyun 	.init		= omap2430_musb_init,
289*4882a593Smuzhiyun 	.exit		= omap2430_musb_exit,
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	.enable		= omap2430_musb_enable,
292*4882a593Smuzhiyun 	.disable	= omap2430_musb_disable,
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	.phy_callback	= omap2430_musb_mailbox,
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun static u64 omap2430_dmamask = DMA_BIT_MASK(32);
298*4882a593Smuzhiyun 
omap2430_probe(struct platform_device * pdev)299*4882a593Smuzhiyun static int omap2430_probe(struct platform_device *pdev)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun 	struct resource			musb_resources[3];
302*4882a593Smuzhiyun 	struct musb_hdrc_platform_data	*pdata = dev_get_platdata(&pdev->dev);
303*4882a593Smuzhiyun 	struct omap_musb_board_data	*data;
304*4882a593Smuzhiyun 	struct platform_device		*musb;
305*4882a593Smuzhiyun 	struct omap2430_glue		*glue;
306*4882a593Smuzhiyun 	struct device_node		*np = pdev->dev.of_node;
307*4882a593Smuzhiyun 	struct musb_hdrc_config		*config;
308*4882a593Smuzhiyun 	struct device_node		*control_node;
309*4882a593Smuzhiyun 	struct platform_device		*control_pdev;
310*4882a593Smuzhiyun 	int				ret = -ENOMEM, val;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	if (!np)
313*4882a593Smuzhiyun 		return -ENODEV;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
316*4882a593Smuzhiyun 	if (!glue)
317*4882a593Smuzhiyun 		goto err0;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
320*4882a593Smuzhiyun 	if (!musb) {
321*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to allocate musb device\n");
322*4882a593Smuzhiyun 		goto err0;
323*4882a593Smuzhiyun 	}
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	musb->dev.parent		= &pdev->dev;
326*4882a593Smuzhiyun 	musb->dev.dma_mask		= &omap2430_dmamask;
327*4882a593Smuzhiyun 	musb->dev.coherent_dma_mask	= omap2430_dmamask;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	glue->dev			= &pdev->dev;
330*4882a593Smuzhiyun 	glue->musb			= musb;
331*4882a593Smuzhiyun 	glue->status			= MUSB_UNKNOWN;
332*4882a593Smuzhiyun 	glue->control_otghs = ERR_PTR(-ENODEV);
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
335*4882a593Smuzhiyun 	if (!pdata)
336*4882a593Smuzhiyun 		goto err2;
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
339*4882a593Smuzhiyun 	if (!data)
340*4882a593Smuzhiyun 		goto err2;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	config = devm_kzalloc(&pdev->dev, sizeof(*config), GFP_KERNEL);
343*4882a593Smuzhiyun 	if (!config)
344*4882a593Smuzhiyun 		goto err2;
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	of_property_read_u32(np, "mode", (u32 *)&pdata->mode);
347*4882a593Smuzhiyun 	of_property_read_u32(np, "interface-type",
348*4882a593Smuzhiyun 			(u32 *)&data->interface_type);
349*4882a593Smuzhiyun 	of_property_read_u32(np, "num-eps", (u32 *)&config->num_eps);
350*4882a593Smuzhiyun 	of_property_read_u32(np, "ram-bits", (u32 *)&config->ram_bits);
351*4882a593Smuzhiyun 	of_property_read_u32(np, "power", (u32 *)&pdata->power);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	ret = of_property_read_u32(np, "multipoint", &val);
354*4882a593Smuzhiyun 	if (!ret && val)
355*4882a593Smuzhiyun 		config->multipoint = true;
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	pdata->board_data	= data;
358*4882a593Smuzhiyun 	pdata->config		= config;
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	control_node = of_parse_phandle(np, "ctrl-module", 0);
361*4882a593Smuzhiyun 	if (control_node) {
362*4882a593Smuzhiyun 		control_pdev = of_find_device_by_node(control_node);
363*4882a593Smuzhiyun 		of_node_put(control_node);
364*4882a593Smuzhiyun 		if (!control_pdev) {
365*4882a593Smuzhiyun 			dev_err(&pdev->dev, "Failed to get control device\n");
366*4882a593Smuzhiyun 			ret = -EINVAL;
367*4882a593Smuzhiyun 			goto err2;
368*4882a593Smuzhiyun 		}
369*4882a593Smuzhiyun 		glue->control_otghs = &control_pdev->dev;
370*4882a593Smuzhiyun 	}
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	pdata->platform_ops		= &omap2430_ops;
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	platform_set_drvdata(pdev, glue);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	/*
377*4882a593Smuzhiyun 	 * REVISIT if we ever have two instances of the wrapper, we will be
378*4882a593Smuzhiyun 	 * in big trouble
379*4882a593Smuzhiyun 	 */
380*4882a593Smuzhiyun 	_glue	= glue;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	INIT_WORK(&glue->omap_musb_mailbox_work, omap_musb_mailbox_work);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	memset(musb_resources, 0x00, sizeof(*musb_resources) *
385*4882a593Smuzhiyun 			ARRAY_SIZE(musb_resources));
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	musb_resources[0].name = pdev->resource[0].name;
388*4882a593Smuzhiyun 	musb_resources[0].start = pdev->resource[0].start;
389*4882a593Smuzhiyun 	musb_resources[0].end = pdev->resource[0].end;
390*4882a593Smuzhiyun 	musb_resources[0].flags = pdev->resource[0].flags;
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	musb_resources[1].name = pdev->resource[1].name;
393*4882a593Smuzhiyun 	musb_resources[1].start = pdev->resource[1].start;
394*4882a593Smuzhiyun 	musb_resources[1].end = pdev->resource[1].end;
395*4882a593Smuzhiyun 	musb_resources[1].flags = pdev->resource[1].flags;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	musb_resources[2].name = pdev->resource[2].name;
398*4882a593Smuzhiyun 	musb_resources[2].start = pdev->resource[2].start;
399*4882a593Smuzhiyun 	musb_resources[2].end = pdev->resource[2].end;
400*4882a593Smuzhiyun 	musb_resources[2].flags = pdev->resource[2].flags;
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	ret = platform_device_add_resources(musb, musb_resources,
403*4882a593Smuzhiyun 			ARRAY_SIZE(musb_resources));
404*4882a593Smuzhiyun 	if (ret) {
405*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to add resources\n");
406*4882a593Smuzhiyun 		goto err2;
407*4882a593Smuzhiyun 	}
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
410*4882a593Smuzhiyun 	if (ret) {
411*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to add platform_data\n");
412*4882a593Smuzhiyun 		goto err2;
413*4882a593Smuzhiyun 	}
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	pm_runtime_enable(glue->dev);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	ret = platform_device_add(musb);
418*4882a593Smuzhiyun 	if (ret) {
419*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to register musb device\n");
420*4882a593Smuzhiyun 		goto err3;
421*4882a593Smuzhiyun 	}
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	return 0;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun err3:
426*4882a593Smuzhiyun 	pm_runtime_disable(glue->dev);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun err2:
429*4882a593Smuzhiyun 	platform_device_put(musb);
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun err0:
432*4882a593Smuzhiyun 	return ret;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun 
omap2430_remove(struct platform_device * pdev)435*4882a593Smuzhiyun static int omap2430_remove(struct platform_device *pdev)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun 	struct omap2430_glue *glue = platform_get_drvdata(pdev);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	platform_device_unregister(glue->musb);
440*4882a593Smuzhiyun 	pm_runtime_disable(glue->dev);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	return 0;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun #ifdef CONFIG_PM
446*4882a593Smuzhiyun 
omap2430_runtime_suspend(struct device * dev)447*4882a593Smuzhiyun static int omap2430_runtime_suspend(struct device *dev)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun 	struct omap2430_glue		*glue = dev_get_drvdata(dev);
450*4882a593Smuzhiyun 	struct musb			*musb = glue_to_musb(glue);
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	if (!musb)
453*4882a593Smuzhiyun 		return 0;
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	musb->context.otg_interfsel = musb_readl(musb->mregs,
456*4882a593Smuzhiyun 						 OTG_INTERFSEL);
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	omap2430_low_level_exit(musb);
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun 	phy_power_off(musb->phy);
461*4882a593Smuzhiyun 	phy_exit(musb->phy);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	return 0;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun 
omap2430_runtime_resume(struct device * dev)466*4882a593Smuzhiyun static int omap2430_runtime_resume(struct device *dev)
467*4882a593Smuzhiyun {
468*4882a593Smuzhiyun 	struct omap2430_glue		*glue = dev_get_drvdata(dev);
469*4882a593Smuzhiyun 	struct musb			*musb = glue_to_musb(glue);
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	if (!musb)
472*4882a593Smuzhiyun 		return 0;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	phy_init(musb->phy);
475*4882a593Smuzhiyun 	phy_power_on(musb->phy);
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	omap2430_low_level_init(musb);
478*4882a593Smuzhiyun 	musb_writel(musb->mregs, OTG_INTERFSEL,
479*4882a593Smuzhiyun 		    musb->context.otg_interfsel);
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	/* Wait for musb to get oriented. Otherwise we can get babble */
482*4882a593Smuzhiyun 	usleep_range(200000, 250000);
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	return 0;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun static const struct dev_pm_ops omap2430_pm_ops = {
488*4882a593Smuzhiyun 	.runtime_suspend = omap2430_runtime_suspend,
489*4882a593Smuzhiyun 	.runtime_resume = omap2430_runtime_resume,
490*4882a593Smuzhiyun };
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun #define DEV_PM_OPS	(&omap2430_pm_ops)
493*4882a593Smuzhiyun #else
494*4882a593Smuzhiyun #define DEV_PM_OPS	NULL
495*4882a593Smuzhiyun #endif
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun #ifdef CONFIG_OF
498*4882a593Smuzhiyun static const struct of_device_id omap2430_id_table[] = {
499*4882a593Smuzhiyun 	{
500*4882a593Smuzhiyun 		.compatible = "ti,omap4-musb"
501*4882a593Smuzhiyun 	},
502*4882a593Smuzhiyun 	{
503*4882a593Smuzhiyun 		.compatible = "ti,omap3-musb"
504*4882a593Smuzhiyun 	},
505*4882a593Smuzhiyun 	{},
506*4882a593Smuzhiyun };
507*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, omap2430_id_table);
508*4882a593Smuzhiyun #endif
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun static struct platform_driver omap2430_driver = {
511*4882a593Smuzhiyun 	.probe		= omap2430_probe,
512*4882a593Smuzhiyun 	.remove		= omap2430_remove,
513*4882a593Smuzhiyun 	.driver		= {
514*4882a593Smuzhiyun 		.name	= "musb-omap2430",
515*4882a593Smuzhiyun 		.pm	= DEV_PM_OPS,
516*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(omap2430_id_table),
517*4882a593Smuzhiyun 	},
518*4882a593Smuzhiyun };
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun module_platform_driver(omap2430_driver);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun MODULE_DESCRIPTION("OMAP2PLUS MUSB Glue Layer");
523*4882a593Smuzhiyun MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
524*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
525