1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2005-2006 by Texas Instruments */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _CPPI_DMA_H_ 5*4882a593Smuzhiyun #define _CPPI_DMA_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/slab.h> 8*4882a593Smuzhiyun #include <linux/list.h> 9*4882a593Smuzhiyun #include <linux/errno.h> 10*4882a593Smuzhiyun #include <linux/dmapool.h> 11*4882a593Smuzhiyun #include <linux/dmaengine.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "musb_core.h" 14*4882a593Smuzhiyun #include "musb_dma.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* CPPI RX/TX state RAM */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct cppi_tx_stateram { 19*4882a593Smuzhiyun u32 tx_head; /* "DMA packet" head descriptor */ 20*4882a593Smuzhiyun u32 tx_buf; 21*4882a593Smuzhiyun u32 tx_current; /* current descriptor */ 22*4882a593Smuzhiyun u32 tx_buf_current; 23*4882a593Smuzhiyun u32 tx_info; /* flags, remaining buflen */ 24*4882a593Smuzhiyun u32 tx_rem_len; 25*4882a593Smuzhiyun u32 tx_dummy; /* unused */ 26*4882a593Smuzhiyun u32 tx_complete; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct cppi_rx_stateram { 30*4882a593Smuzhiyun u32 rx_skipbytes; 31*4882a593Smuzhiyun u32 rx_head; 32*4882a593Smuzhiyun u32 rx_sop; /* "DMA packet" head descriptor */ 33*4882a593Smuzhiyun u32 rx_current; /* current descriptor */ 34*4882a593Smuzhiyun u32 rx_buf_current; 35*4882a593Smuzhiyun u32 rx_len_len; 36*4882a593Smuzhiyun u32 rx_cnt_cnt; 37*4882a593Smuzhiyun u32 rx_complete; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* hw_options bits in CPPI buffer descriptors */ 41*4882a593Smuzhiyun #define CPPI_SOP_SET ((u32)(1 << 31)) 42*4882a593Smuzhiyun #define CPPI_EOP_SET ((u32)(1 << 30)) 43*4882a593Smuzhiyun #define CPPI_OWN_SET ((u32)(1 << 29)) /* owned by cppi */ 44*4882a593Smuzhiyun #define CPPI_EOQ_MASK ((u32)(1 << 28)) 45*4882a593Smuzhiyun #define CPPI_ZERO_SET ((u32)(1 << 23)) /* rx saw zlp; tx issues one */ 46*4882a593Smuzhiyun #define CPPI_RXABT_MASK ((u32)(1 << 19)) /* need more rx buffers */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define CPPI_RECV_PKTLEN_MASK 0xFFFF 49*4882a593Smuzhiyun #define CPPI_BUFFER_LEN_MASK 0xFFFF 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CPPI_TEAR_READY ((u32)(1 << 31)) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* CPPI data structure definitions */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CPPI_DESCRIPTOR_ALIGN 16 /* bytes; 5-dec docs say 4-byte align */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct cppi_descriptor { 58*4882a593Smuzhiyun /* hardware overlay */ 59*4882a593Smuzhiyun u32 hw_next; /* next buffer descriptor Pointer */ 60*4882a593Smuzhiyun u32 hw_bufp; /* i/o buffer pointer */ 61*4882a593Smuzhiyun u32 hw_off_len; /* buffer_offset16, buffer_length16 */ 62*4882a593Smuzhiyun u32 hw_options; /* flags: SOP, EOP etc*/ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct cppi_descriptor *next; 65*4882a593Smuzhiyun dma_addr_t dma; /* address of this descriptor */ 66*4882a593Smuzhiyun u32 buflen; /* for RX: original buffer length */ 67*4882a593Smuzhiyun } __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN))); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct cppi; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* CPPI Channel Control structure */ 73*4882a593Smuzhiyun struct cppi_channel { 74*4882a593Smuzhiyun struct dma_channel channel; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* back pointer to the DMA controller structure */ 77*4882a593Smuzhiyun struct cppi *controller; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* which direction of which endpoint? */ 80*4882a593Smuzhiyun struct musb_hw_ep *hw_ep; 81*4882a593Smuzhiyun bool transmit; 82*4882a593Smuzhiyun u8 index; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* DMA modes: RNDIS or "transparent" */ 85*4882a593Smuzhiyun u8 is_rndis; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* book keeping for current transfer request */ 88*4882a593Smuzhiyun dma_addr_t buf_dma; 89*4882a593Smuzhiyun u32 buf_len; 90*4882a593Smuzhiyun u32 maxpacket; 91*4882a593Smuzhiyun u32 offset; /* dma requested */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun void __iomem *state_ram; /* CPPI state */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct cppi_descriptor *freelist; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* BD management fields */ 98*4882a593Smuzhiyun struct cppi_descriptor *head; 99*4882a593Smuzhiyun struct cppi_descriptor *tail; 100*4882a593Smuzhiyun struct cppi_descriptor *last_processed; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* use tx_complete in host role to track endpoints waiting for 103*4882a593Smuzhiyun * FIFONOTEMPTY to clear. 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun struct list_head tx_complete; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* CPPI DMA controller object */ 109*4882a593Smuzhiyun struct cppi { 110*4882a593Smuzhiyun struct dma_controller controller; 111*4882a593Smuzhiyun void __iomem *mregs; /* Mentor regs */ 112*4882a593Smuzhiyun void __iomem *tibase; /* TI/CPPI regs */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun int irq; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun struct cppi_channel tx[4]; 117*4882a593Smuzhiyun struct cppi_channel rx[4]; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun struct dma_pool *pool; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun struct list_head tx_complete; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* CPPI IRQ handler */ 125*4882a593Smuzhiyun extern irqreturn_t cppi_interrupt(int, void *); 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun struct cppi41_dma_channel { 128*4882a593Smuzhiyun struct dma_channel channel; 129*4882a593Smuzhiyun struct cppi41_dma_controller *controller; 130*4882a593Smuzhiyun struct musb_hw_ep *hw_ep; 131*4882a593Smuzhiyun struct dma_chan *dc; 132*4882a593Smuzhiyun dma_cookie_t cookie; 133*4882a593Smuzhiyun u8 port_num; 134*4882a593Smuzhiyun u8 is_tx; 135*4882a593Smuzhiyun u8 is_allocated; 136*4882a593Smuzhiyun u8 usb_toggle; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun dma_addr_t buf_addr; 139*4882a593Smuzhiyun u32 total_len; 140*4882a593Smuzhiyun u32 prog_len; 141*4882a593Smuzhiyun u32 transferred; 142*4882a593Smuzhiyun u32 packet_sz; 143*4882a593Smuzhiyun struct list_head tx_check; 144*4882a593Smuzhiyun int tx_zlp; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #endif /* end of ifndef _CPPI_DMA_H_ */ 148