1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * mtu3_dr.c - dual role switch and host glue layer
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 MediaTek Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/iopoll.h>
12*4882a593Smuzhiyun #include <linux/irq.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "mtu3.h"
19*4882a593Smuzhiyun #include "mtu3_dr.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* mt8173 etc */
22*4882a593Smuzhiyun #define PERI_WK_CTRL1 0x4
23*4882a593Smuzhiyun #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
24*4882a593Smuzhiyun #define WC1_IS_EN BIT(25)
25*4882a593Smuzhiyun #define WC1_IS_P BIT(6) /* polarity for ip sleep */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* mt2712 etc */
28*4882a593Smuzhiyun #define PERI_SSUSB_SPM_CTRL 0x0
29*4882a593Smuzhiyun #define SSC_IP_SLEEP_EN BIT(4)
30*4882a593Smuzhiyun #define SSC_SPM_INT_EN BIT(1)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun enum ssusb_uwk_vers {
33*4882a593Smuzhiyun SSUSB_UWK_V1 = 1,
34*4882a593Smuzhiyun SSUSB_UWK_V2,
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * ip-sleep wakeup mode:
39*4882a593Smuzhiyun * all clocks can be turn off, but power domain should be kept on
40*4882a593Smuzhiyun */
ssusb_wakeup_ip_sleep_set(struct ssusb_mtk * ssusb,bool enable)41*4882a593Smuzhiyun static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun u32 reg, msk, val;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun switch (ssusb->uwk_vers) {
46*4882a593Smuzhiyun case SSUSB_UWK_V1:
47*4882a593Smuzhiyun reg = ssusb->uwk_reg_base + PERI_WK_CTRL1;
48*4882a593Smuzhiyun msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
49*4882a593Smuzhiyun val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
50*4882a593Smuzhiyun break;
51*4882a593Smuzhiyun case SSUSB_UWK_V2:
52*4882a593Smuzhiyun reg = ssusb->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
53*4882a593Smuzhiyun msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
54*4882a593Smuzhiyun val = enable ? msk : 0;
55*4882a593Smuzhiyun break;
56*4882a593Smuzhiyun default:
57*4882a593Smuzhiyun return;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun regmap_update_bits(ssusb->uwk, reg, msk, val);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
ssusb_wakeup_of_property_parse(struct ssusb_mtk * ssusb,struct device_node * dn)62*4882a593Smuzhiyun int ssusb_wakeup_of_property_parse(struct ssusb_mtk *ssusb,
63*4882a593Smuzhiyun struct device_node *dn)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct of_phandle_args args;
66*4882a593Smuzhiyun int ret;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* wakeup function is optional */
69*4882a593Smuzhiyun ssusb->uwk_en = of_property_read_bool(dn, "wakeup-source");
70*4882a593Smuzhiyun if (!ssusb->uwk_en)
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun ret = of_parse_phandle_with_fixed_args(dn,
74*4882a593Smuzhiyun "mediatek,syscon-wakeup", 2, 0, &args);
75*4882a593Smuzhiyun if (ret)
76*4882a593Smuzhiyun return ret;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun ssusb->uwk_reg_base = args.args[0];
79*4882a593Smuzhiyun ssusb->uwk_vers = args.args[1];
80*4882a593Smuzhiyun ssusb->uwk = syscon_node_to_regmap(args.np);
81*4882a593Smuzhiyun of_node_put(args.np);
82*4882a593Smuzhiyun dev_info(ssusb->dev, "uwk - reg:0x%x, version:%d\n",
83*4882a593Smuzhiyun ssusb->uwk_reg_base, ssusb->uwk_vers);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(ssusb->uwk);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
ssusb_wakeup_set(struct ssusb_mtk * ssusb,bool enable)88*4882a593Smuzhiyun void ssusb_wakeup_set(struct ssusb_mtk *ssusb, bool enable)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun if (ssusb->uwk_en)
91*4882a593Smuzhiyun ssusb_wakeup_ip_sleep_set(ssusb, enable);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
host_ports_num_get(struct ssusb_mtk * ssusb)94*4882a593Smuzhiyun static void host_ports_num_get(struct ssusb_mtk *ssusb)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun u32 xhci_cap;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun xhci_cap = mtu3_readl(ssusb->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
99*4882a593Smuzhiyun ssusb->u2_ports = SSUSB_IP_XHCI_U2_PORT_NUM(xhci_cap);
100*4882a593Smuzhiyun ssusb->u3_ports = SSUSB_IP_XHCI_U3_PORT_NUM(xhci_cap);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun dev_dbg(ssusb->dev, "host - u2_ports:%d, u3_ports:%d\n",
103*4882a593Smuzhiyun ssusb->u2_ports, ssusb->u3_ports);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* only configure ports will be used later */
ssusb_host_enable(struct ssusb_mtk * ssusb)107*4882a593Smuzhiyun int ssusb_host_enable(struct ssusb_mtk *ssusb)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun void __iomem *ibase = ssusb->ippc_base;
110*4882a593Smuzhiyun int num_u3p = ssusb->u3_ports;
111*4882a593Smuzhiyun int num_u2p = ssusb->u2_ports;
112*4882a593Smuzhiyun int u3_ports_disabed;
113*4882a593Smuzhiyun u32 check_clk;
114*4882a593Smuzhiyun u32 value;
115*4882a593Smuzhiyun int i;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* power on host ip */
118*4882a593Smuzhiyun mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* power on and enable u3 ports except skipped ones */
121*4882a593Smuzhiyun u3_ports_disabed = 0;
122*4882a593Smuzhiyun for (i = 0; i < num_u3p; i++) {
123*4882a593Smuzhiyun if ((0x1 << i) & ssusb->u3p_dis_msk) {
124*4882a593Smuzhiyun u3_ports_disabed++;
125*4882a593Smuzhiyun continue;
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
129*4882a593Smuzhiyun value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
130*4882a593Smuzhiyun value |= SSUSB_U3_PORT_HOST_SEL;
131*4882a593Smuzhiyun mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* power on and enable all u2 ports */
135*4882a593Smuzhiyun for (i = 0; i < num_u2p; i++) {
136*4882a593Smuzhiyun value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
137*4882a593Smuzhiyun value &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS);
138*4882a593Smuzhiyun value |= SSUSB_U2_PORT_HOST_SEL;
139*4882a593Smuzhiyun mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun check_clk = SSUSB_XHCI_RST_B_STS;
143*4882a593Smuzhiyun if (num_u3p > u3_ports_disabed)
144*4882a593Smuzhiyun check_clk = SSUSB_U3_MAC_RST_B_STS;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun return ssusb_check_clocks(ssusb, check_clk);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
ssusb_host_disable(struct ssusb_mtk * ssusb,bool suspend)149*4882a593Smuzhiyun int ssusb_host_disable(struct ssusb_mtk *ssusb, bool suspend)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun void __iomem *ibase = ssusb->ippc_base;
152*4882a593Smuzhiyun int num_u3p = ssusb->u3_ports;
153*4882a593Smuzhiyun int num_u2p = ssusb->u2_ports;
154*4882a593Smuzhiyun u32 value;
155*4882a593Smuzhiyun int ret;
156*4882a593Smuzhiyun int i;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* power down and disable u3 ports except skipped ones */
159*4882a593Smuzhiyun for (i = 0; i < num_u3p; i++) {
160*4882a593Smuzhiyun if ((0x1 << i) & ssusb->u3p_dis_msk)
161*4882a593Smuzhiyun continue;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
164*4882a593Smuzhiyun value |= SSUSB_U3_PORT_PDN;
165*4882a593Smuzhiyun value |= suspend ? 0 : SSUSB_U3_PORT_DIS;
166*4882a593Smuzhiyun mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /* power down and disable all u2 ports */
170*4882a593Smuzhiyun for (i = 0; i < num_u2p; i++) {
171*4882a593Smuzhiyun value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
172*4882a593Smuzhiyun value |= SSUSB_U2_PORT_PDN;
173*4882a593Smuzhiyun value |= suspend ? 0 : SSUSB_U2_PORT_DIS;
174*4882a593Smuzhiyun mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* power down host ip */
178*4882a593Smuzhiyun mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun if (!suspend)
181*4882a593Smuzhiyun return 0;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun /* wait for host ip to sleep */
184*4882a593Smuzhiyun ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
185*4882a593Smuzhiyun (value & SSUSB_IP_SLEEP_STS), 100, 100000);
186*4882a593Smuzhiyun if (ret)
187*4882a593Smuzhiyun dev_err(ssusb->dev, "ip sleep failed!!!\n");
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return ret;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
ssusb_host_setup(struct ssusb_mtk * ssusb)192*4882a593Smuzhiyun static void ssusb_host_setup(struct ssusb_mtk *ssusb)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun host_ports_num_get(ssusb);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /*
199*4882a593Smuzhiyun * power on host and power on/enable all ports
200*4882a593Smuzhiyun * if support OTG, gadget driver will switch port0 to device mode
201*4882a593Smuzhiyun */
202*4882a593Smuzhiyun ssusb_host_enable(ssusb);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun if (otg_sx->manual_drd_enabled)
205*4882a593Smuzhiyun ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* if port0 supports dual-role, works as host mode by default */
208*4882a593Smuzhiyun ssusb_set_vbus(&ssusb->otg_switch, 1);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
ssusb_host_cleanup(struct ssusb_mtk * ssusb)211*4882a593Smuzhiyun static void ssusb_host_cleanup(struct ssusb_mtk *ssusb)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun if (ssusb->is_host)
214*4882a593Smuzhiyun ssusb_set_vbus(&ssusb->otg_switch, 0);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun ssusb_host_disable(ssusb, false);
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun /*
220*4882a593Smuzhiyun * If host supports multiple ports, the VBUSes(5V) of ports except port0
221*4882a593Smuzhiyun * which supports OTG are better to be enabled by default in DTS.
222*4882a593Smuzhiyun * Because the host driver will keep link with devices attached when system
223*4882a593Smuzhiyun * enters suspend mode, so no need to control VBUSes after initialization.
224*4882a593Smuzhiyun */
ssusb_host_init(struct ssusb_mtk * ssusb,struct device_node * parent_dn)225*4882a593Smuzhiyun int ssusb_host_init(struct ssusb_mtk *ssusb, struct device_node *parent_dn)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun struct device *parent_dev = ssusb->dev;
228*4882a593Smuzhiyun int ret;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun ssusb_host_setup(ssusb);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun ret = of_platform_populate(parent_dn, NULL, NULL, parent_dev);
233*4882a593Smuzhiyun if (ret) {
234*4882a593Smuzhiyun dev_dbg(parent_dev, "failed to create child devices at %pOF\n",
235*4882a593Smuzhiyun parent_dn);
236*4882a593Smuzhiyun return ret;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun dev_info(parent_dev, "xHCI platform device register success...\n");
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun return 0;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
ssusb_host_exit(struct ssusb_mtk * ssusb)244*4882a593Smuzhiyun void ssusb_host_exit(struct ssusb_mtk *ssusb)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun of_platform_depopulate(ssusb->dev);
247*4882a593Smuzhiyun ssusb_host_cleanup(ssusb);
248*4882a593Smuzhiyun }
249