1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for the NXP ISP1760 chip 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2014 Laurent Pinchart 6*4882a593Smuzhiyun * Copyright 2007 Sebastian Siewior 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Contacts: 9*4882a593Smuzhiyun * Sebastian Siewior <bigeasy@linutronix.de> 10*4882a593Smuzhiyun * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef _ISP1760_REGS_H_ 14*4882a593Smuzhiyun #define _ISP1760_REGS_H_ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* ----------------------------------------------------------------------------- 17*4882a593Smuzhiyun * Host Controller 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* EHCI capability registers */ 21*4882a593Smuzhiyun #define HC_CAPLENGTH 0x000 22*4882a593Smuzhiyun #define HC_LENGTH(p) (((p) >> 00) & 0x00ff) /* bits 7:0 */ 23*4882a593Smuzhiyun #define HC_VERSION(p) (((p) >> 16) & 0xffff) /* bits 31:16 */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define HC_HCSPARAMS 0x004 26*4882a593Smuzhiyun #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */ 27*4882a593Smuzhiyun #define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */ 28*4882a593Smuzhiyun #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define HC_HCCPARAMS 0x008 31*4882a593Smuzhiyun #define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */ 32*4882a593Smuzhiyun #define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* EHCI operational registers */ 35*4882a593Smuzhiyun #define HC_USBCMD 0x020 36*4882a593Smuzhiyun #define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */ 37*4882a593Smuzhiyun #define CMD_RESET (1 << 1) /* reset HC not bus */ 38*4882a593Smuzhiyun #define CMD_RUN (1 << 0) /* start/stop HC */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define HC_USBSTS 0x024 41*4882a593Smuzhiyun #define STS_PCD (1 << 2) /* port change detect */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define HC_FRINDEX 0x02c 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define HC_CONFIGFLAG 0x060 46*4882a593Smuzhiyun #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define HC_PORTSC1 0x064 49*4882a593Smuzhiyun #define PORT_OWNER (1 << 13) /* true: companion hc owns this port */ 50*4882a593Smuzhiyun #define PORT_POWER (1 << 12) /* true: has power (see PPC) */ 51*4882a593Smuzhiyun #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */ 52*4882a593Smuzhiyun #define PORT_RESET (1 << 8) /* reset port */ 53*4882a593Smuzhiyun #define PORT_SUSPEND (1 << 7) /* suspend port */ 54*4882a593Smuzhiyun #define PORT_RESUME (1 << 6) /* resume it */ 55*4882a593Smuzhiyun #define PORT_PE (1 << 2) /* port enable */ 56*4882a593Smuzhiyun #define PORT_CSC (1 << 1) /* connect status change */ 57*4882a593Smuzhiyun #define PORT_CONNECT (1 << 0) /* device connected */ 58*4882a593Smuzhiyun #define PORT_RWC_BITS (PORT_CSC) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define HC_ISO_PTD_DONEMAP_REG 0x130 61*4882a593Smuzhiyun #define HC_ISO_PTD_SKIPMAP_REG 0x134 62*4882a593Smuzhiyun #define HC_ISO_PTD_LASTPTD_REG 0x138 63*4882a593Smuzhiyun #define HC_INT_PTD_DONEMAP_REG 0x140 64*4882a593Smuzhiyun #define HC_INT_PTD_SKIPMAP_REG 0x144 65*4882a593Smuzhiyun #define HC_INT_PTD_LASTPTD_REG 0x148 66*4882a593Smuzhiyun #define HC_ATL_PTD_DONEMAP_REG 0x150 67*4882a593Smuzhiyun #define HC_ATL_PTD_SKIPMAP_REG 0x154 68*4882a593Smuzhiyun #define HC_ATL_PTD_LASTPTD_REG 0x158 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Configuration Register */ 71*4882a593Smuzhiyun #define HC_HW_MODE_CTRL 0x300 72*4882a593Smuzhiyun #define ALL_ATX_RESET (1 << 31) 73*4882a593Smuzhiyun #define HW_ANA_DIGI_OC (1 << 15) 74*4882a593Smuzhiyun #define HW_DEV_DMA (1 << 11) 75*4882a593Smuzhiyun #define HW_COMN_IRQ (1 << 10) 76*4882a593Smuzhiyun #define HW_COMN_DMA (1 << 9) 77*4882a593Smuzhiyun #define HW_DATA_BUS_32BIT (1 << 8) 78*4882a593Smuzhiyun #define HW_DACK_POL_HIGH (1 << 6) 79*4882a593Smuzhiyun #define HW_DREQ_POL_HIGH (1 << 5) 80*4882a593Smuzhiyun #define HW_INTR_HIGH_ACT (1 << 2) 81*4882a593Smuzhiyun #define HW_INTR_EDGE_TRIG (1 << 1) 82*4882a593Smuzhiyun #define HW_GLOBAL_INTR_EN (1 << 0) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define HC_CHIP_ID_REG 0x304 85*4882a593Smuzhiyun #define HC_SCRATCH_REG 0x308 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define HC_RESET_REG 0x30c 88*4882a593Smuzhiyun #define SW_RESET_RESET_HC (1 << 1) 89*4882a593Smuzhiyun #define SW_RESET_RESET_ALL (1 << 0) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define HC_BUFFER_STATUS_REG 0x334 92*4882a593Smuzhiyun #define ISO_BUF_FILL (1 << 2) 93*4882a593Smuzhiyun #define INT_BUF_FILL (1 << 1) 94*4882a593Smuzhiyun #define ATL_BUF_FILL (1 << 0) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define HC_MEMORY_REG 0x33c 97*4882a593Smuzhiyun #define ISP_BANK(x) ((x) << 16) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define HC_PORT1_CTRL 0x374 100*4882a593Smuzhiyun #define PORT1_POWER (3 << 3) 101*4882a593Smuzhiyun #define PORT1_INIT1 (1 << 7) 102*4882a593Smuzhiyun #define PORT1_INIT2 (1 << 23) 103*4882a593Smuzhiyun #define HW_OTG_CTRL_SET 0x374 104*4882a593Smuzhiyun #define HW_OTG_CTRL_CLR 0x376 105*4882a593Smuzhiyun #define HW_OTG_DISABLE (1 << 10) 106*4882a593Smuzhiyun #define HW_OTG_SE0_EN (1 << 9) 107*4882a593Smuzhiyun #define HW_BDIS_ACON_EN (1 << 8) 108*4882a593Smuzhiyun #define HW_SW_SEL_HC_DC (1 << 7) 109*4882a593Smuzhiyun #define HW_VBUS_CHRG (1 << 6) 110*4882a593Smuzhiyun #define HW_VBUS_DISCHRG (1 << 5) 111*4882a593Smuzhiyun #define HW_VBUS_DRV (1 << 4) 112*4882a593Smuzhiyun #define HW_SEL_CP_EXT (1 << 3) 113*4882a593Smuzhiyun #define HW_DM_PULLDOWN (1 << 2) 114*4882a593Smuzhiyun #define HW_DP_PULLDOWN (1 << 1) 115*4882a593Smuzhiyun #define HW_DP_PULLUP (1 << 0) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* Interrupt Register */ 118*4882a593Smuzhiyun #define HC_INTERRUPT_REG 0x310 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define HC_INTERRUPT_ENABLE 0x314 121*4882a593Smuzhiyun #define HC_ISO_INT (1 << 9) 122*4882a593Smuzhiyun #define HC_ATL_INT (1 << 8) 123*4882a593Smuzhiyun #define HC_INTL_INT (1 << 7) 124*4882a593Smuzhiyun #define HC_EOT_INT (1 << 3) 125*4882a593Smuzhiyun #define HC_SOT_INT (1 << 1) 126*4882a593Smuzhiyun #define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT) 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define HC_ISO_IRQ_MASK_OR_REG 0x318 129*4882a593Smuzhiyun #define HC_INT_IRQ_MASK_OR_REG 0x31c 130*4882a593Smuzhiyun #define HC_ATL_IRQ_MASK_OR_REG 0x320 131*4882a593Smuzhiyun #define HC_ISO_IRQ_MASK_AND_REG 0x324 132*4882a593Smuzhiyun #define HC_INT_IRQ_MASK_AND_REG 0x328 133*4882a593Smuzhiyun #define HC_ATL_IRQ_MASK_AND_REG 0x32c 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* ----------------------------------------------------------------------------- 136*4882a593Smuzhiyun * Peripheral Controller 137*4882a593Smuzhiyun */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* Initialization Registers */ 140*4882a593Smuzhiyun #define DC_ADDRESS 0x0200 141*4882a593Smuzhiyun #define DC_DEVEN (1 << 7) 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define DC_MODE 0x020c 144*4882a593Smuzhiyun #define DC_DMACLKON (1 << 9) 145*4882a593Smuzhiyun #define DC_VBUSSTAT (1 << 8) 146*4882a593Smuzhiyun #define DC_CLKAON (1 << 7) 147*4882a593Smuzhiyun #define DC_SNDRSU (1 << 6) 148*4882a593Smuzhiyun #define DC_GOSUSP (1 << 5) 149*4882a593Smuzhiyun #define DC_SFRESET (1 << 4) 150*4882a593Smuzhiyun #define DC_GLINTENA (1 << 3) 151*4882a593Smuzhiyun #define DC_WKUPCS (1 << 2) 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define DC_INTCONF 0x0210 154*4882a593Smuzhiyun #define DC_CDBGMOD_ACK_NAK (0 << 6) 155*4882a593Smuzhiyun #define DC_CDBGMOD_ACK (1 << 6) 156*4882a593Smuzhiyun #define DC_CDBGMOD_ACK_1NAK (2 << 6) 157*4882a593Smuzhiyun #define DC_DDBGMODIN_ACK_NAK (0 << 4) 158*4882a593Smuzhiyun #define DC_DDBGMODIN_ACK (1 << 4) 159*4882a593Smuzhiyun #define DC_DDBGMODIN_ACK_1NAK (2 << 4) 160*4882a593Smuzhiyun #define DC_DDBGMODOUT_ACK_NYET_NAK (0 << 2) 161*4882a593Smuzhiyun #define DC_DDBGMODOUT_ACK_NYET (1 << 2) 162*4882a593Smuzhiyun #define DC_DDBGMODOUT_ACK_NYET_1NAK (2 << 2) 163*4882a593Smuzhiyun #define DC_INTLVL (1 << 1) 164*4882a593Smuzhiyun #define DC_INTPOL (1 << 0) 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define DC_DEBUG 0x0212 167*4882a593Smuzhiyun #define DC_INTENABLE 0x0214 168*4882a593Smuzhiyun #define DC_IEPTX(n) (1 << (11 + 2 * (n))) 169*4882a593Smuzhiyun #define DC_IEPRX(n) (1 << (10 + 2 * (n))) 170*4882a593Smuzhiyun #define DC_IEPRXTX(n) (3 << (10 + 2 * (n))) 171*4882a593Smuzhiyun #define DC_IEP0SETUP (1 << 8) 172*4882a593Smuzhiyun #define DC_IEVBUS (1 << 7) 173*4882a593Smuzhiyun #define DC_IEDMA (1 << 6) 174*4882a593Smuzhiyun #define DC_IEHS_STA (1 << 5) 175*4882a593Smuzhiyun #define DC_IERESM (1 << 4) 176*4882a593Smuzhiyun #define DC_IESUSP (1 << 3) 177*4882a593Smuzhiyun #define DC_IEPSOF (1 << 2) 178*4882a593Smuzhiyun #define DC_IESOF (1 << 1) 179*4882a593Smuzhiyun #define DC_IEBRST (1 << 0) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* Data Flow Registers */ 182*4882a593Smuzhiyun #define DC_EPINDEX 0x022c 183*4882a593Smuzhiyun #define DC_EP0SETUP (1 << 5) 184*4882a593Smuzhiyun #define DC_ENDPIDX(n) ((n) << 1) 185*4882a593Smuzhiyun #define DC_EPDIR (1 << 0) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define DC_CTRLFUNC 0x0228 188*4882a593Smuzhiyun #define DC_CLBUF (1 << 4) 189*4882a593Smuzhiyun #define DC_VENDP (1 << 3) 190*4882a593Smuzhiyun #define DC_DSEN (1 << 2) 191*4882a593Smuzhiyun #define DC_STATUS (1 << 1) 192*4882a593Smuzhiyun #define DC_STALL (1 << 0) 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun #define DC_DATAPORT 0x0220 195*4882a593Smuzhiyun #define DC_BUFLEN 0x021c 196*4882a593Smuzhiyun #define DC_DATACOUNT_MASK 0xffff 197*4882a593Smuzhiyun #define DC_BUFSTAT 0x021e 198*4882a593Smuzhiyun #define DC_EPMAXPKTSZ 0x0204 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #define DC_EPTYPE 0x0208 201*4882a593Smuzhiyun #define DC_NOEMPKT (1 << 4) 202*4882a593Smuzhiyun #define DC_EPENABLE (1 << 3) 203*4882a593Smuzhiyun #define DC_DBLBUF (1 << 2) 204*4882a593Smuzhiyun #define DC_ENDPTYP_ISOC (1 << 0) 205*4882a593Smuzhiyun #define DC_ENDPTYP_BULK (2 << 0) 206*4882a593Smuzhiyun #define DC_ENDPTYP_INTERRUPT (3 << 0) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* DMA Registers */ 209*4882a593Smuzhiyun #define DC_DMACMD 0x0230 210*4882a593Smuzhiyun #define DC_DMATXCOUNT 0x0234 211*4882a593Smuzhiyun #define DC_DMACONF 0x0238 212*4882a593Smuzhiyun #define DC_DMAHW 0x023c 213*4882a593Smuzhiyun #define DC_DMAINTREASON 0x0250 214*4882a593Smuzhiyun #define DC_DMAINTEN 0x0254 215*4882a593Smuzhiyun #define DC_DMAEP 0x0258 216*4882a593Smuzhiyun #define DC_DMABURSTCOUNT 0x0264 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* General Registers */ 219*4882a593Smuzhiyun #define DC_INTERRUPT 0x0218 220*4882a593Smuzhiyun #define DC_CHIPID 0x0270 221*4882a593Smuzhiyun #define DC_FRAMENUM 0x0274 222*4882a593Smuzhiyun #define DC_SCRATCH 0x0278 223*4882a593Smuzhiyun #define DC_UNLOCKDEV 0x027c 224*4882a593Smuzhiyun #define DC_INTPULSEWIDTH 0x0280 225*4882a593Smuzhiyun #define DC_TESTMODE 0x0284 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun #endif 228