1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the NXP ISP1760 chip
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2014 Laurent Pinchart
6*4882a593Smuzhiyun * Copyright 2007 Sebastian Siewior
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Contacts:
9*4882a593Smuzhiyun * Sebastian Siewior <bigeasy@linutronix.de>
10*4882a593Smuzhiyun * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #ifndef _ISP1760_CORE_H_
14*4882a593Smuzhiyun #define _ISP1760_CORE_H_
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/ioport.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "isp1760-hcd.h"
19*4882a593Smuzhiyun #include "isp1760-udc.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct device;
22*4882a593Smuzhiyun struct gpio_desc;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /*
25*4882a593Smuzhiyun * Device flags that can vary from board to board. All of these
26*4882a593Smuzhiyun * indicate the most "atypical" case, so that a devflags of 0 is
27*4882a593Smuzhiyun * a sane default configuration.
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun #define ISP1760_FLAG_BUS_WIDTH_16 0x00000002 /* 16-bit data bus width */
30*4882a593Smuzhiyun #define ISP1760_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
31*4882a593Smuzhiyun #define ISP1760_FLAG_ANALOG_OC 0x00000008 /* Analog overcurrent */
32*4882a593Smuzhiyun #define ISP1760_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
33*4882a593Smuzhiyun #define ISP1760_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
34*4882a593Smuzhiyun #define ISP1760_FLAG_ISP1761 0x00000040 /* Chip is ISP1761 */
35*4882a593Smuzhiyun #define ISP1760_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity active high */
36*4882a593Smuzhiyun #define ISP1760_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun struct isp1760_device {
39*4882a593Smuzhiyun struct device *dev;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun void __iomem *regs;
42*4882a593Smuzhiyun unsigned int devflags;
43*4882a593Smuzhiyun struct gpio_desc *rst_gpio;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun struct isp1760_hcd hcd;
46*4882a593Smuzhiyun struct isp1760_udc udc;
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun int isp1760_register(struct resource *mem, int irq, unsigned long irqflags,
50*4882a593Smuzhiyun struct device *dev, unsigned int devflags);
51*4882a593Smuzhiyun void isp1760_unregister(struct device *dev);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun void isp1760_set_pullup(struct isp1760_device *isp, bool enable);
54*4882a593Smuzhiyun
isp1760_read32(void __iomem * base,u32 reg)55*4882a593Smuzhiyun static inline u32 isp1760_read32(void __iomem *base, u32 reg)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun return readl(base + reg);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
isp1760_write32(void __iomem * base,u32 reg,u32 val)60*4882a593Smuzhiyun static inline void isp1760_write32(void __iomem *base, u32 reg, u32 val)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun writel(val, base + reg);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #endif
66