1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/usb/host/xhci-rcar.h
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Electronics Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _XHCI_RCAR_H
9*4882a593Smuzhiyun #define _XHCI_RCAR_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define XHCI_RCAR_FIRMWARE_NAME_V1 "r8a779x_usb3_v1.dlmem"
12*4882a593Smuzhiyun #define XHCI_RCAR_FIRMWARE_NAME_V2 "r8a779x_usb3_v2.dlmem"
13*4882a593Smuzhiyun #define XHCI_RCAR_FIRMWARE_NAME_V3 "r8a779x_usb3_v3.dlmem"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_USB_XHCI_RCAR)
16*4882a593Smuzhiyun void xhci_rcar_start(struct usb_hcd *hcd);
17*4882a593Smuzhiyun int xhci_rcar_init_quirk(struct usb_hcd *hcd);
18*4882a593Smuzhiyun int xhci_rcar_resume_quirk(struct usb_hcd *hcd);
19*4882a593Smuzhiyun #else
xhci_rcar_start(struct usb_hcd * hcd)20*4882a593Smuzhiyun static inline void xhci_rcar_start(struct usb_hcd *hcd)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun
xhci_rcar_init_quirk(struct usb_hcd * hcd)24*4882a593Smuzhiyun static inline int xhci_rcar_init_quirk(struct usb_hcd *hcd)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
xhci_rcar_resume_quirk(struct usb_hcd * hcd)29*4882a593Smuzhiyun static inline int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun return 0;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun #endif
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
37*4882a593Smuzhiyun * to 1. However, these SoCs don't support 64-bit address memory
38*4882a593Smuzhiyun * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
39*4882a593Smuzhiyun * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
40*4882a593Smuzhiyun * xhci_gen_setup() by using the XHCI_NO_64BIT_SUPPORT quirk.
41*4882a593Smuzhiyun *
42*4882a593Smuzhiyun * And, since the firmware/internal CPU control the USBSTS.STS_HALT
43*4882a593Smuzhiyun * and the process speed is down when the roothub port enters U3,
44*4882a593Smuzhiyun * long delay for the handshake of STS_HALT is neeed in xhci_suspend()
45*4882a593Smuzhiyun * by using the XHCI_SLOW_SUSPEND quirk.
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun #define SET_XHCI_PLAT_PRIV_FOR_RCAR(firmware) \
48*4882a593Smuzhiyun .firmware_name = firmware, \
49*4882a593Smuzhiyun .quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH | \
50*4882a593Smuzhiyun XHCI_SLOW_SUSPEND, \
51*4882a593Smuzhiyun .init_quirk = xhci_rcar_init_quirk, \
52*4882a593Smuzhiyun .plat_start = xhci_rcar_start, \
53*4882a593Smuzhiyun .resume_quirk = xhci_rcar_resume_quirk,
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #endif /* _XHCI_RCAR_H */
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