1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2015 MediaTek Inc.
4*4882a593Smuzhiyun * Author:
5*4882a593Smuzhiyun * Zhigang.Wei <zhigang.wei@mediatek.com>
6*4882a593Smuzhiyun * Chunfeng.Yun <chunfeng.yun@mediatek.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef _XHCI_MTK_H_
10*4882a593Smuzhiyun #define _XHCI_MTK_H_
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "xhci.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /**
15*4882a593Smuzhiyun * To simplify scheduler algorithm, set a upper limit for ESIT,
16*4882a593Smuzhiyun * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
17*4882a593Smuzhiyun * round down to the limit value, that means allocating more
18*4882a593Smuzhiyun * bandwidth to it.
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun #define XHCI_MTK_MAX_ESIT 64
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /**
23*4882a593Smuzhiyun * @fs_bus_bw: array to keep track of bandwidth already used for FS
24*4882a593Smuzhiyun * @ep_list: Endpoints using this TT
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun struct mu3h_sch_tt {
27*4882a593Smuzhiyun u32 fs_bus_bw[XHCI_MTK_MAX_ESIT];
28*4882a593Smuzhiyun struct list_head ep_list;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /**
32*4882a593Smuzhiyun * struct mu3h_sch_bw_info: schedule information for bandwidth domain
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * @bus_bw: array to keep track of bandwidth already used at each uframes
35*4882a593Smuzhiyun * @bw_ep_list: eps in the bandwidth domain
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * treat a HS root port as a bandwidth domain, but treat a SS root port as
38*4882a593Smuzhiyun * two bandwidth domains, one for IN eps and another for OUT eps.
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun struct mu3h_sch_bw_info {
41*4882a593Smuzhiyun u32 bus_bw[XHCI_MTK_MAX_ESIT];
42*4882a593Smuzhiyun struct list_head bw_ep_list;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /**
46*4882a593Smuzhiyun * struct mu3h_sch_ep_info: schedule information for endpoint
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * @esit: unit is 125us, equal to 2 << Interval field in ep-context
49*4882a593Smuzhiyun * @num_budget_microframes: number of continuous uframes
50*4882a593Smuzhiyun * (@repeat==1) scheduled within the interval
51*4882a593Smuzhiyun * @bw_cost_per_microframe: bandwidth cost per microframe
52*4882a593Smuzhiyun * @endpoint: linked into bandwidth domain which it belongs to
53*4882a593Smuzhiyun * @tt_endpoint: linked into mu3h_sch_tt's list which it belongs to
54*4882a593Smuzhiyun * @sch_tt: mu3h_sch_tt linked into
55*4882a593Smuzhiyun * @ep_type: endpoint type
56*4882a593Smuzhiyun * @maxpkt: max packet size of endpoint
57*4882a593Smuzhiyun * @ep: address of usb_host_endpoint struct
58*4882a593Smuzhiyun * @allocated: the bandwidth is aready allocated from bus_bw
59*4882a593Smuzhiyun * @offset: which uframe of the interval that transfer should be
60*4882a593Smuzhiyun * scheduled first time within the interval
61*4882a593Smuzhiyun * @repeat: the time gap between two uframes that transfers are
62*4882a593Smuzhiyun * scheduled within a interval. in the simple algorithm, only
63*4882a593Smuzhiyun * assign 0 or 1 to it; 0 means using only one uframe in a
64*4882a593Smuzhiyun * interval, and 1 means using @num_budget_microframes
65*4882a593Smuzhiyun * continuous uframes
66*4882a593Smuzhiyun * @pkts: number of packets to be transferred in the scheduled uframes
67*4882a593Smuzhiyun * @cs_count: number of CS that host will trigger
68*4882a593Smuzhiyun * @burst_mode: burst mode for scheduling. 0: normal burst mode,
69*4882a593Smuzhiyun * distribute the bMaxBurst+1 packets for a single burst
70*4882a593Smuzhiyun * according to @pkts and @repeat, repeate the burst multiple
71*4882a593Smuzhiyun * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
72*4882a593Smuzhiyun * according to @pkts and @repeat. normal mode is used by
73*4882a593Smuzhiyun * default
74*4882a593Smuzhiyun * @bw_budget_table: table to record bandwidth budget per microframe
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun struct mu3h_sch_ep_info {
77*4882a593Smuzhiyun u32 esit;
78*4882a593Smuzhiyun u32 num_budget_microframes;
79*4882a593Smuzhiyun u32 bw_cost_per_microframe;
80*4882a593Smuzhiyun struct list_head endpoint;
81*4882a593Smuzhiyun struct list_head tt_endpoint;
82*4882a593Smuzhiyun struct mu3h_sch_tt *sch_tt;
83*4882a593Smuzhiyun u32 ep_type;
84*4882a593Smuzhiyun u32 maxpkt;
85*4882a593Smuzhiyun struct usb_host_endpoint *ep;
86*4882a593Smuzhiyun enum usb_device_speed speed;
87*4882a593Smuzhiyun bool allocated;
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun * mtk xHCI scheduling information put into reserved DWs
90*4882a593Smuzhiyun * in ep context
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun u32 offset;
93*4882a593Smuzhiyun u32 repeat;
94*4882a593Smuzhiyun u32 pkts;
95*4882a593Smuzhiyun u32 cs_count;
96*4882a593Smuzhiyun u32 burst_mode;
97*4882a593Smuzhiyun u32 bw_budget_table[];
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #define MU3C_U3_PORT_MAX 4
101*4882a593Smuzhiyun #define MU3C_U2_PORT_MAX 5
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /**
104*4882a593Smuzhiyun * struct mu3c_ippc_regs: MTK ssusb ip port control registers
105*4882a593Smuzhiyun * @ip_pw_ctr0~3: ip power and clock control registers
106*4882a593Smuzhiyun * @ip_pw_sts1~2: ip power and clock status registers
107*4882a593Smuzhiyun * @ip_xhci_cap: ip xHCI capability register
108*4882a593Smuzhiyun * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
109*4882a593Smuzhiyun * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
110*4882a593Smuzhiyun * @u2_phy_pll: usb2 phy pll control register
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun struct mu3c_ippc_regs {
113*4882a593Smuzhiyun __le32 ip_pw_ctr0;
114*4882a593Smuzhiyun __le32 ip_pw_ctr1;
115*4882a593Smuzhiyun __le32 ip_pw_ctr2;
116*4882a593Smuzhiyun __le32 ip_pw_ctr3;
117*4882a593Smuzhiyun __le32 ip_pw_sts1;
118*4882a593Smuzhiyun __le32 ip_pw_sts2;
119*4882a593Smuzhiyun __le32 reserved0[3];
120*4882a593Smuzhiyun __le32 ip_xhci_cap;
121*4882a593Smuzhiyun __le32 reserved1[2];
122*4882a593Smuzhiyun __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
123*4882a593Smuzhiyun __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
124*4882a593Smuzhiyun __le32 reserved2;
125*4882a593Smuzhiyun __le32 u2_phy_pll;
126*4882a593Smuzhiyun __le32 reserved3[33]; /* 0x80 ~ 0xff */
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun struct xhci_hcd_mtk {
130*4882a593Smuzhiyun struct device *dev;
131*4882a593Smuzhiyun struct usb_hcd *hcd;
132*4882a593Smuzhiyun struct mu3h_sch_bw_info *sch_array;
133*4882a593Smuzhiyun struct list_head bw_ep_chk_list;
134*4882a593Smuzhiyun struct mu3c_ippc_regs __iomem *ippc_regs;
135*4882a593Smuzhiyun bool has_ippc;
136*4882a593Smuzhiyun int num_u2_ports;
137*4882a593Smuzhiyun int num_u3_ports;
138*4882a593Smuzhiyun int u3p_dis_msk;
139*4882a593Smuzhiyun struct regulator *vusb33;
140*4882a593Smuzhiyun struct regulator *vbus;
141*4882a593Smuzhiyun struct clk *sys_clk; /* sys and mac clock */
142*4882a593Smuzhiyun struct clk *xhci_clk;
143*4882a593Smuzhiyun struct clk *ref_clk;
144*4882a593Smuzhiyun struct clk *mcu_clk;
145*4882a593Smuzhiyun struct clk *dma_clk;
146*4882a593Smuzhiyun struct regmap *pericfg;
147*4882a593Smuzhiyun struct phy **phys;
148*4882a593Smuzhiyun int num_phys;
149*4882a593Smuzhiyun bool lpm_support;
150*4882a593Smuzhiyun bool u2_lpm_disable;
151*4882a593Smuzhiyun /* usb remote wakeup */
152*4882a593Smuzhiyun bool uwk_en;
153*4882a593Smuzhiyun struct regmap *uwk;
154*4882a593Smuzhiyun u32 uwk_reg_base;
155*4882a593Smuzhiyun u32 uwk_vers;
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
hcd_to_mtk(struct usb_hcd * hcd)158*4882a593Smuzhiyun static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun return dev_get_drvdata(hcd->self.controller);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
164*4882a593Smuzhiyun void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
165*4882a593Smuzhiyun int xhci_mtk_add_ep(struct usb_hcd *hcd, struct usb_device *udev,
166*4882a593Smuzhiyun struct usb_host_endpoint *ep);
167*4882a593Smuzhiyun int xhci_mtk_drop_ep(struct usb_hcd *hcd, struct usb_device *udev,
168*4882a593Smuzhiyun struct usb_host_endpoint *ep);
169*4882a593Smuzhiyun int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
170*4882a593Smuzhiyun void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun #endif /* _XHCI_MTK_H_ */
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