1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * xHCI host controller driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2008 Intel Corp.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Sarah Sharp
8*4882a593Smuzhiyun * Some code borrowed from the Linux EHCI driver.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /* HC should halt within 16 ms, but use 32 ms as some hosts take longer */
12*4882a593Smuzhiyun #define XHCI_MAX_HALT_USEC (32 * 1000)
13*4882a593Smuzhiyun /* HC not running - set to 1 when run/stop bit is cleared. */
14*4882a593Smuzhiyun #define XHCI_STS_HALT (1<<0)
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* HCCPARAMS offset from PCI base address */
17*4882a593Smuzhiyun #define XHCI_HCC_PARAMS_OFFSET 0x10
18*4882a593Smuzhiyun /* HCCPARAMS contains the first extended capability pointer */
19*4882a593Smuzhiyun #define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Command and Status registers offset from the Operational Registers address */
22*4882a593Smuzhiyun #define XHCI_CMD_OFFSET 0x00
23*4882a593Smuzhiyun #define XHCI_STS_OFFSET 0x04
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define XHCI_MAX_EXT_CAPS 50
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Capability Register */
28*4882a593Smuzhiyun /* bits 7:0 - how long is the Capabilities register */
29*4882a593Smuzhiyun #define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Extended capability register fields */
32*4882a593Smuzhiyun #define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
33*4882a593Smuzhiyun #define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
34*4882a593Smuzhiyun #define XHCI_EXT_CAPS_VAL(p) ((p)>>16)
35*4882a593Smuzhiyun /* Extended capability IDs - ID 0 reserved */
36*4882a593Smuzhiyun #define XHCI_EXT_CAPS_LEGACY 1
37*4882a593Smuzhiyun #define XHCI_EXT_CAPS_PROTOCOL 2
38*4882a593Smuzhiyun #define XHCI_EXT_CAPS_PM 3
39*4882a593Smuzhiyun #define XHCI_EXT_CAPS_VIRT 4
40*4882a593Smuzhiyun #define XHCI_EXT_CAPS_ROUTE 5
41*4882a593Smuzhiyun /* IDs 6-9 reserved */
42*4882a593Smuzhiyun #define XHCI_EXT_CAPS_DEBUG 10
43*4882a593Smuzhiyun /* Vendor caps */
44*4882a593Smuzhiyun #define XHCI_EXT_CAPS_VENDOR_INTEL 192
45*4882a593Smuzhiyun /* USB Legacy Support Capability - section 7.1.1 */
46*4882a593Smuzhiyun #define XHCI_HC_BIOS_OWNED (1 << 16)
47*4882a593Smuzhiyun #define XHCI_HC_OS_OWNED (1 << 24)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* USB Legacy Support Capability - section 7.1.1 */
50*4882a593Smuzhiyun /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
51*4882a593Smuzhiyun #define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* USB Legacy Support Control and Status Register - section 7.1.2 */
54*4882a593Smuzhiyun /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
55*4882a593Smuzhiyun #define XHCI_LEGACY_CONTROL_OFFSET (0x04)
56*4882a593Smuzhiyun /* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
57*4882a593Smuzhiyun #define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
58*4882a593Smuzhiyun #define XHCI_LEGACY_SMI_EVENTS (0x7 << 29)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
61*4882a593Smuzhiyun #define XHCI_L1C (1 << 16)
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
64*4882a593Smuzhiyun #define XHCI_HLC (1 << 19)
65*4882a593Smuzhiyun #define XHCI_BLC (1 << 20)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* command register values to disable interrupts and halt the HC */
68*4882a593Smuzhiyun /* start/stop HC execution - do not write unless HC is halted*/
69*4882a593Smuzhiyun #define XHCI_CMD_RUN (1 << 0)
70*4882a593Smuzhiyun /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
71*4882a593Smuzhiyun #define XHCI_CMD_EIE (1 << 2)
72*4882a593Smuzhiyun /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
73*4882a593Smuzhiyun #define XHCI_CMD_HSEIE (1 << 3)
74*4882a593Smuzhiyun /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
75*4882a593Smuzhiyun #define XHCI_CMD_EWE (1 << 10)
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
80*4882a593Smuzhiyun #define XHCI_STS_CNR (1 << 11)
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #include <linux/io.h>
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /**
85*4882a593Smuzhiyun * Find the offset of the extended capabilities with capability ID id.
86*4882a593Smuzhiyun *
87*4882a593Smuzhiyun * @base PCI MMIO registers base address.
88*4882a593Smuzhiyun * @start address at which to start looking, (0 or HCC_PARAMS to start at
89*4882a593Smuzhiyun * beginning of list)
90*4882a593Smuzhiyun * @id Extended capability ID to search for, or 0 for the next
91*4882a593Smuzhiyun * capability
92*4882a593Smuzhiyun *
93*4882a593Smuzhiyun * Returns the offset of the next matching extended capability structure.
94*4882a593Smuzhiyun * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
95*4882a593Smuzhiyun * and this provides a way to find them all.
96*4882a593Smuzhiyun */
97*4882a593Smuzhiyun
xhci_find_next_ext_cap(void __iomem * base,u32 start,int id)98*4882a593Smuzhiyun static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
99*4882a593Smuzhiyun {
100*4882a593Smuzhiyun u32 val;
101*4882a593Smuzhiyun u32 next;
102*4882a593Smuzhiyun u32 offset;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun offset = start;
105*4882a593Smuzhiyun if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
106*4882a593Smuzhiyun val = readl(base + XHCI_HCC_PARAMS_OFFSET);
107*4882a593Smuzhiyun if (val == ~0)
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun offset = XHCI_HCC_EXT_CAPS(val) << 2;
110*4882a593Smuzhiyun if (!offset)
111*4882a593Smuzhiyun return 0;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun do {
114*4882a593Smuzhiyun val = readl(base + offset);
115*4882a593Smuzhiyun if (val == ~0)
116*4882a593Smuzhiyun return 0;
117*4882a593Smuzhiyun if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
118*4882a593Smuzhiyun return offset;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun next = XHCI_EXT_CAPS_NEXT(val);
121*4882a593Smuzhiyun offset += next << 2;
122*4882a593Smuzhiyun } while (next);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return 0;
125*4882a593Smuzhiyun }
126