1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SL811HS register declarations and HCD data structures
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2004 Psion Teklogix
6*4882a593Smuzhiyun * Copyright (C) 2004 David Brownell
7*4882a593Smuzhiyun * Copyright (C) 2001 Cypress Semiconductor Inc.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun * SL811HS has transfer registers, and control registers. In host/master
12*4882a593Smuzhiyun * mode one set of registers is used; in peripheral/slave mode, another.
13*4882a593Smuzhiyun * - SL11H only has some "A" transfer registers from 0x00-0x04
14*4882a593Smuzhiyun * - SL811HS also has "B" registers from 0x08-0x0c
15*4882a593Smuzhiyun * - SL811S (or HS in slave mode) has four A+B sets, at 00, 10, 20, 30
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define SL811_EP_A(base) ((base) + 0)
19*4882a593Smuzhiyun #define SL811_EP_B(base) ((base) + 8)
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define SL811_HOST_BUF 0x00
22*4882a593Smuzhiyun #define SL811_PERIPH_EP0 0x00
23*4882a593Smuzhiyun #define SL811_PERIPH_EP1 0x10
24*4882a593Smuzhiyun #define SL811_PERIPH_EP2 0x20
25*4882a593Smuzhiyun #define SL811_PERIPH_EP3 0x30
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* TRANSFER REGISTERS: host and peripheral sides are similar
29*4882a593Smuzhiyun * except for the control models (master vs slave).
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #define SL11H_HOSTCTLREG 0
32*4882a593Smuzhiyun # define SL11H_HCTLMASK_ARM 0x01
33*4882a593Smuzhiyun # define SL11H_HCTLMASK_ENABLE 0x02
34*4882a593Smuzhiyun # define SL11H_HCTLMASK_IN 0x00
35*4882a593Smuzhiyun # define SL11H_HCTLMASK_OUT 0x04
36*4882a593Smuzhiyun # define SL11H_HCTLMASK_ISOCH 0x10
37*4882a593Smuzhiyun # define SL11H_HCTLMASK_AFTERSOF 0x20
38*4882a593Smuzhiyun # define SL11H_HCTLMASK_TOGGLE 0x40
39*4882a593Smuzhiyun # define SL11H_HCTLMASK_PREAMBLE 0x80
40*4882a593Smuzhiyun #define SL11H_BUFADDRREG 1
41*4882a593Smuzhiyun #define SL11H_BUFLNTHREG 2
42*4882a593Smuzhiyun #define SL11H_PKTSTATREG 3 /* read */
43*4882a593Smuzhiyun # define SL11H_STATMASK_ACK 0x01
44*4882a593Smuzhiyun # define SL11H_STATMASK_ERROR 0x02
45*4882a593Smuzhiyun # define SL11H_STATMASK_TMOUT 0x04
46*4882a593Smuzhiyun # define SL11H_STATMASK_SEQ 0x08
47*4882a593Smuzhiyun # define SL11H_STATMASK_SETUP 0x10
48*4882a593Smuzhiyun # define SL11H_STATMASK_OVF 0x20
49*4882a593Smuzhiyun # define SL11H_STATMASK_NAK 0x40
50*4882a593Smuzhiyun # define SL11H_STATMASK_STALL 0x80
51*4882a593Smuzhiyun #define SL11H_PIDEPREG 3 /* write */
52*4882a593Smuzhiyun # define SL_SETUP 0xd0
53*4882a593Smuzhiyun # define SL_IN 0x90
54*4882a593Smuzhiyun # define SL_OUT 0x10
55*4882a593Smuzhiyun # define SL_SOF 0x50
56*4882a593Smuzhiyun # define SL_PREAMBLE 0xc0
57*4882a593Smuzhiyun # define SL_NAK 0xa0
58*4882a593Smuzhiyun # define SL_STALL 0xe0
59*4882a593Smuzhiyun # define SL_DATA0 0x30
60*4882a593Smuzhiyun # define SL_DATA1 0xb0
61*4882a593Smuzhiyun #define SL11H_XFERCNTREG 4 /* read */
62*4882a593Smuzhiyun #define SL11H_DEVADDRREG 4 /* write */
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* CONTROL REGISTERS: host and peripheral are very different.
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun #define SL11H_CTLREG1 5
68*4882a593Smuzhiyun # define SL11H_CTL1MASK_SOF_ENA 0x01
69*4882a593Smuzhiyun # define SL11H_CTL1MASK_FORCE 0x18
70*4882a593Smuzhiyun # define SL11H_CTL1MASK_NORMAL 0x00
71*4882a593Smuzhiyun # define SL11H_CTL1MASK_SE0 0x08 /* reset */
72*4882a593Smuzhiyun # define SL11H_CTL1MASK_J 0x10
73*4882a593Smuzhiyun # define SL11H_CTL1MASK_K 0x18 /* resume */
74*4882a593Smuzhiyun # define SL11H_CTL1MASK_LSPD 0x20
75*4882a593Smuzhiyun # define SL11H_CTL1MASK_SUSPEND 0x40
76*4882a593Smuzhiyun #define SL11H_IRQ_ENABLE 6
77*4882a593Smuzhiyun # define SL11H_INTMASK_DONE_A 0x01
78*4882a593Smuzhiyun # define SL11H_INTMASK_DONE_B 0x02
79*4882a593Smuzhiyun # define SL11H_INTMASK_SOFINTR 0x10
80*4882a593Smuzhiyun # define SL11H_INTMASK_INSRMV 0x20 /* to/from SE0 */
81*4882a593Smuzhiyun # define SL11H_INTMASK_RD 0x40
82*4882a593Smuzhiyun # define SL11H_INTMASK_DP 0x80 /* only in INTSTATREG */
83*4882a593Smuzhiyun #define SL11S_ADDRESS 7
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* 0x08-0x0c are for the B buffer (not in SL11) */
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define SL11H_IRQ_STATUS 0x0D /* write to ack */
88*4882a593Smuzhiyun #define SL11H_HWREVREG 0x0E /* read */
89*4882a593Smuzhiyun # define SL11H_HWRMASK_HWREV 0xF0
90*4882a593Smuzhiyun #define SL11H_SOFLOWREG 0x0E /* write */
91*4882a593Smuzhiyun #define SL11H_SOFTMRREG 0x0F /* read */
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* a write to this register enables SL811HS features.
94*4882a593Smuzhiyun * HOST flag presumably overrides the chip input signal?
95*4882a593Smuzhiyun */
96*4882a593Smuzhiyun #define SL811HS_CTLREG2 0x0F
97*4882a593Smuzhiyun # define SL811HS_CTL2MASK_SOF_MASK 0x3F
98*4882a593Smuzhiyun # define SL811HS_CTL2MASK_DSWAP 0x40
99*4882a593Smuzhiyun # define SL811HS_CTL2MASK_HOST 0x80
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define SL811HS_CTL2_INIT (SL811HS_CTL2MASK_HOST | 0x2e)
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* DATA BUFFERS: registers from 0x10..0xff are for data buffers;
105*4882a593Smuzhiyun * that's 240 bytes, which we'll split evenly between A and B sides.
106*4882a593Smuzhiyun * Only ISO can use more than 64 bytes per packet.
107*4882a593Smuzhiyun * (The SL11S has 0x40..0xff for buffers.)
108*4882a593Smuzhiyun */
109*4882a593Smuzhiyun #define H_MAXPACKET 120 /* bytes in A or B fifos */
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun #define SL11H_DATA_START 0x10
112*4882a593Smuzhiyun #define SL811HS_PACKET_BUF(is_a) ((is_a) \
113*4882a593Smuzhiyun ? SL11H_DATA_START \
114*4882a593Smuzhiyun : (SL11H_DATA_START + H_MAXPACKET))
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */
119*4882a593Smuzhiyun #define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE)
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun struct sl811 {
122*4882a593Smuzhiyun spinlock_t lock;
123*4882a593Smuzhiyun void __iomem *addr_reg;
124*4882a593Smuzhiyun void __iomem *data_reg;
125*4882a593Smuzhiyun struct sl811_platform_data *board;
126*4882a593Smuzhiyun struct dentry *debug_file;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun unsigned long stat_insrmv;
129*4882a593Smuzhiyun unsigned long stat_wake;
130*4882a593Smuzhiyun unsigned long stat_sof;
131*4882a593Smuzhiyun unsigned long stat_a;
132*4882a593Smuzhiyun unsigned long stat_b;
133*4882a593Smuzhiyun unsigned long stat_lost;
134*4882a593Smuzhiyun unsigned long stat_overrun;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /* sw model */
137*4882a593Smuzhiyun struct timer_list timer;
138*4882a593Smuzhiyun struct sl811h_ep *next_periodic;
139*4882a593Smuzhiyun struct sl811h_ep *next_async;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun struct sl811h_ep *active_a;
142*4882a593Smuzhiyun unsigned long jiffies_a;
143*4882a593Smuzhiyun struct sl811h_ep *active_b;
144*4882a593Smuzhiyun unsigned long jiffies_b;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun u32 port1;
147*4882a593Smuzhiyun u8 ctrl1, ctrl2, irq_enable;
148*4882a593Smuzhiyun u16 frame;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* async schedule: control, bulk */
151*4882a593Smuzhiyun struct list_head async;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* periodic schedule: interrupt, iso */
154*4882a593Smuzhiyun u16 load[PERIODIC_SIZE];
155*4882a593Smuzhiyun struct sl811h_ep *periodic[PERIODIC_SIZE];
156*4882a593Smuzhiyun unsigned periodic_count;
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
hcd_to_sl811(struct usb_hcd * hcd)159*4882a593Smuzhiyun static inline struct sl811 *hcd_to_sl811(struct usb_hcd *hcd)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun return (struct sl811 *) (hcd->hcd_priv);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
sl811_to_hcd(struct sl811 * sl811)164*4882a593Smuzhiyun static inline struct usb_hcd *sl811_to_hcd(struct sl811 *sl811)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun return container_of((void *) sl811, struct usb_hcd, hcd_priv);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun struct sl811h_ep {
170*4882a593Smuzhiyun struct usb_host_endpoint *hep;
171*4882a593Smuzhiyun struct usb_device *udev;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun u8 defctrl;
174*4882a593Smuzhiyun u8 maxpacket;
175*4882a593Smuzhiyun u8 epnum;
176*4882a593Smuzhiyun u8 nextpid;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun u16 error_count;
179*4882a593Smuzhiyun u16 nak_count;
180*4882a593Smuzhiyun u16 length; /* of current packet */
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* periodic schedule */
183*4882a593Smuzhiyun u16 period;
184*4882a593Smuzhiyun u16 branch;
185*4882a593Smuzhiyun u16 load;
186*4882a593Smuzhiyun struct sl811h_ep *next;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /* async schedule */
189*4882a593Smuzhiyun struct list_head schedule;
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* These register utilities should work for the SL811S register API too
195*4882a593Smuzhiyun * NOTE: caller must hold sl811->lock.
196*4882a593Smuzhiyun */
197*4882a593Smuzhiyun
sl811_read(struct sl811 * sl811,int reg)198*4882a593Smuzhiyun static inline u8 sl811_read(struct sl811 *sl811, int reg)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun writeb(reg, sl811->addr_reg);
201*4882a593Smuzhiyun return readb(sl811->data_reg);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
sl811_write(struct sl811 * sl811,int reg,u8 val)204*4882a593Smuzhiyun static inline void sl811_write(struct sl811 *sl811, int reg, u8 val)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun writeb(reg, sl811->addr_reg);
207*4882a593Smuzhiyun writeb(val, sl811->data_reg);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun static inline void
sl811_write_buf(struct sl811 * sl811,int addr,const void * buf,size_t count)211*4882a593Smuzhiyun sl811_write_buf(struct sl811 *sl811, int addr, const void *buf, size_t count)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun const u8 *data;
214*4882a593Smuzhiyun void __iomem *data_reg;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun if (!count)
217*4882a593Smuzhiyun return;
218*4882a593Smuzhiyun writeb(addr, sl811->addr_reg);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun data = buf;
221*4882a593Smuzhiyun data_reg = sl811->data_reg;
222*4882a593Smuzhiyun do {
223*4882a593Smuzhiyun writeb(*data++, data_reg);
224*4882a593Smuzhiyun } while (--count);
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun static inline void
sl811_read_buf(struct sl811 * sl811,int addr,void * buf,size_t count)228*4882a593Smuzhiyun sl811_read_buf(struct sl811 *sl811, int addr, void *buf, size_t count)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun u8 *data;
231*4882a593Smuzhiyun void __iomem *data_reg;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun if (!count)
234*4882a593Smuzhiyun return;
235*4882a593Smuzhiyun writeb(addr, sl811->addr_reg);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun data = buf;
238*4882a593Smuzhiyun data_reg = sl811->data_reg;
239*4882a593Smuzhiyun do {
240*4882a593Smuzhiyun *data++ = readb(data_reg);
241*4882a593Smuzhiyun } while (--count);
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun #ifdef PACKET_TRACE
247*4882a593Smuzhiyun # define PACKET pr_debug("sl811: "stuff)
248*4882a593Smuzhiyun #else
249*4882a593Smuzhiyun # define PACKET(stuff...) do{}while(0)
250*4882a593Smuzhiyun #endif
251