1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * R8A66597 HCD (Host Controller Driver)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2006-2007 Renesas Solutions Corp.
6*4882a593Smuzhiyun * Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
7*4882a593Smuzhiyun * Portions Copyright (C) 2004-2005 David Brownell
8*4882a593Smuzhiyun * Portions Copyright (C) 1999 Roman Weissgaerber
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #ifndef __R8A66597_H__
14*4882a593Smuzhiyun #define __R8A66597_H__
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/clk.h>
17*4882a593Smuzhiyun #include <linux/usb/r8a66597.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define R8A66597_MAX_NUM_PIPE 10
20*4882a593Smuzhiyun #define R8A66597_BUF_BSIZE 8
21*4882a593Smuzhiyun #define R8A66597_MAX_DEVICE 10
22*4882a593Smuzhiyun #define R8A66597_MAX_ROOT_HUB 2
23*4882a593Smuzhiyun #define R8A66597_MAX_SAMPLING 5
24*4882a593Smuzhiyun #define R8A66597_RH_POLL_TIME 10
25*4882a593Smuzhiyun #define R8A66597_MAX_DMA_CHANNEL 2
26*4882a593Smuzhiyun #define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
27*4882a593Smuzhiyun #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
28*4882a593Smuzhiyun #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
29*4882a593Smuzhiyun #define make_devsel(addr) (addr << 12)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun struct r8a66597_pipe_info {
32*4882a593Smuzhiyun unsigned long timer_interval;
33*4882a593Smuzhiyun u16 pipenum;
34*4882a593Smuzhiyun u16 address; /* R8A66597 HCD usb address */
35*4882a593Smuzhiyun u16 epnum;
36*4882a593Smuzhiyun u16 maxpacket;
37*4882a593Smuzhiyun u16 type;
38*4882a593Smuzhiyun u16 bufnum;
39*4882a593Smuzhiyun u16 buf_bsize;
40*4882a593Smuzhiyun u16 interval;
41*4882a593Smuzhiyun u16 dir_in;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun struct r8a66597_pipe {
45*4882a593Smuzhiyun struct r8a66597_pipe_info info;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun unsigned long fifoaddr;
48*4882a593Smuzhiyun unsigned long fifosel;
49*4882a593Smuzhiyun unsigned long fifoctr;
50*4882a593Smuzhiyun unsigned long pipectr;
51*4882a593Smuzhiyun unsigned long pipetre;
52*4882a593Smuzhiyun unsigned long pipetrn;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun struct r8a66597_td {
56*4882a593Smuzhiyun struct r8a66597_pipe *pipe;
57*4882a593Smuzhiyun struct urb *urb;
58*4882a593Smuzhiyun struct list_head queue;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun u16 type;
61*4882a593Smuzhiyun u16 pipenum;
62*4882a593Smuzhiyun int iso_cnt;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun u16 address; /* R8A66597's USB address */
65*4882a593Smuzhiyun u16 maxpacket;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun unsigned zero_packet:1;
68*4882a593Smuzhiyun unsigned short_packet:1;
69*4882a593Smuzhiyun unsigned set_address:1;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun struct r8a66597_device {
73*4882a593Smuzhiyun u16 address; /* R8A66597's USB address */
74*4882a593Smuzhiyun u16 hub_port;
75*4882a593Smuzhiyun u16 root_port;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun unsigned short ep_in_toggle;
78*4882a593Smuzhiyun unsigned short ep_out_toggle;
79*4882a593Smuzhiyun unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
80*4882a593Smuzhiyun unsigned char dma_map;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun enum usb_device_state state;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun struct usb_device *udev;
85*4882a593Smuzhiyun int usb_address;
86*4882a593Smuzhiyun struct list_head device_list;
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun struct r8a66597_root_hub {
90*4882a593Smuzhiyun u32 port;
91*4882a593Smuzhiyun u16 old_syssts;
92*4882a593Smuzhiyun int scount;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun struct r8a66597_device *dev;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun struct r8a66597;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun struct r8a66597_timers {
100*4882a593Smuzhiyun struct timer_list td;
101*4882a593Smuzhiyun struct timer_list interval;
102*4882a593Smuzhiyun struct r8a66597 *r8a66597;
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun struct r8a66597 {
106*4882a593Smuzhiyun spinlock_t lock;
107*4882a593Smuzhiyun void __iomem *reg;
108*4882a593Smuzhiyun struct clk *clk;
109*4882a593Smuzhiyun struct r8a66597_platdata *pdata;
110*4882a593Smuzhiyun struct r8a66597_device device0;
111*4882a593Smuzhiyun struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
112*4882a593Smuzhiyun struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun struct timer_list rh_timer;
115*4882a593Smuzhiyun struct r8a66597_timers timers[R8A66597_MAX_NUM_PIPE];
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun unsigned short address_map;
118*4882a593Smuzhiyun unsigned short timeout_map;
119*4882a593Smuzhiyun unsigned short interval_map;
120*4882a593Smuzhiyun unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
121*4882a593Smuzhiyun unsigned char dma_map;
122*4882a593Smuzhiyun unsigned int max_root_hub;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun struct list_head child_device;
125*4882a593Smuzhiyun unsigned long child_connect_map[4];
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun unsigned bus_suspended:1;
128*4882a593Smuzhiyun unsigned irq_sense_low:1;
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
hcd_to_r8a66597(struct usb_hcd * hcd)131*4882a593Smuzhiyun static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun return (struct r8a66597 *)(hcd->hcd_priv);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
r8a66597_to_hcd(struct r8a66597 * r8a66597)136*4882a593Smuzhiyun static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
r8a66597_get_td(struct r8a66597 * r8a66597,u16 pipenum)141*4882a593Smuzhiyun static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
142*4882a593Smuzhiyun u16 pipenum)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
145*4882a593Smuzhiyun return NULL;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return list_entry(r8a66597->pipe_queue[pipenum].next,
148*4882a593Smuzhiyun struct r8a66597_td, queue);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
r8a66597_get_urb(struct r8a66597 * r8a66597,u16 pipenum)151*4882a593Smuzhiyun static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
152*4882a593Smuzhiyun u16 pipenum)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct r8a66597_td *td;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun td = r8a66597_get_td(r8a66597, pipenum);
157*4882a593Smuzhiyun return (td ? td->urb : NULL);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
r8a66597_read(struct r8a66597 * r8a66597,unsigned long offset)160*4882a593Smuzhiyun static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun return ioread16(r8a66597->reg + offset);
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
r8a66597_read_fifo(struct r8a66597 * r8a66597,unsigned long offset,u16 * buf,int len)165*4882a593Smuzhiyun static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
166*4882a593Smuzhiyun unsigned long offset, u16 *buf,
167*4882a593Smuzhiyun int len)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun void __iomem *fifoaddr = r8a66597->reg + offset;
170*4882a593Smuzhiyun unsigned long count;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun if (r8a66597->pdata->on_chip) {
173*4882a593Smuzhiyun count = len / 4;
174*4882a593Smuzhiyun ioread32_rep(fifoaddr, buf, count);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun if (len & 0x00000003) {
177*4882a593Smuzhiyun unsigned long tmp = ioread32(fifoaddr);
178*4882a593Smuzhiyun memcpy((unsigned char *)buf + count * 4, &tmp,
179*4882a593Smuzhiyun len & 0x03);
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun } else {
182*4882a593Smuzhiyun len = (len + 1) / 2;
183*4882a593Smuzhiyun ioread16_rep(fifoaddr, buf, len);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
r8a66597_write(struct r8a66597 * r8a66597,u16 val,unsigned long offset)187*4882a593Smuzhiyun static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
188*4882a593Smuzhiyun unsigned long offset)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun iowrite16(val, r8a66597->reg + offset);
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
r8a66597_mdfy(struct r8a66597 * r8a66597,u16 val,u16 pat,unsigned long offset)193*4882a593Smuzhiyun static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
194*4882a593Smuzhiyun u16 val, u16 pat, unsigned long offset)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun u16 tmp;
197*4882a593Smuzhiyun tmp = r8a66597_read(r8a66597, offset);
198*4882a593Smuzhiyun tmp = tmp & (~pat);
199*4882a593Smuzhiyun tmp = tmp | val;
200*4882a593Smuzhiyun r8a66597_write(r8a66597, tmp, offset);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun #define r8a66597_bclr(r8a66597, val, offset) \
204*4882a593Smuzhiyun r8a66597_mdfy(r8a66597, 0, val, offset)
205*4882a593Smuzhiyun #define r8a66597_bset(r8a66597, val, offset) \
206*4882a593Smuzhiyun r8a66597_mdfy(r8a66597, val, 0, offset)
207*4882a593Smuzhiyun
r8a66597_write_fifo(struct r8a66597 * r8a66597,struct r8a66597_pipe * pipe,u16 * buf,int len)208*4882a593Smuzhiyun static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
209*4882a593Smuzhiyun struct r8a66597_pipe *pipe, u16 *buf,
210*4882a593Smuzhiyun int len)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun void __iomem *fifoaddr = r8a66597->reg + pipe->fifoaddr;
213*4882a593Smuzhiyun unsigned long count;
214*4882a593Smuzhiyun unsigned char *pb;
215*4882a593Smuzhiyun int i;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun if (r8a66597->pdata->on_chip) {
218*4882a593Smuzhiyun count = len / 4;
219*4882a593Smuzhiyun iowrite32_rep(fifoaddr, buf, count);
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun if (len & 0x00000003) {
222*4882a593Smuzhiyun pb = (unsigned char *)buf + count * 4;
223*4882a593Smuzhiyun for (i = 0; i < (len & 0x00000003); i++) {
224*4882a593Smuzhiyun if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
225*4882a593Smuzhiyun iowrite8(pb[i], fifoaddr + i);
226*4882a593Smuzhiyun else
227*4882a593Smuzhiyun iowrite8(pb[i], fifoaddr + 3 - i);
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun } else {
231*4882a593Smuzhiyun int odd = len & 0x0001;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun len = len / 2;
234*4882a593Smuzhiyun iowrite16_rep(fifoaddr, buf, len);
235*4882a593Smuzhiyun if (unlikely(odd)) {
236*4882a593Smuzhiyun buf = &buf[len];
237*4882a593Smuzhiyun if (r8a66597->pdata->wr0_shorted_to_wr1)
238*4882a593Smuzhiyun r8a66597_bclr(r8a66597, MBW_16, pipe->fifosel);
239*4882a593Smuzhiyun iowrite8((unsigned char)*buf, fifoaddr);
240*4882a593Smuzhiyun if (r8a66597->pdata->wr0_shorted_to_wr1)
241*4882a593Smuzhiyun r8a66597_bset(r8a66597, MBW_16, pipe->fifosel);
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
get_syscfg_reg(int port)246*4882a593Smuzhiyun static inline unsigned long get_syscfg_reg(int port)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun return port == 0 ? SYSCFG0 : SYSCFG1;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
get_syssts_reg(int port)251*4882a593Smuzhiyun static inline unsigned long get_syssts_reg(int port)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun return port == 0 ? SYSSTS0 : SYSSTS1;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
get_dvstctr_reg(int port)256*4882a593Smuzhiyun static inline unsigned long get_dvstctr_reg(int port)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun return port == 0 ? DVSTCTR0 : DVSTCTR1;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
get_dmacfg_reg(int port)261*4882a593Smuzhiyun static inline unsigned long get_dmacfg_reg(int port)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun return port == 0 ? DMA0CFG : DMA1CFG;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
get_intenb_reg(int port)266*4882a593Smuzhiyun static inline unsigned long get_intenb_reg(int port)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun return port == 0 ? INTENB1 : INTENB2;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
get_intsts_reg(int port)271*4882a593Smuzhiyun static inline unsigned long get_intsts_reg(int port)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun return port == 0 ? INTSTS1 : INTSTS2;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
get_rh_usb_speed(struct r8a66597 * r8a66597,int port)276*4882a593Smuzhiyun static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun unsigned long dvstctr_reg = get_dvstctr_reg(port);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
r8a66597_port_power(struct r8a66597 * r8a66597,int port,int power)283*4882a593Smuzhiyun static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
284*4882a593Smuzhiyun int power)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun unsigned long dvstctr_reg = get_dvstctr_reg(port);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun if (r8a66597->pdata->port_power) {
289*4882a593Smuzhiyun r8a66597->pdata->port_power(port, power);
290*4882a593Smuzhiyun } else {
291*4882a593Smuzhiyun if (power)
292*4882a593Smuzhiyun r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
293*4882a593Smuzhiyun else
294*4882a593Smuzhiyun r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
get_xtal_from_pdata(struct r8a66597_platdata * pdata)298*4882a593Smuzhiyun static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun u16 clock = 0;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun switch (pdata->xtal) {
303*4882a593Smuzhiyun case R8A66597_PLATDATA_XTAL_12MHZ:
304*4882a593Smuzhiyun clock = XTAL12;
305*4882a593Smuzhiyun break;
306*4882a593Smuzhiyun case R8A66597_PLATDATA_XTAL_24MHZ:
307*4882a593Smuzhiyun clock = XTAL24;
308*4882a593Smuzhiyun break;
309*4882a593Smuzhiyun case R8A66597_PLATDATA_XTAL_48MHZ:
310*4882a593Smuzhiyun clock = XTAL48;
311*4882a593Smuzhiyun break;
312*4882a593Smuzhiyun default:
313*4882a593Smuzhiyun printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
314*4882a593Smuzhiyun break;
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun return clock;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
321*4882a593Smuzhiyun #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
322*4882a593Smuzhiyun #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
323*4882a593Smuzhiyun #define get_devadd_addr(address) (DEVADD0 + address * 2)
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun #define enable_irq_ready(r8a66597, pipenum) \
326*4882a593Smuzhiyun enable_pipe_irq(r8a66597, pipenum, BRDYENB)
327*4882a593Smuzhiyun #define disable_irq_ready(r8a66597, pipenum) \
328*4882a593Smuzhiyun disable_pipe_irq(r8a66597, pipenum, BRDYENB)
329*4882a593Smuzhiyun #define enable_irq_empty(r8a66597, pipenum) \
330*4882a593Smuzhiyun enable_pipe_irq(r8a66597, pipenum, BEMPENB)
331*4882a593Smuzhiyun #define disable_irq_empty(r8a66597, pipenum) \
332*4882a593Smuzhiyun disable_pipe_irq(r8a66597, pipenum, BEMPENB)
333*4882a593Smuzhiyun #define enable_irq_nrdy(r8a66597, pipenum) \
334*4882a593Smuzhiyun enable_pipe_irq(r8a66597, pipenum, NRDYENB)
335*4882a593Smuzhiyun #define disable_irq_nrdy(r8a66597, pipenum) \
336*4882a593Smuzhiyun disable_pipe_irq(r8a66597, pipenum, NRDYENB)
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun #endif /* __R8A66597_H__ */
339*4882a593Smuzhiyun
340