xref: /OK3568_Linux_fs/kernel/drivers/usb/host/fhci.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Freescale QUICC Engine USB Host Controller Driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) Freescale Semicondutor, Inc. 2006.
6*4882a593Smuzhiyun  *               Shlomi Gridish <gridish@freescale.com>
7*4882a593Smuzhiyun  *               Jerry Huang <Chang-Ming.Huang@freescale.com>
8*4882a593Smuzhiyun  * Copyright (c) Logic Product Development, Inc. 2007
9*4882a593Smuzhiyun  *               Peter Barada <peterb@logicpd.com>
10*4882a593Smuzhiyun  * Copyright (c) MontaVista Software, Inc. 2008.
11*4882a593Smuzhiyun  *               Anton Vorontsov <avorontsov@ru.mvista.com>
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #ifndef __FHCI_H
15*4882a593Smuzhiyun #define __FHCI_H
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/kernel.h>
18*4882a593Smuzhiyun #include <linux/types.h>
19*4882a593Smuzhiyun #include <linux/bug.h>
20*4882a593Smuzhiyun #include <linux/spinlock.h>
21*4882a593Smuzhiyun #include <linux/interrupt.h>
22*4882a593Smuzhiyun #include <linux/kfifo.h>
23*4882a593Smuzhiyun #include <linux/io.h>
24*4882a593Smuzhiyun #include <linux/usb.h>
25*4882a593Smuzhiyun #include <linux/usb/hcd.h>
26*4882a593Smuzhiyun #include <soc/fsl/qe/qe.h>
27*4882a593Smuzhiyun #include <soc/fsl/qe/immap_qe.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define USB_CLOCK	48000000
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define FHCI_PRAM_SIZE 0x100
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define MAX_EDS		32
34*4882a593Smuzhiyun #define MAX_TDS		32
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* CRC16 field size */
38*4882a593Smuzhiyun #define CRC_SIZE 2
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /* USB protocol overhead for each frame transmitted from the host */
41*4882a593Smuzhiyun #define PROTOCOL_OVERHEAD 7
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /* Packet structure, info field */
44*4882a593Smuzhiyun #define PKT_PID_DATA0		0x80000000 /* PID - Data toggle zero */
45*4882a593Smuzhiyun #define PKT_PID_DATA1		0x40000000 /* PID - Data toggle one  */
46*4882a593Smuzhiyun #define PKT_PID_SETUP		0x20000000 /* PID - Setup bit */
47*4882a593Smuzhiyun #define PKT_SETUP_STATUS	0x10000000 /* Setup status bit */
48*4882a593Smuzhiyun #define PKT_SETADDR_STATUS	0x08000000 /* Set address status bit */
49*4882a593Smuzhiyun #define PKT_SET_HOST_LAST	0x04000000 /* Last data packet */
50*4882a593Smuzhiyun #define PKT_HOST_DATA		0x02000000 /* Data packet */
51*4882a593Smuzhiyun #define PKT_FIRST_IN_FRAME	0x01000000 /* First packet in the frame */
52*4882a593Smuzhiyun #define PKT_TOKEN_FRAME		0x00800000 /* Token packet */
53*4882a593Smuzhiyun #define PKT_ZLP			0x00400000 /* Zero length packet */
54*4882a593Smuzhiyun #define PKT_IN_TOKEN_FRAME	0x00200000 /* IN token packet */
55*4882a593Smuzhiyun #define PKT_OUT_TOKEN_FRAME	0x00100000 /* OUT token packet */
56*4882a593Smuzhiyun #define PKT_SETUP_TOKEN_FRAME	0x00080000 /* SETUP token packet */
57*4882a593Smuzhiyun #define PKT_STALL_FRAME		0x00040000 /* STALL packet */
58*4882a593Smuzhiyun #define PKT_NACK_FRAME		0x00020000 /* NACK packet */
59*4882a593Smuzhiyun #define PKT_NO_PID		0x00010000 /* No PID */
60*4882a593Smuzhiyun #define PKT_NO_CRC		0x00008000 /* don't append CRC */
61*4882a593Smuzhiyun #define PKT_HOST_COMMAND	0x00004000 /* Host command packet */
62*4882a593Smuzhiyun #define PKT_DUMMY_PACKET	0x00002000 /* Dummy packet, used for mmm */
63*4882a593Smuzhiyun #define PKT_LOW_SPEED_PACKET	0x00001000 /* Low-Speed packet */
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define TRANS_OK		(0)
66*4882a593Smuzhiyun #define TRANS_INPROGRESS	(-1)
67*4882a593Smuzhiyun #define TRANS_DISCARD		(-2)
68*4882a593Smuzhiyun #define TRANS_FAIL		(-3)
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define PS_INT		0
71*4882a593Smuzhiyun #define PS_DISCONNECTED	1
72*4882a593Smuzhiyun #define PS_CONNECTED	2
73*4882a593Smuzhiyun #define PS_READY	3
74*4882a593Smuzhiyun #define PS_MISSING	4
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* Transfer Descriptor status field */
77*4882a593Smuzhiyun #define USB_TD_OK		0x00000000 /* TD transmited or received ok */
78*4882a593Smuzhiyun #define USB_TD_INPROGRESS	0x80000000 /* TD is being transmitted */
79*4882a593Smuzhiyun #define USB_TD_RX_ER_NONOCT	0x40000000 /* Tx Non Octet Aligned Packet */
80*4882a593Smuzhiyun #define USB_TD_RX_ER_BITSTUFF	0x20000000 /* Frame Aborted-Received pkt */
81*4882a593Smuzhiyun #define USB_TD_RX_ER_CRC	0x10000000 /* CRC error */
82*4882a593Smuzhiyun #define USB_TD_RX_ER_OVERUN	0x08000000 /* Over - run occurred */
83*4882a593Smuzhiyun #define USB_TD_RX_ER_PID	0x04000000 /* wrong PID received */
84*4882a593Smuzhiyun #define USB_TD_RX_DATA_UNDERUN	0x02000000 /* shorter than expected */
85*4882a593Smuzhiyun #define USB_TD_RX_DATA_OVERUN	0x01000000 /* longer than expected */
86*4882a593Smuzhiyun #define USB_TD_TX_ER_NAK	0x00800000 /* NAK handshake */
87*4882a593Smuzhiyun #define USB_TD_TX_ER_STALL	0x00400000 /* STALL handshake */
88*4882a593Smuzhiyun #define USB_TD_TX_ER_TIMEOUT	0x00200000 /* transmit time out */
89*4882a593Smuzhiyun #define USB_TD_TX_ER_UNDERUN	0x00100000 /* transmit underrun */
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #define USB_TD_ERROR (USB_TD_RX_ER_NONOCT | USB_TD_RX_ER_BITSTUFF | \
92*4882a593Smuzhiyun 		USB_TD_RX_ER_CRC | USB_TD_RX_ER_OVERUN | USB_TD_RX_ER_PID | \
93*4882a593Smuzhiyun 		USB_TD_RX_DATA_UNDERUN | USB_TD_RX_DATA_OVERUN | \
94*4882a593Smuzhiyun 		USB_TD_TX_ER_NAK | USB_TD_TX_ER_STALL | \
95*4882a593Smuzhiyun 		USB_TD_TX_ER_TIMEOUT | USB_TD_TX_ER_UNDERUN)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* Transfer Descriptor toggle field */
98*4882a593Smuzhiyun #define USB_TD_TOGGLE_DATA0	0
99*4882a593Smuzhiyun #define USB_TD_TOGGLE_DATA1	1
100*4882a593Smuzhiyun #define USB_TD_TOGGLE_CARRY	2
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun /* #define MULTI_DATA_BUS */
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun /* Bus mode register RBMR/TBMR */
105*4882a593Smuzhiyun #define BUS_MODE_GBL	0x20	/* Global snooping */
106*4882a593Smuzhiyun #define BUS_MODE_BO	0x18	/* Byte ordering */
107*4882a593Smuzhiyun #define BUS_MODE_BO_BE	0x10	/* Byte ordering - Big-endian */
108*4882a593Smuzhiyun #define BUS_MODE_DTB	0x02	/* Data bus */
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun /* FHCI QE USB Register Description */
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /* USB Mode Register bit define */
113*4882a593Smuzhiyun #define USB_MODE_EN		0x01
114*4882a593Smuzhiyun #define USB_MODE_HOST		0x02
115*4882a593Smuzhiyun #define USB_MODE_TEST		0x04
116*4882a593Smuzhiyun #define USB_MODE_SFTE		0x08
117*4882a593Smuzhiyun #define USB_MODE_RESUME		0x40
118*4882a593Smuzhiyun #define USB_MODE_LSS		0x80
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun /* USB Slave Address Register Mask */
121*4882a593Smuzhiyun #define USB_SLVADDR_MASK	0x7F
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /* USB Endpoint register define */
124*4882a593Smuzhiyun #define USB_EPNUM_MASK		0xF000
125*4882a593Smuzhiyun #define USB_EPNUM_SHIFT		12
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #define USB_TRANS_MODE_SHIFT	8
128*4882a593Smuzhiyun #define USB_TRANS_CTR		0x0000
129*4882a593Smuzhiyun #define USB_TRANS_INT		0x0100
130*4882a593Smuzhiyun #define USB_TRANS_BULK		0x0200
131*4882a593Smuzhiyun #define USB_TRANS_ISO		0x0300
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #define USB_EP_MF		0x0020
134*4882a593Smuzhiyun #define USB_EP_RTE		0x0010
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define USB_THS_SHIFT		2
137*4882a593Smuzhiyun #define USB_THS_MASK		0x000c
138*4882a593Smuzhiyun #define USB_THS_NORMAL		0x0
139*4882a593Smuzhiyun #define USB_THS_IGNORE_IN	0x0004
140*4882a593Smuzhiyun #define USB_THS_NACK		0x0008
141*4882a593Smuzhiyun #define USB_THS_STALL		0x000c
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #define USB_RHS_SHIFT   	0
144*4882a593Smuzhiyun #define USB_RHS_MASK		0x0003
145*4882a593Smuzhiyun #define USB_RHS_NORMAL  	0x0
146*4882a593Smuzhiyun #define USB_RHS_IGNORE_OUT	0x0001
147*4882a593Smuzhiyun #define USB_RHS_NACK		0x0002
148*4882a593Smuzhiyun #define USB_RHS_STALL		0x0003
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun #define USB_RTHS_MASK		0x000f
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /* USB Command Register define */
153*4882a593Smuzhiyun #define USB_CMD_STR_FIFO	0x80
154*4882a593Smuzhiyun #define USB_CMD_FLUSH_FIFO	0x40
155*4882a593Smuzhiyun #define USB_CMD_ISFT		0x20
156*4882a593Smuzhiyun #define USB_CMD_DSFT		0x10
157*4882a593Smuzhiyun #define USB_CMD_EP_MASK		0x03
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun /* USB Event and Mask Register define */
160*4882a593Smuzhiyun #define USB_E_MSF_MASK		0x0800
161*4882a593Smuzhiyun #define USB_E_SFT_MASK		0x0400
162*4882a593Smuzhiyun #define USB_E_RESET_MASK	0x0200
163*4882a593Smuzhiyun #define USB_E_IDLE_MASK		0x0100
164*4882a593Smuzhiyun #define USB_E_TXE4_MASK		0x0080
165*4882a593Smuzhiyun #define USB_E_TXE3_MASK		0x0040
166*4882a593Smuzhiyun #define USB_E_TXE2_MASK		0x0020
167*4882a593Smuzhiyun #define USB_E_TXE1_MASK		0x0010
168*4882a593Smuzhiyun #define USB_E_SOF_MASK		0x0008
169*4882a593Smuzhiyun #define USB_E_BSY_MASK		0x0004
170*4882a593Smuzhiyun #define USB_E_TXB_MASK		0x0002
171*4882a593Smuzhiyun #define USB_E_RXB_MASK		0x0001
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /* Freescale USB HOST */
174*4882a593Smuzhiyun struct fhci_pram {
175*4882a593Smuzhiyun 	__be16 ep_ptr[4];	/* Endpoint porter reg */
176*4882a593Smuzhiyun 	__be32 rx_state;	/* Rx internal state */
177*4882a593Smuzhiyun 	__be32 rx_ptr;		/* Rx internal data pointer */
178*4882a593Smuzhiyun 	__be16 frame_num;	/* Frame number */
179*4882a593Smuzhiyun 	__be16 rx_cnt;		/* Rx byte count */
180*4882a593Smuzhiyun 	__be32 rx_temp;		/* Rx temp */
181*4882a593Smuzhiyun 	__be32 rx_data_temp;	/* Rx data temp */
182*4882a593Smuzhiyun 	__be16 rx_u_ptr;	/* Rx microcode return address temp */
183*4882a593Smuzhiyun 	u8 reserved1[2];	/* reserved area */
184*4882a593Smuzhiyun 	__be32 sof_tbl;		/* SOF lookup table pointer */
185*4882a593Smuzhiyun 	u8 sof_u_crc_temp;	/* SOF micorcode CRC5 temp reg */
186*4882a593Smuzhiyun 	u8 reserved2[0xdb];
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /* Freescale USB Endpoint*/
190*4882a593Smuzhiyun struct fhci_ep_pram {
191*4882a593Smuzhiyun 	__be16 rx_base;		/* Rx BD base address */
192*4882a593Smuzhiyun 	__be16 tx_base;		/* Tx BD base address */
193*4882a593Smuzhiyun 	u8 rx_func_code;	/* Rx function code */
194*4882a593Smuzhiyun 	u8 tx_func_code;	/* Tx function code */
195*4882a593Smuzhiyun 	__be16 rx_buff_len;	/* Rx buffer length */
196*4882a593Smuzhiyun 	__be16 rx_bd_ptr;	/* Rx BD pointer */
197*4882a593Smuzhiyun 	__be16 tx_bd_ptr;	/* Tx BD pointer */
198*4882a593Smuzhiyun 	__be32 tx_state;	/* Tx internal state */
199*4882a593Smuzhiyun 	__be32 tx_ptr;		/* Tx internal data pointer */
200*4882a593Smuzhiyun 	__be16 tx_crc;		/* temp transmit CRC */
201*4882a593Smuzhiyun 	__be16 tx_cnt;		/* Tx byte count */
202*4882a593Smuzhiyun 	__be32 tx_temp;		/* Tx temp */
203*4882a593Smuzhiyun 	__be16 tx_u_ptr;	/* Tx microcode return address temp */
204*4882a593Smuzhiyun 	__be16 reserved;
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun struct fhci_controller_list {
208*4882a593Smuzhiyun 	struct list_head ctrl_list;	/* control endpoints */
209*4882a593Smuzhiyun 	struct list_head bulk_list;	/* bulk endpoints */
210*4882a593Smuzhiyun 	struct list_head iso_list;	/* isochronous endpoints */
211*4882a593Smuzhiyun 	struct list_head intr_list;	/* interruput endpoints */
212*4882a593Smuzhiyun 	struct list_head done_list;	/* done transfers */
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun struct virtual_root_hub {
216*4882a593Smuzhiyun 	int dev_num;	/* USB address of the root hub */
217*4882a593Smuzhiyun 	u32 feature;	/* indicates what feature has been set */
218*4882a593Smuzhiyun 	struct usb_hub_status hub;
219*4882a593Smuzhiyun 	struct usb_port_status port;
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun enum fhci_gpios {
223*4882a593Smuzhiyun 	GPIO_USBOE = 0,
224*4882a593Smuzhiyun 	GPIO_USBTP,
225*4882a593Smuzhiyun 	GPIO_USBTN,
226*4882a593Smuzhiyun 	GPIO_USBRP,
227*4882a593Smuzhiyun 	GPIO_USBRN,
228*4882a593Smuzhiyun 	/* these are optional */
229*4882a593Smuzhiyun 	GPIO_SPEED,
230*4882a593Smuzhiyun 	GPIO_POWER,
231*4882a593Smuzhiyun 	NUM_GPIOS,
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun enum fhci_pins {
235*4882a593Smuzhiyun 	PIN_USBOE = 0,
236*4882a593Smuzhiyun 	PIN_USBTP,
237*4882a593Smuzhiyun 	PIN_USBTN,
238*4882a593Smuzhiyun 	NUM_PINS,
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun struct fhci_hcd {
242*4882a593Smuzhiyun 	enum qe_clock fullspeed_clk;
243*4882a593Smuzhiyun 	enum qe_clock lowspeed_clk;
244*4882a593Smuzhiyun 	struct qe_pin *pins[NUM_PINS];
245*4882a593Smuzhiyun 	int gpios[NUM_GPIOS];
246*4882a593Smuzhiyun 	bool alow_gpios[NUM_GPIOS];
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	struct qe_usb_ctlr __iomem *regs; /* I/O memory used to communicate */
249*4882a593Smuzhiyun 	struct fhci_pram __iomem *pram;	/* Parameter RAM */
250*4882a593Smuzhiyun 	struct gtm_timer *timer;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	spinlock_t lock;
253*4882a593Smuzhiyun 	struct fhci_usb *usb_lld; /* Low-level driver */
254*4882a593Smuzhiyun 	struct virtual_root_hub *vroot_hub; /* the virtual root hub */
255*4882a593Smuzhiyun 	int active_urbs;
256*4882a593Smuzhiyun 	struct fhci_controller_list *hc_list;
257*4882a593Smuzhiyun 	struct tasklet_struct *process_done_task; /* tasklet for done list */
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	struct list_head empty_eds;
260*4882a593Smuzhiyun 	struct list_head empty_tds;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun #ifdef CONFIG_FHCI_DEBUG
263*4882a593Smuzhiyun 	int usb_irq_stat[13];
264*4882a593Smuzhiyun 	struct dentry *dfs_root;
265*4882a593Smuzhiyun #endif
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun #define USB_FRAME_USAGE 90
269*4882a593Smuzhiyun #define FRAME_TIME_USAGE (USB_FRAME_USAGE*10)	/* frame time usage */
270*4882a593Smuzhiyun #define SW_FIX_TIME_BETWEEN_TRANSACTION 150	/* SW */
271*4882a593Smuzhiyun #define MAX_BYTES_PER_FRAME (USB_FRAME_USAGE*15)
272*4882a593Smuzhiyun #define MAX_PERIODIC_FRAME_USAGE 90
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun /* transaction type */
275*4882a593Smuzhiyun enum fhci_ta_type {
276*4882a593Smuzhiyun 	FHCI_TA_IN = 0,	/* input transaction */
277*4882a593Smuzhiyun 	FHCI_TA_OUT,	/* output transaction */
278*4882a593Smuzhiyun 	FHCI_TA_SETUP,	/* setup transaction */
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun /* transfer mode */
282*4882a593Smuzhiyun enum fhci_tf_mode {
283*4882a593Smuzhiyun 	FHCI_TF_CTRL = 0,
284*4882a593Smuzhiyun 	FHCI_TF_ISO,
285*4882a593Smuzhiyun 	FHCI_TF_BULK,
286*4882a593Smuzhiyun 	FHCI_TF_INTR,
287*4882a593Smuzhiyun };
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun enum fhci_speed {
290*4882a593Smuzhiyun 	FHCI_FULL_SPEED,
291*4882a593Smuzhiyun 	FHCI_LOW_SPEED,
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun /* endpoint state */
295*4882a593Smuzhiyun enum fhci_ed_state {
296*4882a593Smuzhiyun 	FHCI_ED_NEW = 0, /* pipe is new */
297*4882a593Smuzhiyun 	FHCI_ED_OPER,    /* pipe is operating */
298*4882a593Smuzhiyun 	FHCI_ED_URB_DEL, /* pipe is in hold because urb is being deleted */
299*4882a593Smuzhiyun 	FHCI_ED_SKIP,    /* skip this pipe */
300*4882a593Smuzhiyun 	FHCI_ED_HALTED,  /* pipe is halted */
301*4882a593Smuzhiyun };
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun enum fhci_port_status {
304*4882a593Smuzhiyun 	FHCI_PORT_POWER_OFF = 0,
305*4882a593Smuzhiyun 	FHCI_PORT_DISABLED,
306*4882a593Smuzhiyun 	FHCI_PORT_DISCONNECTING,
307*4882a593Smuzhiyun 	FHCI_PORT_WAITING,	/* waiting for connection */
308*4882a593Smuzhiyun 	FHCI_PORT_FULL,		/* full speed connected */
309*4882a593Smuzhiyun 	FHCI_PORT_LOW,		/* low speed connected */
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun enum fhci_mem_alloc {
313*4882a593Smuzhiyun 	MEM_CACHABLE_SYS = 0x00000001,	/* primary DDR,cachable */
314*4882a593Smuzhiyun 	MEM_NOCACHE_SYS = 0x00000004,	/* primary DDR,non-cachable */
315*4882a593Smuzhiyun 	MEM_SECONDARY = 0x00000002,	/* either secondary DDR or SDRAM */
316*4882a593Smuzhiyun 	MEM_PRAM = 0x00000008,		/* multi-user RAM identifier */
317*4882a593Smuzhiyun };
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun /* USB default parameters*/
320*4882a593Smuzhiyun #define DEFAULT_RING_LEN	8
321*4882a593Smuzhiyun #define DEFAULT_DATA_MEM	MEM_CACHABLE_SYS
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun struct ed {
324*4882a593Smuzhiyun 	u8 dev_addr;		/* device address */
325*4882a593Smuzhiyun 	u8 ep_addr;		/* endpoint address */
326*4882a593Smuzhiyun 	enum fhci_tf_mode mode;	/* USB transfer mode */
327*4882a593Smuzhiyun 	enum fhci_speed speed;
328*4882a593Smuzhiyun 	unsigned int max_pkt_size;
329*4882a593Smuzhiyun 	enum fhci_ed_state state;
330*4882a593Smuzhiyun 	struct list_head td_list; /* a list of all queued TD to this pipe */
331*4882a593Smuzhiyun 	struct list_head node;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	/* read only parameters, should be cleared upon initialization */
334*4882a593Smuzhiyun 	u8 toggle_carry;	/* toggle carry from the last TD submitted */
335*4882a593Smuzhiyun 	u16 next_iso;		/* time stamp of next queued ISO transfer */
336*4882a593Smuzhiyun 	struct td *td_head;	/* a pointer to the current TD handled */
337*4882a593Smuzhiyun };
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun struct td {
340*4882a593Smuzhiyun 	void *data;		 /* a pointer to the data buffer */
341*4882a593Smuzhiyun 	unsigned int len;	 /* length of the data to be submitted */
342*4882a593Smuzhiyun 	unsigned int actual_len; /* actual bytes transferred on this td */
343*4882a593Smuzhiyun 	enum fhci_ta_type type;	 /* transaction type */
344*4882a593Smuzhiyun 	u8 toggle;		 /* toggle for next trans. within this TD */
345*4882a593Smuzhiyun 	u16 iso_index;		 /* ISO transaction index */
346*4882a593Smuzhiyun 	u16 start_frame;	 /* start frame time stamp */
347*4882a593Smuzhiyun 	u16 interval;		 /* interval between trans. (for ISO/Intr) */
348*4882a593Smuzhiyun 	u32 status;		 /* status of the TD */
349*4882a593Smuzhiyun 	struct ed *ed;		 /* a handle to the corresponding ED */
350*4882a593Smuzhiyun 	struct urb *urb;	 /* a handle to the corresponding URB */
351*4882a593Smuzhiyun 	bool ioc;		 /* Inform On Completion */
352*4882a593Smuzhiyun 	struct list_head node;
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	/* read only parameters should be cleared upon initialization */
355*4882a593Smuzhiyun 	struct packet *pkt;
356*4882a593Smuzhiyun 	int nak_cnt;
357*4882a593Smuzhiyun 	int error_cnt;
358*4882a593Smuzhiyun 	struct list_head frame_lh;
359*4882a593Smuzhiyun };
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun struct packet {
362*4882a593Smuzhiyun 	u8 *data;	/* packet data */
363*4882a593Smuzhiyun 	u32 len;	/* packet length */
364*4882a593Smuzhiyun 	u32 status;	/* status of the packet - equivalent to the status
365*4882a593Smuzhiyun 			 * field for the corresponding structure td */
366*4882a593Smuzhiyun 	u32 info;	/* packet information */
367*4882a593Smuzhiyun 	void __iomem *priv_data; /* private data of the driver (TDs or BDs) */
368*4882a593Smuzhiyun };
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun /* struct for each URB */
371*4882a593Smuzhiyun #define URB_INPROGRESS	0
372*4882a593Smuzhiyun #define URB_DEL		1
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun /* URB states (state field) */
375*4882a593Smuzhiyun #define US_BULK		0
376*4882a593Smuzhiyun #define US_BULK0	1
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun /* three setup states */
379*4882a593Smuzhiyun #define US_CTRL_SETUP	2
380*4882a593Smuzhiyun #define US_CTRL_DATA	1
381*4882a593Smuzhiyun #define US_CTRL_ACK	0
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun #define EP_ZERO	0
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun struct urb_priv {
386*4882a593Smuzhiyun 	int num_of_tds;
387*4882a593Smuzhiyun 	int tds_cnt;
388*4882a593Smuzhiyun 	int state;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	struct td **tds;
391*4882a593Smuzhiyun 	struct ed *ed;
392*4882a593Smuzhiyun 	struct timer_list time_out;
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun struct endpoint {
396*4882a593Smuzhiyun 	/* Pointer to ep parameter RAM */
397*4882a593Smuzhiyun 	struct fhci_ep_pram __iomem *ep_pram_ptr;
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	/* Host transactions */
400*4882a593Smuzhiyun 	struct usb_td __iomem *td_base; /* first TD in the ring */
401*4882a593Smuzhiyun 	struct usb_td __iomem *conf_td; /* next TD for confirm after transac */
402*4882a593Smuzhiyun 	struct usb_td __iomem *empty_td;/* next TD for new transaction req. */
403*4882a593Smuzhiyun 	struct kfifo empty_frame_Q;  /* Empty frames list to use */
404*4882a593Smuzhiyun 	struct kfifo conf_frame_Q;   /* frames passed to TDs,waiting for tx */
405*4882a593Smuzhiyun 	struct kfifo dummy_packets_Q;/* dummy packets for the CRC overun */
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	bool already_pushed_dummy_bd;
408*4882a593Smuzhiyun };
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun /* struct for each 1mSec frame time */
411*4882a593Smuzhiyun #define FRAME_IS_TRANSMITTED		0x00
412*4882a593Smuzhiyun #define FRAME_TIMER_END_TRANSMISSION	0x01
413*4882a593Smuzhiyun #define FRAME_DATA_END_TRANSMISSION	0x02
414*4882a593Smuzhiyun #define FRAME_END_TRANSMISSION		0x03
415*4882a593Smuzhiyun #define FRAME_IS_PREPARED		0x04
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun struct fhci_time_frame {
418*4882a593Smuzhiyun 	u16 frame_num;	 /* frame number */
419*4882a593Smuzhiyun 	u16 total_bytes; /* total bytes submitted within this frame */
420*4882a593Smuzhiyun 	u8 frame_status; /* flag that indicates to stop fill this frame */
421*4882a593Smuzhiyun 	struct list_head tds_list; /* all tds of this frame */
422*4882a593Smuzhiyun };
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun /* internal driver structure*/
425*4882a593Smuzhiyun struct fhci_usb {
426*4882a593Smuzhiyun 	u16 saved_msk;		 /* saving of the USB mask register */
427*4882a593Smuzhiyun 	struct endpoint *ep0;	 /* pointer for endpoint0 structure */
428*4882a593Smuzhiyun 	int intr_nesting_cnt;	 /* interrupt nesting counter */
429*4882a593Smuzhiyun 	u16 max_frame_usage;	 /* max frame time usage,in micro-sec */
430*4882a593Smuzhiyun 	u16 max_bytes_per_frame; /* max byte can be tx in one time frame */
431*4882a593Smuzhiyun 	u32 sw_transaction_time; /* sw complete trans time,in micro-sec */
432*4882a593Smuzhiyun 	struct fhci_time_frame *actual_frame;
433*4882a593Smuzhiyun 	struct fhci_controller_list *hc_list;	/* main structure for hc */
434*4882a593Smuzhiyun 	struct virtual_root_hub *vroot_hub;
435*4882a593Smuzhiyun 	enum fhci_port_status port_status;	/* v_rh port status */
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	u32 (*transfer_confirm)(struct fhci_hcd *fhci);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	struct fhci_hcd *fhci;
440*4882a593Smuzhiyun };
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun /*
443*4882a593Smuzhiyun  * Various helpers and prototypes below.
444*4882a593Smuzhiyun  */
445*4882a593Smuzhiyun 
get_frame_num(struct fhci_hcd * fhci)446*4882a593Smuzhiyun static inline u16 get_frame_num(struct fhci_hcd *fhci)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	return in_be16(&fhci->pram->frame_num) & 0x07ff;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun #define fhci_dbg(fhci, fmt, args...) \
452*4882a593Smuzhiyun 		dev_dbg(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
453*4882a593Smuzhiyun #define fhci_vdbg(fhci, fmt, args...) \
454*4882a593Smuzhiyun 		dev_vdbg(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
455*4882a593Smuzhiyun #define fhci_err(fhci, fmt, args...) \
456*4882a593Smuzhiyun 		dev_err(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
457*4882a593Smuzhiyun #define fhci_info(fhci, fmt, args...) \
458*4882a593Smuzhiyun 		dev_info(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
459*4882a593Smuzhiyun #define fhci_warn(fhci, fmt, args...) \
460*4882a593Smuzhiyun 		dev_warn(fhci_to_hcd(fhci)->self.controller, fmt, ##args)
461*4882a593Smuzhiyun 
hcd_to_fhci(struct usb_hcd * hcd)462*4882a593Smuzhiyun static inline struct fhci_hcd *hcd_to_fhci(struct usb_hcd *hcd)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun 	return (struct fhci_hcd *)hcd->hcd_priv;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun 
fhci_to_hcd(struct fhci_hcd * fhci)467*4882a593Smuzhiyun static inline struct usb_hcd *fhci_to_hcd(struct fhci_hcd *fhci)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun 	return container_of((void *)fhci, struct usb_hcd, hcd_priv);
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun /* fifo of pointers */
cq_new(struct kfifo * fifo,int size)473*4882a593Smuzhiyun static inline int cq_new(struct kfifo *fifo, int size)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun 	return kfifo_alloc(fifo, size * sizeof(void *), GFP_KERNEL);
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun 
cq_delete(struct kfifo * kfifo)478*4882a593Smuzhiyun static inline void cq_delete(struct kfifo *kfifo)
479*4882a593Smuzhiyun {
480*4882a593Smuzhiyun 	kfifo_free(kfifo);
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun 
cq_howmany(struct kfifo * kfifo)483*4882a593Smuzhiyun static inline unsigned int cq_howmany(struct kfifo *kfifo)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun 	return kfifo_len(kfifo) / sizeof(void *);
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun 
cq_put(struct kfifo * kfifo,void * p)488*4882a593Smuzhiyun static inline int cq_put(struct kfifo *kfifo, void *p)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun 	return kfifo_in(kfifo, (void *)&p, sizeof(p));
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun 
cq_get(struct kfifo * kfifo)493*4882a593Smuzhiyun static inline void *cq_get(struct kfifo *kfifo)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun 	unsigned int sz;
496*4882a593Smuzhiyun 	void *p;
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	sz = kfifo_out(kfifo, (void *)&p, sizeof(p));
499*4882a593Smuzhiyun 	if (sz != sizeof(p))
500*4882a593Smuzhiyun 		return NULL;
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	return p;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun /* fhci-hcd.c */
506*4882a593Smuzhiyun void fhci_start_sof_timer(struct fhci_hcd *fhci);
507*4882a593Smuzhiyun void fhci_stop_sof_timer(struct fhci_hcd *fhci);
508*4882a593Smuzhiyun u16 fhci_get_sof_timer_count(struct fhci_usb *usb);
509*4882a593Smuzhiyun void fhci_usb_enable_interrupt(struct fhci_usb *usb);
510*4882a593Smuzhiyun void fhci_usb_disable_interrupt(struct fhci_usb *usb);
511*4882a593Smuzhiyun int fhci_ioports_check_bus_state(struct fhci_hcd *fhci);
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun /* fhci-mem.c */
514*4882a593Smuzhiyun void fhci_recycle_empty_td(struct fhci_hcd *fhci, struct td *td);
515*4882a593Smuzhiyun void fhci_recycle_empty_ed(struct fhci_hcd *fhci, struct ed *ed);
516*4882a593Smuzhiyun struct ed *fhci_get_empty_ed(struct fhci_hcd *fhci);
517*4882a593Smuzhiyun struct td *fhci_td_fill(struct fhci_hcd *fhci, struct urb *urb,
518*4882a593Smuzhiyun 			struct urb_priv *urb_priv, struct ed *ed, u16 index,
519*4882a593Smuzhiyun 			enum fhci_ta_type type, int toggle, u8 *data, u32 len,
520*4882a593Smuzhiyun 			u16 interval, u16 start_frame, bool ioc);
521*4882a593Smuzhiyun void fhci_add_tds_to_ed(struct ed *ed, struct td **td_list, int number);
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun /* fhci-hub.c */
524*4882a593Smuzhiyun void fhci_config_transceiver(struct fhci_hcd *fhci,
525*4882a593Smuzhiyun 			enum fhci_port_status status);
526*4882a593Smuzhiyun void fhci_port_disable(struct fhci_hcd *fhci);
527*4882a593Smuzhiyun void fhci_port_enable(void *lld);
528*4882a593Smuzhiyun void fhci_io_port_generate_reset(struct fhci_hcd *fhci);
529*4882a593Smuzhiyun void fhci_port_reset(void *lld);
530*4882a593Smuzhiyun int fhci_hub_status_data(struct usb_hcd *hcd, char *buf);
531*4882a593Smuzhiyun int fhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
532*4882a593Smuzhiyun 		     u16 wIndex, char *buf, u16 wLength);
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun /* fhci-tds.c */
535*4882a593Smuzhiyun void fhci_flush_bds(struct fhci_usb *usb);
536*4882a593Smuzhiyun void fhci_flush_actual_frame(struct fhci_usb *usb);
537*4882a593Smuzhiyun u32 fhci_host_transaction(struct fhci_usb *usb, struct packet *pkt,
538*4882a593Smuzhiyun 			  enum fhci_ta_type trans_type, u8 dest_addr,
539*4882a593Smuzhiyun 			  u8 dest_ep, enum fhci_tf_mode trans_mode,
540*4882a593Smuzhiyun 			  enum fhci_speed dest_speed, u8 data_toggle);
541*4882a593Smuzhiyun void fhci_host_transmit_actual_frame(struct fhci_usb *usb);
542*4882a593Smuzhiyun void fhci_tx_conf_interrupt(struct fhci_usb *usb);
543*4882a593Smuzhiyun void fhci_push_dummy_bd(struct endpoint *ep);
544*4882a593Smuzhiyun u32 fhci_create_ep(struct fhci_usb *usb, enum fhci_mem_alloc data_mem,
545*4882a593Smuzhiyun 		   u32 ring_len);
546*4882a593Smuzhiyun void fhci_init_ep_registers(struct fhci_usb *usb,
547*4882a593Smuzhiyun 			    struct endpoint *ep,
548*4882a593Smuzhiyun 			    enum fhci_mem_alloc data_mem);
549*4882a593Smuzhiyun void fhci_ep0_free(struct fhci_usb *usb);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun /* fhci-sched.c */
552*4882a593Smuzhiyun extern struct tasklet_struct fhci_tasklet;
553*4882a593Smuzhiyun void fhci_transaction_confirm(struct fhci_usb *usb, struct packet *pkt);
554*4882a593Smuzhiyun void fhci_flush_all_transmissions(struct fhci_usb *usb);
555*4882a593Smuzhiyun void fhci_schedule_transactions(struct fhci_usb *usb);
556*4882a593Smuzhiyun void fhci_device_connected_interrupt(struct fhci_hcd *fhci);
557*4882a593Smuzhiyun void fhci_device_disconnected_interrupt(struct fhci_hcd *fhci);
558*4882a593Smuzhiyun void fhci_queue_urb(struct fhci_hcd *fhci, struct urb *urb);
559*4882a593Smuzhiyun u32 fhci_transfer_confirm_callback(struct fhci_hcd *fhci);
560*4882a593Smuzhiyun irqreturn_t fhci_irq(struct usb_hcd *hcd);
561*4882a593Smuzhiyun irqreturn_t fhci_frame_limit_timer_irq(int irq, void *_hcd);
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun /* fhci-q.h */
564*4882a593Smuzhiyun void fhci_urb_complete_free(struct fhci_hcd *fhci, struct urb *urb);
565*4882a593Smuzhiyun struct td *fhci_remove_td_from_ed(struct ed *ed);
566*4882a593Smuzhiyun struct td *fhci_remove_td_from_frame(struct fhci_time_frame *frame);
567*4882a593Smuzhiyun void fhci_move_td_from_ed_to_done_list(struct fhci_usb *usb, struct ed *ed);
568*4882a593Smuzhiyun struct td *fhci_peek_td_from_frame(struct fhci_time_frame *frame);
569*4882a593Smuzhiyun void fhci_add_td_to_frame(struct fhci_time_frame *frame, struct td *td);
570*4882a593Smuzhiyun struct td *fhci_remove_td_from_done_list(struct fhci_controller_list *p_list);
571*4882a593Smuzhiyun void fhci_done_td(struct urb *urb, struct td *td);
572*4882a593Smuzhiyun void fhci_del_ed_list(struct fhci_hcd *fhci, struct ed *ed);
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun #ifdef CONFIG_FHCI_DEBUG
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun void fhci_dbg_isr(struct fhci_hcd *fhci, int usb_er);
577*4882a593Smuzhiyun void fhci_dfs_destroy(struct fhci_hcd *fhci);
578*4882a593Smuzhiyun void fhci_dfs_create(struct fhci_hcd *fhci);
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun #else
581*4882a593Smuzhiyun 
fhci_dbg_isr(struct fhci_hcd * fhci,int usb_er)582*4882a593Smuzhiyun static inline void fhci_dbg_isr(struct fhci_hcd *fhci, int usb_er) {}
fhci_dfs_destroy(struct fhci_hcd * fhci)583*4882a593Smuzhiyun static inline void fhci_dfs_destroy(struct fhci_hcd *fhci) {}
fhci_dfs_create(struct fhci_hcd * fhci)584*4882a593Smuzhiyun static inline void fhci_dfs_create(struct fhci_hcd *fhci) {}
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun #endif /* CONFIG_FHCI_DEBUG */
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun #endif /* __FHCI_H */
589