1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2001 by David Brownell
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun /* this file is part of ehci-hcd.c */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /*
11*4882a593Smuzhiyun * There's basically three types of memory:
12*4882a593Smuzhiyun * - data used only by the HCD ... kmalloc is fine
13*4882a593Smuzhiyun * - async and periodic schedules, shared by HC and HCD ... these
14*4882a593Smuzhiyun * need to use dma_pool or dma_alloc_coherent
15*4882a593Smuzhiyun * - driver buffers, read/written by HC ... single shot DMA mapped
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
18*4882a593Smuzhiyun * No memory seen by this driver is pageable.
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* Allocate the key transfer structures from the previously allocated pool */
24*4882a593Smuzhiyun
ehci_qtd_init(struct ehci_hcd * ehci,struct ehci_qtd * qtd,dma_addr_t dma)25*4882a593Smuzhiyun static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
26*4882a593Smuzhiyun dma_addr_t dma)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun memset (qtd, 0, sizeof *qtd);
29*4882a593Smuzhiyun qtd->qtd_dma = dma;
30*4882a593Smuzhiyun qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
31*4882a593Smuzhiyun qtd->hw_next = EHCI_LIST_END(ehci);
32*4882a593Smuzhiyun qtd->hw_alt_next = EHCI_LIST_END(ehci);
33*4882a593Smuzhiyun INIT_LIST_HEAD (&qtd->qtd_list);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
ehci_qtd_alloc(struct ehci_hcd * ehci,gfp_t flags)36*4882a593Smuzhiyun static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct ehci_qtd *qtd;
39*4882a593Smuzhiyun dma_addr_t dma;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
42*4882a593Smuzhiyun if (qtd != NULL) {
43*4882a593Smuzhiyun ehci_qtd_init(ehci, qtd, dma);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun return qtd;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
ehci_qtd_free(struct ehci_hcd * ehci,struct ehci_qtd * qtd)48*4882a593Smuzhiyun static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun
qh_destroy(struct ehci_hcd * ehci,struct ehci_qh * qh)54*4882a593Smuzhiyun static void qh_destroy(struct ehci_hcd *ehci, struct ehci_qh *qh)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun /* clean qtds first, and know this is not linked */
57*4882a593Smuzhiyun if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
58*4882a593Smuzhiyun ehci_dbg (ehci, "unused qh not empty!\n");
59*4882a593Smuzhiyun BUG ();
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun if (qh->dummy)
62*4882a593Smuzhiyun ehci_qtd_free (ehci, qh->dummy);
63*4882a593Smuzhiyun dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
64*4882a593Smuzhiyun kfree(qh);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
ehci_qh_alloc(struct ehci_hcd * ehci,gfp_t flags)67*4882a593Smuzhiyun static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun struct ehci_qh *qh;
70*4882a593Smuzhiyun dma_addr_t dma;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun qh = kzalloc(sizeof *qh, GFP_ATOMIC);
73*4882a593Smuzhiyun if (!qh)
74*4882a593Smuzhiyun goto done;
75*4882a593Smuzhiyun qh->hw = (struct ehci_qh_hw *)
76*4882a593Smuzhiyun dma_pool_alloc(ehci->qh_pool, flags, &dma);
77*4882a593Smuzhiyun if (!qh->hw)
78*4882a593Smuzhiyun goto fail;
79*4882a593Smuzhiyun memset(qh->hw, 0, sizeof *qh->hw);
80*4882a593Smuzhiyun qh->qh_dma = dma;
81*4882a593Smuzhiyun // INIT_LIST_HEAD (&qh->qh_list);
82*4882a593Smuzhiyun INIT_LIST_HEAD (&qh->qtd_list);
83*4882a593Smuzhiyun INIT_LIST_HEAD(&qh->unlink_node);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* dummy td enables safe urb queuing */
86*4882a593Smuzhiyun qh->dummy = ehci_qtd_alloc (ehci, flags);
87*4882a593Smuzhiyun if (qh->dummy == NULL) {
88*4882a593Smuzhiyun ehci_dbg (ehci, "no dummy td\n");
89*4882a593Smuzhiyun goto fail1;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun done:
92*4882a593Smuzhiyun return qh;
93*4882a593Smuzhiyun fail1:
94*4882a593Smuzhiyun dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
95*4882a593Smuzhiyun fail:
96*4882a593Smuzhiyun kfree(qh);
97*4882a593Smuzhiyun return NULL;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /* The queue heads and transfer descriptors are managed from pools tied
103*4882a593Smuzhiyun * to each of the "per device" structures.
104*4882a593Smuzhiyun * This is the initialisation and cleanup code.
105*4882a593Smuzhiyun */
106*4882a593Smuzhiyun
ehci_mem_cleanup(struct ehci_hcd * ehci)107*4882a593Smuzhiyun static void ehci_mem_cleanup (struct ehci_hcd *ehci)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun if (ehci->async)
110*4882a593Smuzhiyun qh_destroy(ehci, ehci->async);
111*4882a593Smuzhiyun ehci->async = NULL;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (ehci->dummy)
114*4882a593Smuzhiyun qh_destroy(ehci, ehci->dummy);
115*4882a593Smuzhiyun ehci->dummy = NULL;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* DMA consistent memory and pools */
118*4882a593Smuzhiyun dma_pool_destroy(ehci->qtd_pool);
119*4882a593Smuzhiyun ehci->qtd_pool = NULL;
120*4882a593Smuzhiyun dma_pool_destroy(ehci->qh_pool);
121*4882a593Smuzhiyun ehci->qh_pool = NULL;
122*4882a593Smuzhiyun dma_pool_destroy(ehci->itd_pool);
123*4882a593Smuzhiyun ehci->itd_pool = NULL;
124*4882a593Smuzhiyun dma_pool_destroy(ehci->sitd_pool);
125*4882a593Smuzhiyun ehci->sitd_pool = NULL;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun if (ehci->periodic)
128*4882a593Smuzhiyun dma_free_coherent(ehci_to_hcd(ehci)->self.sysdev,
129*4882a593Smuzhiyun ehci->periodic_size * sizeof (u32),
130*4882a593Smuzhiyun ehci->periodic, ehci->periodic_dma);
131*4882a593Smuzhiyun ehci->periodic = NULL;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* shadow periodic table */
134*4882a593Smuzhiyun kfree(ehci->pshadow);
135*4882a593Smuzhiyun ehci->pshadow = NULL;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* remember to add cleanup code (above) if you add anything here */
ehci_mem_init(struct ehci_hcd * ehci,gfp_t flags)139*4882a593Smuzhiyun static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun int i;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* QTDs for control/bulk/intr transfers */
144*4882a593Smuzhiyun ehci->qtd_pool = dma_pool_create ("ehci_qtd",
145*4882a593Smuzhiyun ehci_to_hcd(ehci)->self.sysdev,
146*4882a593Smuzhiyun sizeof (struct ehci_qtd),
147*4882a593Smuzhiyun 32 /* byte alignment (for hw parts) */,
148*4882a593Smuzhiyun 4096 /* can't cross 4K */);
149*4882a593Smuzhiyun if (!ehci->qtd_pool) {
150*4882a593Smuzhiyun goto fail;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* QHs for control/bulk/intr transfers */
154*4882a593Smuzhiyun ehci->qh_pool = dma_pool_create ("ehci_qh",
155*4882a593Smuzhiyun ehci_to_hcd(ehci)->self.sysdev,
156*4882a593Smuzhiyun sizeof(struct ehci_qh_hw),
157*4882a593Smuzhiyun 32 /* byte alignment (for hw parts) */,
158*4882a593Smuzhiyun 4096 /* can't cross 4K */);
159*4882a593Smuzhiyun if (!ehci->qh_pool) {
160*4882a593Smuzhiyun goto fail;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun ehci->async = ehci_qh_alloc (ehci, flags);
163*4882a593Smuzhiyun if (!ehci->async) {
164*4882a593Smuzhiyun goto fail;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /* ITD for high speed ISO transfers */
168*4882a593Smuzhiyun ehci->itd_pool = dma_pool_create ("ehci_itd",
169*4882a593Smuzhiyun ehci_to_hcd(ehci)->self.sysdev,
170*4882a593Smuzhiyun sizeof (struct ehci_itd),
171*4882a593Smuzhiyun 32 /* byte alignment (for hw parts) */,
172*4882a593Smuzhiyun 4096 /* can't cross 4K */);
173*4882a593Smuzhiyun if (!ehci->itd_pool) {
174*4882a593Smuzhiyun goto fail;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* SITD for full/low speed split ISO transfers */
178*4882a593Smuzhiyun ehci->sitd_pool = dma_pool_create ("ehci_sitd",
179*4882a593Smuzhiyun ehci_to_hcd(ehci)->self.sysdev,
180*4882a593Smuzhiyun sizeof (struct ehci_sitd),
181*4882a593Smuzhiyun 32 /* byte alignment (for hw parts) */,
182*4882a593Smuzhiyun 4096 /* can't cross 4K */);
183*4882a593Smuzhiyun if (!ehci->sitd_pool) {
184*4882a593Smuzhiyun goto fail;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /* Hardware periodic table */
188*4882a593Smuzhiyun ehci->periodic = (__le32 *)
189*4882a593Smuzhiyun dma_alloc_coherent(ehci_to_hcd(ehci)->self.sysdev,
190*4882a593Smuzhiyun ehci->periodic_size * sizeof(__le32),
191*4882a593Smuzhiyun &ehci->periodic_dma, flags);
192*4882a593Smuzhiyun if (ehci->periodic == NULL) {
193*4882a593Smuzhiyun goto fail;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun if (ehci->use_dummy_qh) {
197*4882a593Smuzhiyun struct ehci_qh_hw *hw;
198*4882a593Smuzhiyun ehci->dummy = ehci_qh_alloc(ehci, flags);
199*4882a593Smuzhiyun if (!ehci->dummy)
200*4882a593Smuzhiyun goto fail;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun hw = ehci->dummy->hw;
203*4882a593Smuzhiyun hw->hw_next = EHCI_LIST_END(ehci);
204*4882a593Smuzhiyun hw->hw_qtd_next = EHCI_LIST_END(ehci);
205*4882a593Smuzhiyun hw->hw_alt_next = EHCI_LIST_END(ehci);
206*4882a593Smuzhiyun ehci->dummy->hw = hw;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun for (i = 0; i < ehci->periodic_size; i++)
209*4882a593Smuzhiyun ehci->periodic[i] = cpu_to_hc32(ehci,
210*4882a593Smuzhiyun ehci->dummy->qh_dma);
211*4882a593Smuzhiyun } else {
212*4882a593Smuzhiyun for (i = 0; i < ehci->periodic_size; i++)
213*4882a593Smuzhiyun ehci->periodic[i] = EHCI_LIST_END(ehci);
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun /* software shadow of hardware table */
217*4882a593Smuzhiyun ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
218*4882a593Smuzhiyun if (ehci->pshadow != NULL)
219*4882a593Smuzhiyun return 0;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun fail:
222*4882a593Smuzhiyun ehci_dbg (ehci, "couldn't init memory\n");
223*4882a593Smuzhiyun ehci_mem_cleanup (ehci);
224*4882a593Smuzhiyun return -ENOMEM;
225*4882a593Smuzhiyun }
226