1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * Copyright (c) 2005 MontaVista Software 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _EHCI_FSL_H 6*4882a593Smuzhiyun #define _EHCI_FSL_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* offsets for the non-ehci registers in the FSL SOC USB controller */ 9*4882a593Smuzhiyun #define FSL_SOC_USB_SBUSCFG 0x90 10*4882a593Smuzhiyun #define SBUSCFG_INCR8 0x02 /* INCR8, specified */ 11*4882a593Smuzhiyun #define FSL_SOC_USB_ULPIVP 0x170 12*4882a593Smuzhiyun #define FSL_SOC_USB_PORTSC1 0x184 13*4882a593Smuzhiyun #define PORT_PTS_MSK (3<<30) 14*4882a593Smuzhiyun #define PORT_PTS_UTMI (0<<30) 15*4882a593Smuzhiyun #define PORT_PTS_ULPI (2<<30) 16*4882a593Smuzhiyun #define PORT_PTS_SERIAL (3<<30) 17*4882a593Smuzhiyun #define PORT_PTS_PTW (1<<28) 18*4882a593Smuzhiyun #define FSL_SOC_USB_PORTSC2 0x188 19*4882a593Smuzhiyun #define FSL_SOC_USB_USBMODE 0x1a8 20*4882a593Smuzhiyun #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ 21*4882a593Smuzhiyun #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ 22*4882a593Smuzhiyun #define USBMODE_ES (1 << 2) /* (Big) Endian Select */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define FSL_SOC_USB_USBGENCTRL 0x200 25*4882a593Smuzhiyun #define USBGENCTRL_PPP (1 << 3) 26*4882a593Smuzhiyun #define USBGENCTRL_PFP (1 << 2) 27*4882a593Smuzhiyun #define FSL_SOC_USB_ISIPHYCTRL 0x204 28*4882a593Smuzhiyun #define ISIPHYCTRL_PXE (1) 29*4882a593Smuzhiyun #define ISIPHYCTRL_PHYE (1 << 4) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ 32*4882a593Smuzhiyun #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ 33*4882a593Smuzhiyun #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ 34*4882a593Smuzhiyun #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ 35*4882a593Smuzhiyun #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ 36*4882a593Smuzhiyun #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ 37*4882a593Smuzhiyun #define CTRL_UTMI_PHY_EN (1<<9) 38*4882a593Smuzhiyun #define CTRL_PHY_CLK_VALID (1 << 17) 39*4882a593Smuzhiyun #define SNOOP_SIZE_2GB 0x1e 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* control Register Bit Masks */ 42*4882a593Smuzhiyun #define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ 43*4882a593Smuzhiyun #define ULPI_INT_EN (1<<0) 44*4882a593Smuzhiyun #define WU_INT_EN (1<<1) 45*4882a593Smuzhiyun #define USB_CTRL_USB_EN (1<<2) 46*4882a593Smuzhiyun #define LINE_STATE_FILTER__EN (1<<3) 47*4882a593Smuzhiyun #define KEEP_OTG_ON (1<<4) 48*4882a593Smuzhiyun #define OTG_PORT (1<<5) 49*4882a593Smuzhiyun #define PLL_RESET (1<<8) 50*4882a593Smuzhiyun #define UTMI_PHY_EN (1<<9) 51*4882a593Smuzhiyun #define ULPI_PHY_CLK_SEL (1<<10) 52*4882a593Smuzhiyun #define PHY_CLK_VALID (1<<17) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Retry count for checking UTMI PHY CLK validity */ 55*4882a593Smuzhiyun #define UTMI_PHY_CLK_VALID_CHK_RETRY 5 56*4882a593Smuzhiyun #endif /* _EHCI_FSL_H */ 57