xref: /OK3568_Linux_fs/kernel/drivers/usb/gadget/udc/net2280.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * NetChip 2280 high/full speed USB device controller.
4*4882a593Smuzhiyun  * Unlike many such controllers, this one talks PCI.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun /*
8*4882a593Smuzhiyun  * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
9*4882a593Smuzhiyun  * Copyright (C) 2003 David Brownell
10*4882a593Smuzhiyun  * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/usb/net2280.h>
14*4882a593Smuzhiyun #include <linux/usb/usb338x.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #ifdef	__KERNEL__
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /* indexed registers [11.10] are accessed indirectly
21*4882a593Smuzhiyun  * caller must own the device lock.
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun 
get_idx_reg(struct net2280_regs __iomem * regs,u32 index)24*4882a593Smuzhiyun static inline u32 get_idx_reg(struct net2280_regs __iomem *regs, u32 index)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun 	writel(index, &regs->idxaddr);
27*4882a593Smuzhiyun 	/* NOTE:  synchs device/cpu memory views */
28*4882a593Smuzhiyun 	return readl(&regs->idxdata);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun static inline void
set_idx_reg(struct net2280_regs __iomem * regs,u32 index,u32 value)32*4882a593Smuzhiyun set_idx_reg(struct net2280_regs __iomem *regs, u32 index, u32 value)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	writel(index, &regs->idxaddr);
35*4882a593Smuzhiyun 	writel(value, &regs->idxdata);
36*4882a593Smuzhiyun 	/* posted, may not be visible yet */
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #endif	/* __KERNEL__ */
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define PCI_VENDOR_ID_PLX_LEGACY 0x17cc
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define PLX_LEGACY		BIT(0)
44*4882a593Smuzhiyun #define PLX_2280		BIT(1)
45*4882a593Smuzhiyun #define PLX_SUPERSPEED		BIT(2)
46*4882a593Smuzhiyun #define PLX_PCIE		BIT(3)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define REG_DIAG		0x0
49*4882a593Smuzhiyun #define     RETRY_COUNTER                                       16
50*4882a593Smuzhiyun #define     FORCE_PCI_SERR                                      11
51*4882a593Smuzhiyun #define     FORCE_PCI_INTERRUPT                                 10
52*4882a593Smuzhiyun #define     FORCE_USB_INTERRUPT                                 9
53*4882a593Smuzhiyun #define     FORCE_CPU_INTERRUPT                                 8
54*4882a593Smuzhiyun #define     ILLEGAL_BYTE_ENABLES                                5
55*4882a593Smuzhiyun #define     FAST_TIMES                                          4
56*4882a593Smuzhiyun #define     FORCE_RECEIVE_ERROR                                 2
57*4882a593Smuzhiyun #define     FORCE_TRANSMIT_CRC_ERROR                            0
58*4882a593Smuzhiyun #define REG_FRAME		0x02	/* from last sof */
59*4882a593Smuzhiyun #define REG_CHIPREV		0x03	/* in bcd */
60*4882a593Smuzhiyun #define	REG_HS_NAK_RATE		0x0a	/* NAK per N uframes */
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define	CHIPREV_1	0x0100
63*4882a593Smuzhiyun #define	CHIPREV_1A	0x0110
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* DEFECT 7374 */
66*4882a593Smuzhiyun #define DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS         200
67*4882a593Smuzhiyun #define DEFECT_7374_PROCESSOR_WAIT_TIME             10
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /* ep0 max packet size */
70*4882a593Smuzhiyun #define EP0_SS_MAX_PACKET_SIZE  0x200
71*4882a593Smuzhiyun #define EP0_HS_MAX_PACKET_SIZE  0x40
72*4882a593Smuzhiyun #ifdef	__KERNEL__
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* [8.3] for scatter/gather i/o
77*4882a593Smuzhiyun  * use struct net2280_dma_regs bitfields
78*4882a593Smuzhiyun  */
79*4882a593Smuzhiyun struct net2280_dma {
80*4882a593Smuzhiyun 	__le32		dmacount;
81*4882a593Smuzhiyun 	__le32		dmaaddr;		/* the buffer */
82*4882a593Smuzhiyun 	__le32		dmadesc;		/* next dma descriptor */
83*4882a593Smuzhiyun 	__le32		_reserved;
84*4882a593Smuzhiyun } __aligned(16);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /* DRIVER DATA STRUCTURES and UTILITIES */
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun struct net2280_ep {
91*4882a593Smuzhiyun 	struct usb_ep				ep;
92*4882a593Smuzhiyun 	struct net2280_ep_regs __iomem *cfg;
93*4882a593Smuzhiyun 	struct net2280_ep_regs			__iomem *regs;
94*4882a593Smuzhiyun 	struct net2280_dma_regs			__iomem *dma;
95*4882a593Smuzhiyun 	struct net2280_dma			*dummy;
96*4882a593Smuzhiyun 	dma_addr_t				td_dma;	/* of dummy */
97*4882a593Smuzhiyun 	struct net2280				*dev;
98*4882a593Smuzhiyun 	unsigned long				irqs;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	/* analogous to a host-side qh */
101*4882a593Smuzhiyun 	struct list_head			queue;
102*4882a593Smuzhiyun 	const struct usb_endpoint_descriptor	*desc;
103*4882a593Smuzhiyun 	unsigned				num : 8,
104*4882a593Smuzhiyun 						fifo_size : 12,
105*4882a593Smuzhiyun 						in_fifo_validate : 1,
106*4882a593Smuzhiyun 						out_overflow : 1,
107*4882a593Smuzhiyun 						stopped : 1,
108*4882a593Smuzhiyun 						wedged : 1,
109*4882a593Smuzhiyun 						is_in : 1,
110*4882a593Smuzhiyun 						is_iso : 1,
111*4882a593Smuzhiyun 						responded : 1;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
allow_status(struct net2280_ep * ep)114*4882a593Smuzhiyun static inline void allow_status(struct net2280_ep *ep)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	/* ep0 only */
117*4882a593Smuzhiyun 	writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
118*4882a593Smuzhiyun 		BIT(CLEAR_NAK_OUT_PACKETS) |
119*4882a593Smuzhiyun 		BIT(CLEAR_NAK_OUT_PACKETS_MODE),
120*4882a593Smuzhiyun 		&ep->regs->ep_rsp);
121*4882a593Smuzhiyun 	ep->stopped = 1;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
allow_status_338x(struct net2280_ep * ep)124*4882a593Smuzhiyun static inline void allow_status_338x(struct net2280_ep *ep)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun 	/*
127*4882a593Smuzhiyun 	 * Control Status Phase Handshake was set by the chip when the setup
128*4882a593Smuzhiyun 	 * packet arrived. While set, the chip automatically NAKs the host's
129*4882a593Smuzhiyun 	 * Status Phase tokens.
130*4882a593Smuzhiyun 	 */
131*4882a593Smuzhiyun 	writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	ep->stopped = 1;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* TD 9.9 Halt Endpoint test.  TD 9.22 set feature test. */
136*4882a593Smuzhiyun 	ep->responded = 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun struct net2280_request {
140*4882a593Smuzhiyun 	struct usb_request		req;
141*4882a593Smuzhiyun 	struct net2280_dma		*td;
142*4882a593Smuzhiyun 	dma_addr_t			td_dma;
143*4882a593Smuzhiyun 	struct list_head		queue;
144*4882a593Smuzhiyun 	unsigned			mapped : 1,
145*4882a593Smuzhiyun 					valid : 1;
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun struct net2280 {
149*4882a593Smuzhiyun 	/* each pci device provides one gadget, several endpoints */
150*4882a593Smuzhiyun 	struct usb_gadget		gadget;
151*4882a593Smuzhiyun 	spinlock_t			lock;
152*4882a593Smuzhiyun 	struct net2280_ep		ep[9];
153*4882a593Smuzhiyun 	struct usb_gadget_driver	*driver;
154*4882a593Smuzhiyun 	unsigned			enabled : 1,
155*4882a593Smuzhiyun 					protocol_stall : 1,
156*4882a593Smuzhiyun 					softconnect : 1,
157*4882a593Smuzhiyun 					got_irq : 1,
158*4882a593Smuzhiyun 					region:1,
159*4882a593Smuzhiyun 					added:1,
160*4882a593Smuzhiyun 					u1_enable:1,
161*4882a593Smuzhiyun 					u2_enable:1,
162*4882a593Smuzhiyun 					ltm_enable:1,
163*4882a593Smuzhiyun 					wakeup_enable:1,
164*4882a593Smuzhiyun 					addressed_state:1,
165*4882a593Smuzhiyun 					bug7734_patched:1;
166*4882a593Smuzhiyun 	u16				chiprev;
167*4882a593Smuzhiyun 	int enhanced_mode;
168*4882a593Smuzhiyun 	int n_ep;
169*4882a593Smuzhiyun 	kernel_ulong_t			quirks;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	/* pci state used to access those endpoints */
173*4882a593Smuzhiyun 	struct pci_dev			*pdev;
174*4882a593Smuzhiyun 	struct net2280_regs		__iomem *regs;
175*4882a593Smuzhiyun 	struct net2280_usb_regs		__iomem *usb;
176*4882a593Smuzhiyun 	struct usb338x_usb_ext_regs	__iomem *usb_ext;
177*4882a593Smuzhiyun 	struct net2280_pci_regs		__iomem *pci;
178*4882a593Smuzhiyun 	struct net2280_dma_regs		__iomem *dma;
179*4882a593Smuzhiyun 	struct net2280_dep_regs		__iomem *dep;
180*4882a593Smuzhiyun 	struct net2280_ep_regs		__iomem *epregs;
181*4882a593Smuzhiyun 	struct usb338x_ll_regs		__iomem *llregs;
182*4882a593Smuzhiyun 	struct usb338x_pl_regs		__iomem *plregs;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	struct dma_pool			*requests;
185*4882a593Smuzhiyun 	/* statistics...*/
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun 
set_halt(struct net2280_ep * ep)188*4882a593Smuzhiyun static inline void set_halt(struct net2280_ep *ep)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	/* ep0 and bulk/intr endpoints */
191*4882a593Smuzhiyun 	writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
192*4882a593Smuzhiyun 		/* set NAK_OUT for erratum 0114 */
193*4882a593Smuzhiyun 		((ep->dev->chiprev == CHIPREV_1) << SET_NAK_OUT_PACKETS) |
194*4882a593Smuzhiyun 		BIT(SET_ENDPOINT_HALT),
195*4882a593Smuzhiyun 		&ep->regs->ep_rsp);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
clear_halt(struct net2280_ep * ep)198*4882a593Smuzhiyun static inline void clear_halt(struct net2280_ep *ep)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	/* ep0 and bulk/intr endpoints */
201*4882a593Smuzhiyun 	writel(BIT(CLEAR_ENDPOINT_HALT) |
202*4882a593Smuzhiyun 		BIT(CLEAR_ENDPOINT_TOGGLE) |
203*4882a593Smuzhiyun 		    /*
204*4882a593Smuzhiyun 		     * unless the gadget driver left a short packet in the
205*4882a593Smuzhiyun 		     * fifo, this reverses the erratum 0114 workaround.
206*4882a593Smuzhiyun 		     */
207*4882a593Smuzhiyun 		((ep->dev->chiprev == CHIPREV_1) << CLEAR_NAK_OUT_PACKETS),
208*4882a593Smuzhiyun 		&ep->regs->ep_rsp);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /*
212*4882a593Smuzhiyun  * FSM value for Defect 7374 (U1U2 Test) is managed in
213*4882a593Smuzhiyun  * chip's SCRATCH register:
214*4882a593Smuzhiyun  */
215*4882a593Smuzhiyun #define DEFECT7374_FSM_FIELD    28
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun /* Waiting for Control Read:
218*4882a593Smuzhiyun  *  - A transition to this state indicates a fresh USB connection,
219*4882a593Smuzhiyun  *    before the first Setup Packet. The connection speed is not
220*4882a593Smuzhiyun  *    known. Firmware is waiting for the first Control Read.
221*4882a593Smuzhiyun  *  - Starting state: This state can be thought of as the FSM's typical
222*4882a593Smuzhiyun  *    starting state.
223*4882a593Smuzhiyun  *  - Tip: Upon the first SS Control Read the FSM never
224*4882a593Smuzhiyun  *    returns to this state.
225*4882a593Smuzhiyun  */
226*4882a593Smuzhiyun #define DEFECT7374_FSM_WAITING_FOR_CONTROL_READ BIT(DEFECT7374_FSM_FIELD)
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun /* Non-SS Control Read:
229*4882a593Smuzhiyun  *  - A transition to this state indicates detection of the first HS
230*4882a593Smuzhiyun  *    or FS Control Read.
231*4882a593Smuzhiyun  *  - Tip: Upon the first SS Control Read the FSM never
232*4882a593Smuzhiyun  *    returns to this state.
233*4882a593Smuzhiyun  */
234*4882a593Smuzhiyun #define	DEFECT7374_FSM_NON_SS_CONTROL_READ (2 << DEFECT7374_FSM_FIELD)
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun /* SS Control Read:
237*4882a593Smuzhiyun  *  - A transition to this state indicates detection of the
238*4882a593Smuzhiyun  *    first SS Control Read.
239*4882a593Smuzhiyun  *  - This state indicates workaround completion. Workarounds no longer
240*4882a593Smuzhiyun  *    need to be applied (as long as the chip remains powered up).
241*4882a593Smuzhiyun  *  - Tip: Once in this state the FSM state does not change (until
242*4882a593Smuzhiyun  *    the chip's power is lost and restored).
243*4882a593Smuzhiyun  *  - This can be thought of as the final state of the FSM;
244*4882a593Smuzhiyun  *    the FSM 'locks-up' in this state until the chip loses power.
245*4882a593Smuzhiyun  */
246*4882a593Smuzhiyun #define DEFECT7374_FSM_SS_CONTROL_READ (3 << DEFECT7374_FSM_FIELD)
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun #ifdef USE_RDK_LEDS
249*4882a593Smuzhiyun 
net2280_led_init(struct net2280 * dev)250*4882a593Smuzhiyun static inline void net2280_led_init(struct net2280 *dev)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun 	/* LED3 (green) is on during USB activity. note erratum 0113. */
253*4882a593Smuzhiyun 	writel(BIT(GPIO3_LED_SELECT) |
254*4882a593Smuzhiyun 		BIT(GPIO3_OUTPUT_ENABLE) |
255*4882a593Smuzhiyun 		BIT(GPIO2_OUTPUT_ENABLE) |
256*4882a593Smuzhiyun 		BIT(GPIO1_OUTPUT_ENABLE) |
257*4882a593Smuzhiyun 		BIT(GPIO0_OUTPUT_ENABLE),
258*4882a593Smuzhiyun 		&dev->regs->gpioctl);
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun /* indicate speed with bi-color LED 0/1 */
262*4882a593Smuzhiyun static inline
net2280_led_speed(struct net2280 * dev,enum usb_device_speed speed)263*4882a593Smuzhiyun void net2280_led_speed(struct net2280 *dev, enum usb_device_speed speed)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun 	u32	val = readl(&dev->regs->gpioctl);
266*4882a593Smuzhiyun 	switch (speed) {
267*4882a593Smuzhiyun 	case USB_SPEED_SUPER:		/* green + red */
268*4882a593Smuzhiyun 		val |= BIT(GPIO0_DATA) | BIT(GPIO1_DATA);
269*4882a593Smuzhiyun 		break;
270*4882a593Smuzhiyun 	case USB_SPEED_HIGH:		/* green */
271*4882a593Smuzhiyun 		val &= ~BIT(GPIO0_DATA);
272*4882a593Smuzhiyun 		val |= BIT(GPIO1_DATA);
273*4882a593Smuzhiyun 		break;
274*4882a593Smuzhiyun 	case USB_SPEED_FULL:		/* red */
275*4882a593Smuzhiyun 		val &= ~BIT(GPIO1_DATA);
276*4882a593Smuzhiyun 		val |= BIT(GPIO0_DATA);
277*4882a593Smuzhiyun 		break;
278*4882a593Smuzhiyun 	default:			/* (off/black) */
279*4882a593Smuzhiyun 		val &= ~(BIT(GPIO1_DATA) | BIT(GPIO0_DATA));
280*4882a593Smuzhiyun 		break;
281*4882a593Smuzhiyun 	}
282*4882a593Smuzhiyun 	writel(val, &dev->regs->gpioctl);
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun /* indicate power with LED 2 */
net2280_led_active(struct net2280 * dev,int is_active)286*4882a593Smuzhiyun static inline void net2280_led_active(struct net2280 *dev, int is_active)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun 	u32	val = readl(&dev->regs->gpioctl);
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	/* FIXME this LED never seems to turn on.*/
291*4882a593Smuzhiyun 	if (is_active)
292*4882a593Smuzhiyun 		val |= GPIO2_DATA;
293*4882a593Smuzhiyun 	else
294*4882a593Smuzhiyun 		val &= ~GPIO2_DATA;
295*4882a593Smuzhiyun 	writel(val, &dev->regs->gpioctl);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun 
net2280_led_shutdown(struct net2280 * dev)298*4882a593Smuzhiyun static inline void net2280_led_shutdown(struct net2280 *dev)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun 	/* turn off all four GPIO*_DATA bits */
301*4882a593Smuzhiyun 	writel(readl(&dev->regs->gpioctl) & ~0x0f,
302*4882a593Smuzhiyun 			&dev->regs->gpioctl);
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun #else
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun #define net2280_led_init(dev)		do { } while (0)
308*4882a593Smuzhiyun #define net2280_led_speed(dev, speed)	do { } while (0)
309*4882a593Smuzhiyun #define net2280_led_shutdown(dev)	do { } while (0)
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun #endif
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun #define ep_dbg(ndev, fmt, args...) \
316*4882a593Smuzhiyun 	dev_dbg((&((ndev)->pdev->dev)), fmt, ##args)
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun #define ep_vdbg(ndev, fmt, args...) \
319*4882a593Smuzhiyun 	dev_vdbg((&((ndev)->pdev->dev)), fmt, ##args)
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun #define ep_info(ndev, fmt, args...) \
322*4882a593Smuzhiyun 	dev_info((&((ndev)->pdev->dev)), fmt, ##args)
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun #define ep_warn(ndev, fmt, args...) \
325*4882a593Smuzhiyun 	dev_warn((&((ndev)->pdev->dev)), fmt, ##args)
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun #define ep_err(ndev, fmt, args...) \
328*4882a593Smuzhiyun 	dev_err((&((ndev)->pdev->dev)), fmt, ##args)
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
331*4882a593Smuzhiyun 
set_fifo_bytecount(struct net2280_ep * ep,unsigned count)332*4882a593Smuzhiyun static inline void set_fifo_bytecount(struct net2280_ep *ep, unsigned count)
333*4882a593Smuzhiyun {
334*4882a593Smuzhiyun 	if (ep->dev->pdev->vendor == 0x17cc)
335*4882a593Smuzhiyun 		writeb(count, 2 + (u8 __iomem *) &ep->regs->ep_cfg);
336*4882a593Smuzhiyun 	else{
337*4882a593Smuzhiyun 		u32 tmp = readl(&ep->cfg->ep_cfg) &
338*4882a593Smuzhiyun 					(~(0x07 << EP_FIFO_BYTE_COUNT));
339*4882a593Smuzhiyun 		writel(tmp | (count << EP_FIFO_BYTE_COUNT), &ep->cfg->ep_cfg);
340*4882a593Smuzhiyun 	}
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun 
start_out_naking(struct net2280_ep * ep)343*4882a593Smuzhiyun static inline void start_out_naking(struct net2280_ep *ep)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun 	/* NOTE:  hardware races lurk here, and PING protocol issues */
346*4882a593Smuzhiyun 	writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
347*4882a593Smuzhiyun 	/* synch with device */
348*4882a593Smuzhiyun 	readl(&ep->regs->ep_rsp);
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun 
stop_out_naking(struct net2280_ep * ep)351*4882a593Smuzhiyun static inline void stop_out_naking(struct net2280_ep *ep)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	u32	tmp;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	tmp = readl(&ep->regs->ep_stat);
356*4882a593Smuzhiyun 	if ((tmp & BIT(NAK_OUT_PACKETS)) != 0)
357*4882a593Smuzhiyun 		writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 
set_max_speed(struct net2280_ep * ep,u32 max)361*4882a593Smuzhiyun static inline void set_max_speed(struct net2280_ep *ep, u32 max)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun 	u32 reg;
364*4882a593Smuzhiyun 	static const u32 ep_enhanced[9] = { 0x10, 0x60, 0x30, 0x80,
365*4882a593Smuzhiyun 					  0x50, 0x20, 0x70, 0x40, 0x90 };
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	if (ep->dev->enhanced_mode) {
368*4882a593Smuzhiyun 		reg = ep_enhanced[ep->num];
369*4882a593Smuzhiyun 		switch (ep->dev->gadget.speed) {
370*4882a593Smuzhiyun 		case USB_SPEED_SUPER:
371*4882a593Smuzhiyun 			reg += 2;
372*4882a593Smuzhiyun 			break;
373*4882a593Smuzhiyun 		case USB_SPEED_FULL:
374*4882a593Smuzhiyun 			reg += 1;
375*4882a593Smuzhiyun 			break;
376*4882a593Smuzhiyun 		case USB_SPEED_HIGH:
377*4882a593Smuzhiyun 		default:
378*4882a593Smuzhiyun 			break;
379*4882a593Smuzhiyun 		}
380*4882a593Smuzhiyun 	} else {
381*4882a593Smuzhiyun 		reg = (ep->num + 1) * 0x10;
382*4882a593Smuzhiyun 		if (ep->dev->gadget.speed != USB_SPEED_HIGH)
383*4882a593Smuzhiyun 			reg += 1;
384*4882a593Smuzhiyun 	}
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	set_idx_reg(ep->dev->regs, reg, max);
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun #endif	/* __KERNEL__ */
390