1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the PLX NET2280 USB device controller.
4*4882a593Smuzhiyun * Specs and errata are available from <http://www.plxtech.com>.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * PLX Technology Inc. (formerly NetChip Technology) supported the
7*4882a593Smuzhiyun * development of this driver.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * CODE STATUS HIGHLIGHTS
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * This driver should work well with most "gadget" drivers, including
13*4882a593Smuzhiyun * the Mass Storage, Serial, and Ethernet/RNDIS gadget drivers
14*4882a593Smuzhiyun * as well as Gadget Zero and Gadgetfs.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * DMA is enabled by default.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * MSI is enabled by default. The legacy IRQ is used if MSI couldn't
19*4882a593Smuzhiyun * be enabled.
20*4882a593Smuzhiyun *
21*4882a593Smuzhiyun * Note that almost all the errata workarounds here are only needed for
22*4882a593Smuzhiyun * rev1 chips. Rev1a silicon (0110) fixes almost all of them.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * Copyright (C) 2003 David Brownell
27*4882a593Smuzhiyun * Copyright (C) 2003-2005 PLX Technology, Inc.
28*4882a593Smuzhiyun * Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * Modified Seth Levy 2005 PLX Technology, Inc. to provide compatibility
31*4882a593Smuzhiyun * with 2282 chip
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * Modified Ricardo Ribalda Qtechnology AS to provide compatibility
34*4882a593Smuzhiyun * with usb 338x chip. Based on PLX driver
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include <linux/module.h>
38*4882a593Smuzhiyun #include <linux/pci.h>
39*4882a593Smuzhiyun #include <linux/dma-mapping.h>
40*4882a593Smuzhiyun #include <linux/kernel.h>
41*4882a593Smuzhiyun #include <linux/delay.h>
42*4882a593Smuzhiyun #include <linux/ioport.h>
43*4882a593Smuzhiyun #include <linux/slab.h>
44*4882a593Smuzhiyun #include <linux/errno.h>
45*4882a593Smuzhiyun #include <linux/init.h>
46*4882a593Smuzhiyun #include <linux/timer.h>
47*4882a593Smuzhiyun #include <linux/list.h>
48*4882a593Smuzhiyun #include <linux/interrupt.h>
49*4882a593Smuzhiyun #include <linux/moduleparam.h>
50*4882a593Smuzhiyun #include <linux/device.h>
51*4882a593Smuzhiyun #include <linux/usb/ch9.h>
52*4882a593Smuzhiyun #include <linux/usb/gadget.h>
53*4882a593Smuzhiyun #include <linux/prefetch.h>
54*4882a593Smuzhiyun #include <linux/io.h>
55*4882a593Smuzhiyun #include <linux/iopoll.h>
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #include <asm/byteorder.h>
58*4882a593Smuzhiyun #include <asm/irq.h>
59*4882a593Smuzhiyun #include <asm/unaligned.h>
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define DRIVER_DESC "PLX NET228x/USB338x USB Peripheral Controller"
62*4882a593Smuzhiyun #define DRIVER_VERSION "2005 Sept 27/v3.0"
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define EP_DONTUSE 13 /* nonzero */
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define USE_RDK_LEDS /* GPIO pins control three LEDs */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static const char driver_name[] = "net2280";
70*4882a593Smuzhiyun static const char driver_desc[] = DRIVER_DESC;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun static const u32 ep_bit[9] = { 0, 17, 2, 19, 4, 1, 18, 3, 20 };
73*4882a593Smuzhiyun static const char ep0name[] = "ep0";
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define EP_INFO(_name, _caps) \
76*4882a593Smuzhiyun { \
77*4882a593Smuzhiyun .name = _name, \
78*4882a593Smuzhiyun .caps = _caps, \
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct {
82*4882a593Smuzhiyun const char *name;
83*4882a593Smuzhiyun const struct usb_ep_caps caps;
84*4882a593Smuzhiyun } ep_info_dft[] = { /* Default endpoint configuration */
85*4882a593Smuzhiyun EP_INFO(ep0name,
86*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
87*4882a593Smuzhiyun EP_INFO("ep-a",
88*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)),
89*4882a593Smuzhiyun EP_INFO("ep-b",
90*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)),
91*4882a593Smuzhiyun EP_INFO("ep-c",
92*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)),
93*4882a593Smuzhiyun EP_INFO("ep-d",
94*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)),
95*4882a593Smuzhiyun EP_INFO("ep-e",
96*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)),
97*4882a593Smuzhiyun EP_INFO("ep-f",
98*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)),
99*4882a593Smuzhiyun EP_INFO("ep-g",
100*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)),
101*4882a593Smuzhiyun EP_INFO("ep-h",
102*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_ALL)),
103*4882a593Smuzhiyun }, ep_info_adv[] = { /* Endpoints for usb3380 advance mode */
104*4882a593Smuzhiyun EP_INFO(ep0name,
105*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_ALL)),
106*4882a593Smuzhiyun EP_INFO("ep1in",
107*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_IN)),
108*4882a593Smuzhiyun EP_INFO("ep2out",
109*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_OUT)),
110*4882a593Smuzhiyun EP_INFO("ep3in",
111*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_IN)),
112*4882a593Smuzhiyun EP_INFO("ep4out",
113*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_OUT)),
114*4882a593Smuzhiyun EP_INFO("ep1out",
115*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_OUT)),
116*4882a593Smuzhiyun EP_INFO("ep2in",
117*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_IN)),
118*4882a593Smuzhiyun EP_INFO("ep3out",
119*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_OUT)),
120*4882a593Smuzhiyun EP_INFO("ep4in",
121*4882a593Smuzhiyun USB_EP_CAPS(USB_EP_CAPS_TYPE_ALL, USB_EP_CAPS_DIR_IN)),
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #undef EP_INFO
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* mode 0 == ep-{a,b,c,d} 1K fifo each
127*4882a593Smuzhiyun * mode 1 == ep-{a,b} 2K fifo each, ep-{c,d} unavailable
128*4882a593Smuzhiyun * mode 2 == ep-a 2K fifo, ep-{b,c} 1K each, ep-d unavailable
129*4882a593Smuzhiyun */
130*4882a593Smuzhiyun static ushort fifo_mode;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /* "modprobe net2280 fifo_mode=1" etc */
133*4882a593Smuzhiyun module_param(fifo_mode, ushort, 0644);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* enable_suspend -- When enabled, the driver will respond to
136*4882a593Smuzhiyun * USB suspend requests by powering down the NET2280. Otherwise,
137*4882a593Smuzhiyun * USB suspend requests will be ignored. This is acceptable for
138*4882a593Smuzhiyun * self-powered devices
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun static bool enable_suspend;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* "modprobe net2280 enable_suspend=1" etc */
143*4882a593Smuzhiyun module_param(enable_suspend, bool, 0444);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun #define DIR_STRING(bAddress) (((bAddress) & USB_DIR_IN) ? "in" : "out")
146*4882a593Smuzhiyun
type_string(u8 bmAttributes)147*4882a593Smuzhiyun static char *type_string(u8 bmAttributes)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun switch ((bmAttributes) & USB_ENDPOINT_XFERTYPE_MASK) {
150*4882a593Smuzhiyun case USB_ENDPOINT_XFER_BULK: return "bulk";
151*4882a593Smuzhiyun case USB_ENDPOINT_XFER_ISOC: return "iso";
152*4882a593Smuzhiyun case USB_ENDPOINT_XFER_INT: return "intr";
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun return "control";
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun #include "net2280.h"
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun #define valid_bit cpu_to_le32(BIT(VALID_BIT))
160*4882a593Smuzhiyun #define dma_done_ie cpu_to_le32(BIT(DMA_DONE_INTERRUPT_ENABLE))
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun static void ep_clear_seqnum(struct net2280_ep *ep);
163*4882a593Smuzhiyun static void stop_activity(struct net2280 *dev,
164*4882a593Smuzhiyun struct usb_gadget_driver *driver);
165*4882a593Smuzhiyun static void ep0_start(struct net2280 *dev);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
enable_pciirqenb(struct net2280_ep * ep)168*4882a593Smuzhiyun static inline void enable_pciirqenb(struct net2280_ep *ep)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun u32 tmp = readl(&ep->dev->regs->pciirqenb0);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun if (ep->dev->quirks & PLX_LEGACY)
173*4882a593Smuzhiyun tmp |= BIT(ep->num);
174*4882a593Smuzhiyun else
175*4882a593Smuzhiyun tmp |= BIT(ep_bit[ep->num]);
176*4882a593Smuzhiyun writel(tmp, &ep->dev->regs->pciirqenb0);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun return;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun static int
net2280_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)182*4882a593Smuzhiyun net2280_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun struct net2280 *dev;
185*4882a593Smuzhiyun struct net2280_ep *ep;
186*4882a593Smuzhiyun u32 max;
187*4882a593Smuzhiyun u32 tmp = 0;
188*4882a593Smuzhiyun u32 type;
189*4882a593Smuzhiyun unsigned long flags;
190*4882a593Smuzhiyun static const u32 ep_key[9] = { 1, 0, 1, 0, 1, 1, 0, 1, 0 };
191*4882a593Smuzhiyun int ret = 0;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun ep = container_of(_ep, struct net2280_ep, ep);
194*4882a593Smuzhiyun if (!_ep || !desc || ep->desc || _ep->name == ep0name ||
195*4882a593Smuzhiyun desc->bDescriptorType != USB_DT_ENDPOINT) {
196*4882a593Smuzhiyun pr_err("%s: failed at line=%d\n", __func__, __LINE__);
197*4882a593Smuzhiyun return -EINVAL;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun dev = ep->dev;
200*4882a593Smuzhiyun if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
201*4882a593Smuzhiyun ret = -ESHUTDOWN;
202*4882a593Smuzhiyun goto print_err;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun /* erratum 0119 workaround ties up an endpoint number */
206*4882a593Smuzhiyun if ((desc->bEndpointAddress & 0x0f) == EP_DONTUSE) {
207*4882a593Smuzhiyun ret = -EDOM;
208*4882a593Smuzhiyun goto print_err;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun if (dev->quirks & PLX_PCIE) {
212*4882a593Smuzhiyun if ((desc->bEndpointAddress & 0x0f) >= 0x0c) {
213*4882a593Smuzhiyun ret = -EDOM;
214*4882a593Smuzhiyun goto print_err;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun ep->is_in = !!usb_endpoint_dir_in(desc);
217*4882a593Smuzhiyun if (dev->enhanced_mode && ep->is_in && ep_key[ep->num]) {
218*4882a593Smuzhiyun ret = -EINVAL;
219*4882a593Smuzhiyun goto print_err;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* sanity check ep-e/ep-f since their fifos are small */
224*4882a593Smuzhiyun max = usb_endpoint_maxp(desc);
225*4882a593Smuzhiyun if (ep->num > 4 && max > 64 && (dev->quirks & PLX_LEGACY)) {
226*4882a593Smuzhiyun ret = -ERANGE;
227*4882a593Smuzhiyun goto print_err;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
231*4882a593Smuzhiyun _ep->maxpacket = max;
232*4882a593Smuzhiyun ep->desc = desc;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* ep_reset() has already been called */
235*4882a593Smuzhiyun ep->stopped = 0;
236*4882a593Smuzhiyun ep->wedged = 0;
237*4882a593Smuzhiyun ep->out_overflow = 0;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* set speed-dependent max packet; may kick in high bandwidth */
240*4882a593Smuzhiyun set_max_speed(ep, max);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /* set type, direction, address; reset fifo counters */
243*4882a593Smuzhiyun writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if ((dev->quirks & PLX_PCIE) && dev->enhanced_mode) {
246*4882a593Smuzhiyun tmp = readl(&ep->cfg->ep_cfg);
247*4882a593Smuzhiyun /* If USB ep number doesn't match hardware ep number */
248*4882a593Smuzhiyun if ((tmp & 0xf) != usb_endpoint_num(desc)) {
249*4882a593Smuzhiyun ret = -EINVAL;
250*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
251*4882a593Smuzhiyun goto print_err;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun if (ep->is_in)
254*4882a593Smuzhiyun tmp &= ~USB3380_EP_CFG_MASK_IN;
255*4882a593Smuzhiyun else
256*4882a593Smuzhiyun tmp &= ~USB3380_EP_CFG_MASK_OUT;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun type = (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK);
259*4882a593Smuzhiyun if (type == USB_ENDPOINT_XFER_INT) {
260*4882a593Smuzhiyun /* erratum 0105 workaround prevents hs NYET */
261*4882a593Smuzhiyun if (dev->chiprev == 0100 &&
262*4882a593Smuzhiyun dev->gadget.speed == USB_SPEED_HIGH &&
263*4882a593Smuzhiyun !(desc->bEndpointAddress & USB_DIR_IN))
264*4882a593Smuzhiyun writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE),
265*4882a593Smuzhiyun &ep->regs->ep_rsp);
266*4882a593Smuzhiyun } else if (type == USB_ENDPOINT_XFER_BULK) {
267*4882a593Smuzhiyun /* catch some particularly blatant driver bugs */
268*4882a593Smuzhiyun if ((dev->gadget.speed == USB_SPEED_SUPER && max != 1024) ||
269*4882a593Smuzhiyun (dev->gadget.speed == USB_SPEED_HIGH && max != 512) ||
270*4882a593Smuzhiyun (dev->gadget.speed == USB_SPEED_FULL && max > 64)) {
271*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
272*4882a593Smuzhiyun ret = -ERANGE;
273*4882a593Smuzhiyun goto print_err;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun ep->is_iso = (type == USB_ENDPOINT_XFER_ISOC);
277*4882a593Smuzhiyun /* Enable this endpoint */
278*4882a593Smuzhiyun if (dev->quirks & PLX_LEGACY) {
279*4882a593Smuzhiyun tmp |= type << ENDPOINT_TYPE;
280*4882a593Smuzhiyun tmp |= desc->bEndpointAddress;
281*4882a593Smuzhiyun /* default full fifo lines */
282*4882a593Smuzhiyun tmp |= (4 << ENDPOINT_BYTE_COUNT);
283*4882a593Smuzhiyun tmp |= BIT(ENDPOINT_ENABLE);
284*4882a593Smuzhiyun ep->is_in = (tmp & USB_DIR_IN) != 0;
285*4882a593Smuzhiyun } else {
286*4882a593Smuzhiyun /* In Legacy mode, only OUT endpoints are used */
287*4882a593Smuzhiyun if (dev->enhanced_mode && ep->is_in) {
288*4882a593Smuzhiyun tmp |= type << IN_ENDPOINT_TYPE;
289*4882a593Smuzhiyun tmp |= BIT(IN_ENDPOINT_ENABLE);
290*4882a593Smuzhiyun } else {
291*4882a593Smuzhiyun tmp |= type << OUT_ENDPOINT_TYPE;
292*4882a593Smuzhiyun tmp |= BIT(OUT_ENDPOINT_ENABLE);
293*4882a593Smuzhiyun tmp |= (ep->is_in << ENDPOINT_DIRECTION);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun tmp |= (4 << ENDPOINT_BYTE_COUNT);
297*4882a593Smuzhiyun if (!dev->enhanced_mode)
298*4882a593Smuzhiyun tmp |= usb_endpoint_num(desc);
299*4882a593Smuzhiyun tmp |= (ep->ep.maxburst << MAX_BURST_SIZE);
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun /* Make sure all the registers are written before ep_rsp*/
303*4882a593Smuzhiyun wmb();
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /* for OUT transfers, block the rx fifo until a read is posted */
306*4882a593Smuzhiyun if (!ep->is_in)
307*4882a593Smuzhiyun writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
308*4882a593Smuzhiyun else if (!(dev->quirks & PLX_2280)) {
309*4882a593Smuzhiyun /* Added for 2282, Don't use nak packets on an in endpoint,
310*4882a593Smuzhiyun * this was ignored on 2280
311*4882a593Smuzhiyun */
312*4882a593Smuzhiyun writel(BIT(CLEAR_NAK_OUT_PACKETS) |
313*4882a593Smuzhiyun BIT(CLEAR_NAK_OUT_PACKETS_MODE), &ep->regs->ep_rsp);
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun if (dev->quirks & PLX_PCIE)
317*4882a593Smuzhiyun ep_clear_seqnum(ep);
318*4882a593Smuzhiyun writel(tmp, &ep->cfg->ep_cfg);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun /* enable irqs */
321*4882a593Smuzhiyun if (!ep->dma) { /* pio, per-packet */
322*4882a593Smuzhiyun enable_pciirqenb(ep);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun tmp = BIT(DATA_PACKET_RECEIVED_INTERRUPT_ENABLE) |
325*4882a593Smuzhiyun BIT(DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE);
326*4882a593Smuzhiyun if (dev->quirks & PLX_2280)
327*4882a593Smuzhiyun tmp |= readl(&ep->regs->ep_irqenb);
328*4882a593Smuzhiyun writel(tmp, &ep->regs->ep_irqenb);
329*4882a593Smuzhiyun } else { /* dma, per-request */
330*4882a593Smuzhiyun tmp = BIT((8 + ep->num)); /* completion */
331*4882a593Smuzhiyun tmp |= readl(&dev->regs->pciirqenb1);
332*4882a593Smuzhiyun writel(tmp, &dev->regs->pciirqenb1);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* for short OUT transfers, dma completions can't
335*4882a593Smuzhiyun * advance the queue; do it pio-style, by hand.
336*4882a593Smuzhiyun * NOTE erratum 0112 workaround #2
337*4882a593Smuzhiyun */
338*4882a593Smuzhiyun if ((desc->bEndpointAddress & USB_DIR_IN) == 0) {
339*4882a593Smuzhiyun tmp = BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE);
340*4882a593Smuzhiyun writel(tmp, &ep->regs->ep_irqenb);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun enable_pciirqenb(ep);
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun tmp = desc->bEndpointAddress;
347*4882a593Smuzhiyun ep_dbg(dev, "enabled %s (ep%d%s-%s) %s max %04x\n",
348*4882a593Smuzhiyun _ep->name, tmp & 0x0f, DIR_STRING(tmp),
349*4882a593Smuzhiyun type_string(desc->bmAttributes),
350*4882a593Smuzhiyun ep->dma ? "dma" : "pio", max);
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun /* pci writes may still be posted */
353*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
354*4882a593Smuzhiyun return ret;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun print_err:
357*4882a593Smuzhiyun dev_err(&ep->dev->pdev->dev, "%s: error=%d\n", __func__, ret);
358*4882a593Smuzhiyun return ret;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
handshake(u32 __iomem * ptr,u32 mask,u32 done,int usec)361*4882a593Smuzhiyun static int handshake(u32 __iomem *ptr, u32 mask, u32 done, int usec)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun u32 result;
364*4882a593Smuzhiyun int ret;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun ret = readl_poll_timeout_atomic(ptr, result,
367*4882a593Smuzhiyun ((result & mask) == done ||
368*4882a593Smuzhiyun result == U32_MAX),
369*4882a593Smuzhiyun 1, usec);
370*4882a593Smuzhiyun if (result == U32_MAX) /* device unplugged */
371*4882a593Smuzhiyun return -ENODEV;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun return ret;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun static const struct usb_ep_ops net2280_ep_ops;
377*4882a593Smuzhiyun
ep_reset_228x(struct net2280_regs __iomem * regs,struct net2280_ep * ep)378*4882a593Smuzhiyun static void ep_reset_228x(struct net2280_regs __iomem *regs,
379*4882a593Smuzhiyun struct net2280_ep *ep)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun u32 tmp;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun ep->desc = NULL;
384*4882a593Smuzhiyun INIT_LIST_HEAD(&ep->queue);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun usb_ep_set_maxpacket_limit(&ep->ep, ~0);
387*4882a593Smuzhiyun ep->ep.ops = &net2280_ep_ops;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun /* disable the dma, irqs, endpoint... */
390*4882a593Smuzhiyun if (ep->dma) {
391*4882a593Smuzhiyun writel(0, &ep->dma->dmactl);
392*4882a593Smuzhiyun writel(BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) |
393*4882a593Smuzhiyun BIT(DMA_TRANSACTION_DONE_INTERRUPT) |
394*4882a593Smuzhiyun BIT(DMA_ABORT),
395*4882a593Smuzhiyun &ep->dma->dmastat);
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun tmp = readl(®s->pciirqenb0);
398*4882a593Smuzhiyun tmp &= ~BIT(ep->num);
399*4882a593Smuzhiyun writel(tmp, ®s->pciirqenb0);
400*4882a593Smuzhiyun } else {
401*4882a593Smuzhiyun tmp = readl(®s->pciirqenb1);
402*4882a593Smuzhiyun tmp &= ~BIT((8 + ep->num)); /* completion */
403*4882a593Smuzhiyun writel(tmp, ®s->pciirqenb1);
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun writel(0, &ep->regs->ep_irqenb);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /* init to our chosen defaults, notably so that we NAK OUT
408*4882a593Smuzhiyun * packets until the driver queues a read (+note erratum 0112)
409*4882a593Smuzhiyun */
410*4882a593Smuzhiyun if (!ep->is_in || (ep->dev->quirks & PLX_2280)) {
411*4882a593Smuzhiyun tmp = BIT(SET_NAK_OUT_PACKETS_MODE) |
412*4882a593Smuzhiyun BIT(SET_NAK_OUT_PACKETS) |
413*4882a593Smuzhiyun BIT(CLEAR_EP_HIDE_STATUS_PHASE) |
414*4882a593Smuzhiyun BIT(CLEAR_INTERRUPT_MODE);
415*4882a593Smuzhiyun } else {
416*4882a593Smuzhiyun /* added for 2282 */
417*4882a593Smuzhiyun tmp = BIT(CLEAR_NAK_OUT_PACKETS_MODE) |
418*4882a593Smuzhiyun BIT(CLEAR_NAK_OUT_PACKETS) |
419*4882a593Smuzhiyun BIT(CLEAR_EP_HIDE_STATUS_PHASE) |
420*4882a593Smuzhiyun BIT(CLEAR_INTERRUPT_MODE);
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun if (ep->num != 0) {
424*4882a593Smuzhiyun tmp |= BIT(CLEAR_ENDPOINT_TOGGLE) |
425*4882a593Smuzhiyun BIT(CLEAR_ENDPOINT_HALT);
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun writel(tmp, &ep->regs->ep_rsp);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun /* scrub most status bits, and flush any fifo state */
430*4882a593Smuzhiyun if (ep->dev->quirks & PLX_2280)
431*4882a593Smuzhiyun tmp = BIT(FIFO_OVERFLOW) |
432*4882a593Smuzhiyun BIT(FIFO_UNDERFLOW);
433*4882a593Smuzhiyun else
434*4882a593Smuzhiyun tmp = 0;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun writel(tmp | BIT(TIMEOUT) |
437*4882a593Smuzhiyun BIT(USB_STALL_SENT) |
438*4882a593Smuzhiyun BIT(USB_IN_NAK_SENT) |
439*4882a593Smuzhiyun BIT(USB_IN_ACK_RCVD) |
440*4882a593Smuzhiyun BIT(USB_OUT_PING_NAK_SENT) |
441*4882a593Smuzhiyun BIT(USB_OUT_ACK_SENT) |
442*4882a593Smuzhiyun BIT(FIFO_FLUSH) |
443*4882a593Smuzhiyun BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) |
444*4882a593Smuzhiyun BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) |
445*4882a593Smuzhiyun BIT(DATA_PACKET_RECEIVED_INTERRUPT) |
446*4882a593Smuzhiyun BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) |
447*4882a593Smuzhiyun BIT(DATA_OUT_PING_TOKEN_INTERRUPT) |
448*4882a593Smuzhiyun BIT(DATA_IN_TOKEN_INTERRUPT),
449*4882a593Smuzhiyun &ep->regs->ep_stat);
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun /* fifo size is handled separately */
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
ep_reset_338x(struct net2280_regs __iomem * regs,struct net2280_ep * ep)454*4882a593Smuzhiyun static void ep_reset_338x(struct net2280_regs __iomem *regs,
455*4882a593Smuzhiyun struct net2280_ep *ep)
456*4882a593Smuzhiyun {
457*4882a593Smuzhiyun u32 tmp, dmastat;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun ep->desc = NULL;
460*4882a593Smuzhiyun INIT_LIST_HEAD(&ep->queue);
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun usb_ep_set_maxpacket_limit(&ep->ep, ~0);
463*4882a593Smuzhiyun ep->ep.ops = &net2280_ep_ops;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun /* disable the dma, irqs, endpoint... */
466*4882a593Smuzhiyun if (ep->dma) {
467*4882a593Smuzhiyun writel(0, &ep->dma->dmactl);
468*4882a593Smuzhiyun writel(BIT(DMA_ABORT_DONE_INTERRUPT) |
469*4882a593Smuzhiyun BIT(DMA_PAUSE_DONE_INTERRUPT) |
470*4882a593Smuzhiyun BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) |
471*4882a593Smuzhiyun BIT(DMA_TRANSACTION_DONE_INTERRUPT),
472*4882a593Smuzhiyun /* | BIT(DMA_ABORT), */
473*4882a593Smuzhiyun &ep->dma->dmastat);
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun dmastat = readl(&ep->dma->dmastat);
476*4882a593Smuzhiyun if (dmastat == 0x5002) {
477*4882a593Smuzhiyun ep_warn(ep->dev, "The dmastat return = %x!!\n",
478*4882a593Smuzhiyun dmastat);
479*4882a593Smuzhiyun writel(0x5a, &ep->dma->dmastat);
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun tmp = readl(®s->pciirqenb0);
483*4882a593Smuzhiyun tmp &= ~BIT(ep_bit[ep->num]);
484*4882a593Smuzhiyun writel(tmp, ®s->pciirqenb0);
485*4882a593Smuzhiyun } else {
486*4882a593Smuzhiyun if (ep->num < 5) {
487*4882a593Smuzhiyun tmp = readl(®s->pciirqenb1);
488*4882a593Smuzhiyun tmp &= ~BIT((8 + ep->num)); /* completion */
489*4882a593Smuzhiyun writel(tmp, ®s->pciirqenb1);
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun writel(0, &ep->regs->ep_irqenb);
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun writel(BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) |
495*4882a593Smuzhiyun BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) |
496*4882a593Smuzhiyun BIT(FIFO_OVERFLOW) |
497*4882a593Smuzhiyun BIT(DATA_PACKET_RECEIVED_INTERRUPT) |
498*4882a593Smuzhiyun BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) |
499*4882a593Smuzhiyun BIT(DATA_OUT_PING_TOKEN_INTERRUPT) |
500*4882a593Smuzhiyun BIT(DATA_IN_TOKEN_INTERRUPT), &ep->regs->ep_stat);
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun tmp = readl(&ep->cfg->ep_cfg);
503*4882a593Smuzhiyun if (ep->is_in)
504*4882a593Smuzhiyun tmp &= ~USB3380_EP_CFG_MASK_IN;
505*4882a593Smuzhiyun else
506*4882a593Smuzhiyun tmp &= ~USB3380_EP_CFG_MASK_OUT;
507*4882a593Smuzhiyun writel(tmp, &ep->cfg->ep_cfg);
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun static void nuke(struct net2280_ep *);
511*4882a593Smuzhiyun
net2280_disable(struct usb_ep * _ep)512*4882a593Smuzhiyun static int net2280_disable(struct usb_ep *_ep)
513*4882a593Smuzhiyun {
514*4882a593Smuzhiyun struct net2280_ep *ep;
515*4882a593Smuzhiyun unsigned long flags;
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun ep = container_of(_ep, struct net2280_ep, ep);
518*4882a593Smuzhiyun if (!_ep || _ep->name == ep0name) {
519*4882a593Smuzhiyun pr_err("%s: Invalid ep=%p\n", __func__, _ep);
520*4882a593Smuzhiyun return -EINVAL;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun spin_lock_irqsave(&ep->dev->lock, flags);
523*4882a593Smuzhiyun nuke(ep);
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun if (ep->dev->quirks & PLX_PCIE)
526*4882a593Smuzhiyun ep_reset_338x(ep->dev->regs, ep);
527*4882a593Smuzhiyun else
528*4882a593Smuzhiyun ep_reset_228x(ep->dev->regs, ep);
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun ep_vdbg(ep->dev, "disabled %s %s\n",
531*4882a593Smuzhiyun ep->dma ? "dma" : "pio", _ep->name);
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun /* synch memory views with the device */
534*4882a593Smuzhiyun (void)readl(&ep->cfg->ep_cfg);
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun if (!ep->dma && ep->num >= 1 && ep->num <= 4)
537*4882a593Smuzhiyun ep->dma = &ep->dev->dma[ep->num - 1];
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun spin_unlock_irqrestore(&ep->dev->lock, flags);
540*4882a593Smuzhiyun return 0;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun static struct usb_request
net2280_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)546*4882a593Smuzhiyun *net2280_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun struct net2280_ep *ep;
549*4882a593Smuzhiyun struct net2280_request *req;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun if (!_ep) {
552*4882a593Smuzhiyun pr_err("%s: Invalid ep\n", __func__);
553*4882a593Smuzhiyun return NULL;
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun ep = container_of(_ep, struct net2280_ep, ep);
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun req = kzalloc(sizeof(*req), gfp_flags);
558*4882a593Smuzhiyun if (!req)
559*4882a593Smuzhiyun return NULL;
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun INIT_LIST_HEAD(&req->queue);
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun /* this dma descriptor may be swapped with the previous dummy */
564*4882a593Smuzhiyun if (ep->dma) {
565*4882a593Smuzhiyun struct net2280_dma *td;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun td = dma_pool_alloc(ep->dev->requests, gfp_flags,
568*4882a593Smuzhiyun &req->td_dma);
569*4882a593Smuzhiyun if (!td) {
570*4882a593Smuzhiyun kfree(req);
571*4882a593Smuzhiyun return NULL;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun td->dmacount = 0; /* not VALID */
574*4882a593Smuzhiyun td->dmadesc = td->dmaaddr;
575*4882a593Smuzhiyun req->td = td;
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun return &req->req;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
net2280_free_request(struct usb_ep * _ep,struct usb_request * _req)580*4882a593Smuzhiyun static void net2280_free_request(struct usb_ep *_ep, struct usb_request *_req)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun struct net2280_ep *ep;
583*4882a593Smuzhiyun struct net2280_request *req;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun ep = container_of(_ep, struct net2280_ep, ep);
586*4882a593Smuzhiyun if (!_ep || !_req) {
587*4882a593Smuzhiyun dev_err(&ep->dev->pdev->dev, "%s: Invalid ep=%p or req=%p\n",
588*4882a593Smuzhiyun __func__, _ep, _req);
589*4882a593Smuzhiyun return;
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun req = container_of(_req, struct net2280_request, req);
593*4882a593Smuzhiyun WARN_ON(!list_empty(&req->queue));
594*4882a593Smuzhiyun if (req->td)
595*4882a593Smuzhiyun dma_pool_free(ep->dev->requests, req->td, req->td_dma);
596*4882a593Smuzhiyun kfree(req);
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun /* load a packet into the fifo we use for usb IN transfers.
602*4882a593Smuzhiyun * works for all endpoints.
603*4882a593Smuzhiyun *
604*4882a593Smuzhiyun * NOTE: pio with ep-a..ep-d could stuff multiple packets into the fifo
605*4882a593Smuzhiyun * at a time, but this code is simpler because it knows it only writes
606*4882a593Smuzhiyun * one packet. ep-a..ep-d should use dma instead.
607*4882a593Smuzhiyun */
write_fifo(struct net2280_ep * ep,struct usb_request * req)608*4882a593Smuzhiyun static void write_fifo(struct net2280_ep *ep, struct usb_request *req)
609*4882a593Smuzhiyun {
610*4882a593Smuzhiyun struct net2280_ep_regs __iomem *regs = ep->regs;
611*4882a593Smuzhiyun u8 *buf;
612*4882a593Smuzhiyun u32 tmp;
613*4882a593Smuzhiyun unsigned count, total;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun /* INVARIANT: fifo is currently empty. (testable) */
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun if (req) {
618*4882a593Smuzhiyun buf = req->buf + req->actual;
619*4882a593Smuzhiyun prefetch(buf);
620*4882a593Smuzhiyun total = req->length - req->actual;
621*4882a593Smuzhiyun } else {
622*4882a593Smuzhiyun total = 0;
623*4882a593Smuzhiyun buf = NULL;
624*4882a593Smuzhiyun }
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun /* write just one packet at a time */
627*4882a593Smuzhiyun count = ep->ep.maxpacket;
628*4882a593Smuzhiyun if (count > total) /* min() cannot be used on a bitfield */
629*4882a593Smuzhiyun count = total;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun ep_vdbg(ep->dev, "write %s fifo (IN) %d bytes%s req %p\n",
632*4882a593Smuzhiyun ep->ep.name, count,
633*4882a593Smuzhiyun (count != ep->ep.maxpacket) ? " (short)" : "",
634*4882a593Smuzhiyun req);
635*4882a593Smuzhiyun while (count >= 4) {
636*4882a593Smuzhiyun /* NOTE be careful if you try to align these. fifo lines
637*4882a593Smuzhiyun * should normally be full (4 bytes) and successive partial
638*4882a593Smuzhiyun * lines are ok only in certain cases.
639*4882a593Smuzhiyun */
640*4882a593Smuzhiyun tmp = get_unaligned((u32 *)buf);
641*4882a593Smuzhiyun cpu_to_le32s(&tmp);
642*4882a593Smuzhiyun writel(tmp, ®s->ep_data);
643*4882a593Smuzhiyun buf += 4;
644*4882a593Smuzhiyun count -= 4;
645*4882a593Smuzhiyun }
646*4882a593Smuzhiyun
647*4882a593Smuzhiyun /* last fifo entry is "short" unless we wrote a full packet.
648*4882a593Smuzhiyun * also explicitly validate last word in (periodic) transfers
649*4882a593Smuzhiyun * when maxpacket is not a multiple of 4 bytes.
650*4882a593Smuzhiyun */
651*4882a593Smuzhiyun if (count || total < ep->ep.maxpacket) {
652*4882a593Smuzhiyun tmp = count ? get_unaligned((u32 *)buf) : count;
653*4882a593Smuzhiyun cpu_to_le32s(&tmp);
654*4882a593Smuzhiyun set_fifo_bytecount(ep, count & 0x03);
655*4882a593Smuzhiyun writel(tmp, ®s->ep_data);
656*4882a593Smuzhiyun }
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun /* pci writes may still be posted */
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun /* work around erratum 0106: PCI and USB race over the OUT fifo.
662*4882a593Smuzhiyun * caller guarantees chiprev 0100, out endpoint is NAKing, and
663*4882a593Smuzhiyun * there's no real data in the fifo.
664*4882a593Smuzhiyun *
665*4882a593Smuzhiyun * NOTE: also used in cases where that erratum doesn't apply:
666*4882a593Smuzhiyun * where the host wrote "too much" data to us.
667*4882a593Smuzhiyun */
out_flush(struct net2280_ep * ep)668*4882a593Smuzhiyun static void out_flush(struct net2280_ep *ep)
669*4882a593Smuzhiyun {
670*4882a593Smuzhiyun u32 __iomem *statp;
671*4882a593Smuzhiyun u32 tmp;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun statp = &ep->regs->ep_stat;
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun tmp = readl(statp);
676*4882a593Smuzhiyun if (tmp & BIT(NAK_OUT_PACKETS)) {
677*4882a593Smuzhiyun ep_dbg(ep->dev, "%s %s %08x !NAK\n",
678*4882a593Smuzhiyun ep->ep.name, __func__, tmp);
679*4882a593Smuzhiyun writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
680*4882a593Smuzhiyun }
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun writel(BIT(DATA_OUT_PING_TOKEN_INTERRUPT) |
683*4882a593Smuzhiyun BIT(DATA_PACKET_RECEIVED_INTERRUPT),
684*4882a593Smuzhiyun statp);
685*4882a593Smuzhiyun writel(BIT(FIFO_FLUSH), statp);
686*4882a593Smuzhiyun /* Make sure that stap is written */
687*4882a593Smuzhiyun mb();
688*4882a593Smuzhiyun tmp = readl(statp);
689*4882a593Smuzhiyun if (tmp & BIT(DATA_OUT_PING_TOKEN_INTERRUPT) &&
690*4882a593Smuzhiyun /* high speed did bulk NYET; fifo isn't filling */
691*4882a593Smuzhiyun ep->dev->gadget.speed == USB_SPEED_FULL) {
692*4882a593Smuzhiyun unsigned usec;
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun usec = 50; /* 64 byte bulk/interrupt */
695*4882a593Smuzhiyun handshake(statp, BIT(USB_OUT_PING_NAK_SENT),
696*4882a593Smuzhiyun BIT(USB_OUT_PING_NAK_SENT), usec);
697*4882a593Smuzhiyun /* NAK done; now CLEAR_NAK_OUT_PACKETS is safe */
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun /* unload packet(s) from the fifo we use for usb OUT transfers.
702*4882a593Smuzhiyun * returns true iff the request completed, because of short packet
703*4882a593Smuzhiyun * or the request buffer having filled with full packets.
704*4882a593Smuzhiyun *
705*4882a593Smuzhiyun * for ep-a..ep-d this will read multiple packets out when they
706*4882a593Smuzhiyun * have been accepted.
707*4882a593Smuzhiyun */
read_fifo(struct net2280_ep * ep,struct net2280_request * req)708*4882a593Smuzhiyun static int read_fifo(struct net2280_ep *ep, struct net2280_request *req)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun struct net2280_ep_regs __iomem *regs = ep->regs;
711*4882a593Smuzhiyun u8 *buf = req->req.buf + req->req.actual;
712*4882a593Smuzhiyun unsigned count, tmp, is_short;
713*4882a593Smuzhiyun unsigned cleanup = 0, prevent = 0;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun /* erratum 0106 ... packets coming in during fifo reads might
716*4882a593Smuzhiyun * be incompletely rejected. not all cases have workarounds.
717*4882a593Smuzhiyun */
718*4882a593Smuzhiyun if (ep->dev->chiprev == 0x0100 &&
719*4882a593Smuzhiyun ep->dev->gadget.speed == USB_SPEED_FULL) {
720*4882a593Smuzhiyun udelay(1);
721*4882a593Smuzhiyun tmp = readl(&ep->regs->ep_stat);
722*4882a593Smuzhiyun if ((tmp & BIT(NAK_OUT_PACKETS)))
723*4882a593Smuzhiyun cleanup = 1;
724*4882a593Smuzhiyun else if ((tmp & BIT(FIFO_FULL))) {
725*4882a593Smuzhiyun start_out_naking(ep);
726*4882a593Smuzhiyun prevent = 1;
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun /* else: hope we don't see the problem */
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun /* never overflow the rx buffer. the fifo reads packets until
732*4882a593Smuzhiyun * it sees a short one; we might not be ready for them all.
733*4882a593Smuzhiyun */
734*4882a593Smuzhiyun prefetchw(buf);
735*4882a593Smuzhiyun count = readl(®s->ep_avail);
736*4882a593Smuzhiyun if (unlikely(count == 0)) {
737*4882a593Smuzhiyun udelay(1);
738*4882a593Smuzhiyun tmp = readl(&ep->regs->ep_stat);
739*4882a593Smuzhiyun count = readl(®s->ep_avail);
740*4882a593Smuzhiyun /* handled that data already? */
741*4882a593Smuzhiyun if (count == 0 && (tmp & BIT(NAK_OUT_PACKETS)) == 0)
742*4882a593Smuzhiyun return 0;
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun tmp = req->req.length - req->req.actual;
746*4882a593Smuzhiyun if (count > tmp) {
747*4882a593Smuzhiyun /* as with DMA, data overflow gets flushed */
748*4882a593Smuzhiyun if ((tmp % ep->ep.maxpacket) != 0) {
749*4882a593Smuzhiyun ep_err(ep->dev,
750*4882a593Smuzhiyun "%s out fifo %d bytes, expected %d\n",
751*4882a593Smuzhiyun ep->ep.name, count, tmp);
752*4882a593Smuzhiyun req->req.status = -EOVERFLOW;
753*4882a593Smuzhiyun cleanup = 1;
754*4882a593Smuzhiyun /* NAK_OUT_PACKETS will be set, so flushing is safe;
755*4882a593Smuzhiyun * the next read will start with the next packet
756*4882a593Smuzhiyun */
757*4882a593Smuzhiyun } /* else it's a ZLP, no worries */
758*4882a593Smuzhiyun count = tmp;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun req->req.actual += count;
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun is_short = (count == 0) || ((count % ep->ep.maxpacket) != 0);
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun ep_vdbg(ep->dev, "read %s fifo (OUT) %d bytes%s%s%s req %p %d/%d\n",
765*4882a593Smuzhiyun ep->ep.name, count, is_short ? " (short)" : "",
766*4882a593Smuzhiyun cleanup ? " flush" : "", prevent ? " nak" : "",
767*4882a593Smuzhiyun req, req->req.actual, req->req.length);
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun while (count >= 4) {
770*4882a593Smuzhiyun tmp = readl(®s->ep_data);
771*4882a593Smuzhiyun cpu_to_le32s(&tmp);
772*4882a593Smuzhiyun put_unaligned(tmp, (u32 *)buf);
773*4882a593Smuzhiyun buf += 4;
774*4882a593Smuzhiyun count -= 4;
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun if (count) {
777*4882a593Smuzhiyun tmp = readl(®s->ep_data);
778*4882a593Smuzhiyun /* LE conversion is implicit here: */
779*4882a593Smuzhiyun do {
780*4882a593Smuzhiyun *buf++ = (u8) tmp;
781*4882a593Smuzhiyun tmp >>= 8;
782*4882a593Smuzhiyun } while (--count);
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun if (cleanup)
785*4882a593Smuzhiyun out_flush(ep);
786*4882a593Smuzhiyun if (prevent) {
787*4882a593Smuzhiyun writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
788*4882a593Smuzhiyun (void) readl(&ep->regs->ep_rsp);
789*4882a593Smuzhiyun }
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun return is_short || req->req.actual == req->req.length;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun /* fill out dma descriptor to match a given request */
fill_dma_desc(struct net2280_ep * ep,struct net2280_request * req,int valid)795*4882a593Smuzhiyun static void fill_dma_desc(struct net2280_ep *ep,
796*4882a593Smuzhiyun struct net2280_request *req, int valid)
797*4882a593Smuzhiyun {
798*4882a593Smuzhiyun struct net2280_dma *td = req->td;
799*4882a593Smuzhiyun u32 dmacount = req->req.length;
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun /* don't let DMA continue after a short OUT packet,
802*4882a593Smuzhiyun * so overruns can't affect the next transfer.
803*4882a593Smuzhiyun * in case of overruns on max-size packets, we can't
804*4882a593Smuzhiyun * stop the fifo from filling but we can flush it.
805*4882a593Smuzhiyun */
806*4882a593Smuzhiyun if (ep->is_in)
807*4882a593Smuzhiyun dmacount |= BIT(DMA_DIRECTION);
808*4882a593Smuzhiyun if ((!ep->is_in && (dmacount % ep->ep.maxpacket) != 0) ||
809*4882a593Smuzhiyun !(ep->dev->quirks & PLX_2280))
810*4882a593Smuzhiyun dmacount |= BIT(END_OF_CHAIN);
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun req->valid = valid;
813*4882a593Smuzhiyun if (valid)
814*4882a593Smuzhiyun dmacount |= BIT(VALID_BIT);
815*4882a593Smuzhiyun dmacount |= BIT(DMA_DONE_INTERRUPT_ENABLE);
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun /* td->dmadesc = previously set by caller */
818*4882a593Smuzhiyun td->dmaaddr = cpu_to_le32 (req->req.dma);
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun /* 2280 may be polling VALID_BIT through ep->dma->dmadesc */
821*4882a593Smuzhiyun wmb();
822*4882a593Smuzhiyun td->dmacount = cpu_to_le32(dmacount);
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun static const u32 dmactl_default =
826*4882a593Smuzhiyun BIT(DMA_SCATTER_GATHER_DONE_INTERRUPT) |
827*4882a593Smuzhiyun BIT(DMA_CLEAR_COUNT_ENABLE) |
828*4882a593Smuzhiyun /* erratum 0116 workaround part 1 (use POLLING) */
829*4882a593Smuzhiyun (POLL_100_USEC << DESCRIPTOR_POLLING_RATE) |
830*4882a593Smuzhiyun BIT(DMA_VALID_BIT_POLLING_ENABLE) |
831*4882a593Smuzhiyun BIT(DMA_VALID_BIT_ENABLE) |
832*4882a593Smuzhiyun BIT(DMA_SCATTER_GATHER_ENABLE) |
833*4882a593Smuzhiyun /* erratum 0116 workaround part 2 (no AUTOSTART) */
834*4882a593Smuzhiyun BIT(DMA_ENABLE);
835*4882a593Smuzhiyun
spin_stop_dma(struct net2280_dma_regs __iomem * dma)836*4882a593Smuzhiyun static inline void spin_stop_dma(struct net2280_dma_regs __iomem *dma)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun handshake(&dma->dmactl, BIT(DMA_ENABLE), 0, 50);
839*4882a593Smuzhiyun }
840*4882a593Smuzhiyun
stop_dma(struct net2280_dma_regs __iomem * dma)841*4882a593Smuzhiyun static inline void stop_dma(struct net2280_dma_regs __iomem *dma)
842*4882a593Smuzhiyun {
843*4882a593Smuzhiyun writel(readl(&dma->dmactl) & ~BIT(DMA_ENABLE), &dma->dmactl);
844*4882a593Smuzhiyun spin_stop_dma(dma);
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun
start_queue(struct net2280_ep * ep,u32 dmactl,u32 td_dma)847*4882a593Smuzhiyun static void start_queue(struct net2280_ep *ep, u32 dmactl, u32 td_dma)
848*4882a593Smuzhiyun {
849*4882a593Smuzhiyun struct net2280_dma_regs __iomem *dma = ep->dma;
850*4882a593Smuzhiyun unsigned int tmp = BIT(VALID_BIT) | (ep->is_in << DMA_DIRECTION);
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun if (!(ep->dev->quirks & PLX_2280))
853*4882a593Smuzhiyun tmp |= BIT(END_OF_CHAIN);
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun writel(tmp, &dma->dmacount);
856*4882a593Smuzhiyun writel(readl(&dma->dmastat), &dma->dmastat);
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun writel(td_dma, &dma->dmadesc);
859*4882a593Smuzhiyun if (ep->dev->quirks & PLX_PCIE)
860*4882a593Smuzhiyun dmactl |= BIT(DMA_REQUEST_OUTSTANDING);
861*4882a593Smuzhiyun writel(dmactl, &dma->dmactl);
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun /* erratum 0116 workaround part 3: pci arbiter away from net2280 */
864*4882a593Smuzhiyun (void) readl(&ep->dev->pci->pcimstctl);
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun writel(BIT(DMA_START), &dma->dmastat);
867*4882a593Smuzhiyun }
868*4882a593Smuzhiyun
start_dma(struct net2280_ep * ep,struct net2280_request * req)869*4882a593Smuzhiyun static void start_dma(struct net2280_ep *ep, struct net2280_request *req)
870*4882a593Smuzhiyun {
871*4882a593Smuzhiyun u32 tmp;
872*4882a593Smuzhiyun struct net2280_dma_regs __iomem *dma = ep->dma;
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun /* FIXME can't use DMA for ZLPs */
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun /* on this path we "know" there's no dma active (yet) */
877*4882a593Smuzhiyun WARN_ON(readl(&dma->dmactl) & BIT(DMA_ENABLE));
878*4882a593Smuzhiyun writel(0, &ep->dma->dmactl);
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun /* previous OUT packet might have been short */
881*4882a593Smuzhiyun if (!ep->is_in && (readl(&ep->regs->ep_stat) &
882*4882a593Smuzhiyun BIT(NAK_OUT_PACKETS))) {
883*4882a593Smuzhiyun writel(BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT),
884*4882a593Smuzhiyun &ep->regs->ep_stat);
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun tmp = readl(&ep->regs->ep_avail);
887*4882a593Smuzhiyun if (tmp) {
888*4882a593Smuzhiyun writel(readl(&dma->dmastat), &dma->dmastat);
889*4882a593Smuzhiyun
890*4882a593Smuzhiyun /* transfer all/some fifo data */
891*4882a593Smuzhiyun writel(req->req.dma, &dma->dmaaddr);
892*4882a593Smuzhiyun tmp = min(tmp, req->req.length);
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun /* dma irq, faking scatterlist status */
895*4882a593Smuzhiyun req->td->dmacount = cpu_to_le32(req->req.length - tmp);
896*4882a593Smuzhiyun writel(BIT(DMA_DONE_INTERRUPT_ENABLE) | tmp,
897*4882a593Smuzhiyun &dma->dmacount);
898*4882a593Smuzhiyun req->td->dmadesc = 0;
899*4882a593Smuzhiyun req->valid = 1;
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun writel(BIT(DMA_ENABLE), &dma->dmactl);
902*4882a593Smuzhiyun writel(BIT(DMA_START), &dma->dmastat);
903*4882a593Smuzhiyun return;
904*4882a593Smuzhiyun }
905*4882a593Smuzhiyun stop_out_naking(ep);
906*4882a593Smuzhiyun }
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun tmp = dmactl_default;
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun /* force packet boundaries between dma requests, but prevent the
911*4882a593Smuzhiyun * controller from automagically writing a last "short" packet
912*4882a593Smuzhiyun * (zero length) unless the driver explicitly said to do that.
913*4882a593Smuzhiyun */
914*4882a593Smuzhiyun if (ep->is_in) {
915*4882a593Smuzhiyun if (likely((req->req.length % ep->ep.maxpacket) ||
916*4882a593Smuzhiyun req->req.zero)){
917*4882a593Smuzhiyun tmp |= BIT(DMA_FIFO_VALIDATE);
918*4882a593Smuzhiyun ep->in_fifo_validate = 1;
919*4882a593Smuzhiyun } else
920*4882a593Smuzhiyun ep->in_fifo_validate = 0;
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun /* init req->td, pointing to the current dummy */
924*4882a593Smuzhiyun req->td->dmadesc = cpu_to_le32 (ep->td_dma);
925*4882a593Smuzhiyun fill_dma_desc(ep, req, 1);
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun req->td->dmacount |= cpu_to_le32(BIT(END_OF_CHAIN));
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun start_queue(ep, tmp, req->td_dma);
930*4882a593Smuzhiyun }
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun static inline void
queue_dma(struct net2280_ep * ep,struct net2280_request * req,int valid)933*4882a593Smuzhiyun queue_dma(struct net2280_ep *ep, struct net2280_request *req, int valid)
934*4882a593Smuzhiyun {
935*4882a593Smuzhiyun struct net2280_dma *end;
936*4882a593Smuzhiyun dma_addr_t tmp;
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun /* swap new dummy for old, link; fill and maybe activate */
939*4882a593Smuzhiyun end = ep->dummy;
940*4882a593Smuzhiyun ep->dummy = req->td;
941*4882a593Smuzhiyun req->td = end;
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun tmp = ep->td_dma;
944*4882a593Smuzhiyun ep->td_dma = req->td_dma;
945*4882a593Smuzhiyun req->td_dma = tmp;
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun end->dmadesc = cpu_to_le32 (ep->td_dma);
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun fill_dma_desc(ep, req, valid);
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun static void
done(struct net2280_ep * ep,struct net2280_request * req,int status)953*4882a593Smuzhiyun done(struct net2280_ep *ep, struct net2280_request *req, int status)
954*4882a593Smuzhiyun {
955*4882a593Smuzhiyun struct net2280 *dev;
956*4882a593Smuzhiyun unsigned stopped = ep->stopped;
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun list_del_init(&req->queue);
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun if (req->req.status == -EINPROGRESS)
961*4882a593Smuzhiyun req->req.status = status;
962*4882a593Smuzhiyun else
963*4882a593Smuzhiyun status = req->req.status;
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun dev = ep->dev;
966*4882a593Smuzhiyun if (ep->dma)
967*4882a593Smuzhiyun usb_gadget_unmap_request(&dev->gadget, &req->req, ep->is_in);
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun if (status && status != -ESHUTDOWN)
970*4882a593Smuzhiyun ep_vdbg(dev, "complete %s req %p stat %d len %u/%u\n",
971*4882a593Smuzhiyun ep->ep.name, &req->req, status,
972*4882a593Smuzhiyun req->req.actual, req->req.length);
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun /* don't modify queue heads during completion callback */
975*4882a593Smuzhiyun ep->stopped = 1;
976*4882a593Smuzhiyun spin_unlock(&dev->lock);
977*4882a593Smuzhiyun usb_gadget_giveback_request(&ep->ep, &req->req);
978*4882a593Smuzhiyun spin_lock(&dev->lock);
979*4882a593Smuzhiyun ep->stopped = stopped;
980*4882a593Smuzhiyun }
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun static int
net2280_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)985*4882a593Smuzhiyun net2280_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
986*4882a593Smuzhiyun {
987*4882a593Smuzhiyun struct net2280_request *req;
988*4882a593Smuzhiyun struct net2280_ep *ep;
989*4882a593Smuzhiyun struct net2280 *dev;
990*4882a593Smuzhiyun unsigned long flags;
991*4882a593Smuzhiyun int ret = 0;
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun /* we always require a cpu-view buffer, so that we can
994*4882a593Smuzhiyun * always use pio (as fallback or whatever).
995*4882a593Smuzhiyun */
996*4882a593Smuzhiyun ep = container_of(_ep, struct net2280_ep, ep);
997*4882a593Smuzhiyun if (!_ep || (!ep->desc && ep->num != 0)) {
998*4882a593Smuzhiyun pr_err("%s: Invalid ep=%p or ep->desc\n", __func__, _ep);
999*4882a593Smuzhiyun return -EINVAL;
1000*4882a593Smuzhiyun }
1001*4882a593Smuzhiyun req = container_of(_req, struct net2280_request, req);
1002*4882a593Smuzhiyun if (!_req || !_req->complete || !_req->buf ||
1003*4882a593Smuzhiyun !list_empty(&req->queue)) {
1004*4882a593Smuzhiyun ret = -EINVAL;
1005*4882a593Smuzhiyun goto print_err;
1006*4882a593Smuzhiyun }
1007*4882a593Smuzhiyun if (_req->length > (~0 & DMA_BYTE_COUNT_MASK)) {
1008*4882a593Smuzhiyun ret = -EDOM;
1009*4882a593Smuzhiyun goto print_err;
1010*4882a593Smuzhiyun }
1011*4882a593Smuzhiyun dev = ep->dev;
1012*4882a593Smuzhiyun if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
1013*4882a593Smuzhiyun ret = -ESHUTDOWN;
1014*4882a593Smuzhiyun goto print_err;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun /* FIXME implement PIO fallback for ZLPs with DMA */
1018*4882a593Smuzhiyun if (ep->dma && _req->length == 0) {
1019*4882a593Smuzhiyun ret = -EOPNOTSUPP;
1020*4882a593Smuzhiyun goto print_err;
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun /* set up dma mapping in case the caller didn't */
1024*4882a593Smuzhiyun if (ep->dma) {
1025*4882a593Smuzhiyun ret = usb_gadget_map_request(&dev->gadget, _req,
1026*4882a593Smuzhiyun ep->is_in);
1027*4882a593Smuzhiyun if (ret)
1028*4882a593Smuzhiyun goto print_err;
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun ep_vdbg(dev, "%s queue req %p, len %d buf %p\n",
1032*4882a593Smuzhiyun _ep->name, _req, _req->length, _req->buf);
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun _req->status = -EINPROGRESS;
1037*4882a593Smuzhiyun _req->actual = 0;
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun /* kickstart this i/o queue? */
1040*4882a593Smuzhiyun if (list_empty(&ep->queue) && !ep->stopped &&
1041*4882a593Smuzhiyun !((dev->quirks & PLX_PCIE) && ep->dma &&
1042*4882a593Smuzhiyun (readl(&ep->regs->ep_rsp) & BIT(CLEAR_ENDPOINT_HALT)))) {
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun /* use DMA if the endpoint supports it, else pio */
1045*4882a593Smuzhiyun if (ep->dma)
1046*4882a593Smuzhiyun start_dma(ep, req);
1047*4882a593Smuzhiyun else {
1048*4882a593Smuzhiyun /* maybe there's no control data, just status ack */
1049*4882a593Smuzhiyun if (ep->num == 0 && _req->length == 0) {
1050*4882a593Smuzhiyun allow_status(ep);
1051*4882a593Smuzhiyun done(ep, req, 0);
1052*4882a593Smuzhiyun ep_vdbg(dev, "%s status ack\n", ep->ep.name);
1053*4882a593Smuzhiyun goto done;
1054*4882a593Smuzhiyun }
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun /* PIO ... stuff the fifo, or unblock it. */
1057*4882a593Smuzhiyun if (ep->is_in)
1058*4882a593Smuzhiyun write_fifo(ep, _req);
1059*4882a593Smuzhiyun else {
1060*4882a593Smuzhiyun u32 s;
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun /* OUT FIFO might have packet(s) buffered */
1063*4882a593Smuzhiyun s = readl(&ep->regs->ep_stat);
1064*4882a593Smuzhiyun if ((s & BIT(FIFO_EMPTY)) == 0) {
1065*4882a593Smuzhiyun /* note: _req->short_not_ok is
1066*4882a593Smuzhiyun * ignored here since PIO _always_
1067*4882a593Smuzhiyun * stops queue advance here, and
1068*4882a593Smuzhiyun * _req->status doesn't change for
1069*4882a593Smuzhiyun * short reads (only _req->actual)
1070*4882a593Smuzhiyun */
1071*4882a593Smuzhiyun if (read_fifo(ep, req) &&
1072*4882a593Smuzhiyun ep->num == 0) {
1073*4882a593Smuzhiyun done(ep, req, 0);
1074*4882a593Smuzhiyun allow_status(ep);
1075*4882a593Smuzhiyun /* don't queue it */
1076*4882a593Smuzhiyun req = NULL;
1077*4882a593Smuzhiyun } else if (read_fifo(ep, req) &&
1078*4882a593Smuzhiyun ep->num != 0) {
1079*4882a593Smuzhiyun done(ep, req, 0);
1080*4882a593Smuzhiyun req = NULL;
1081*4882a593Smuzhiyun } else
1082*4882a593Smuzhiyun s = readl(&ep->regs->ep_stat);
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun /* don't NAK, let the fifo fill */
1086*4882a593Smuzhiyun if (req && (s & BIT(NAK_OUT_PACKETS)))
1087*4882a593Smuzhiyun writel(BIT(CLEAR_NAK_OUT_PACKETS),
1088*4882a593Smuzhiyun &ep->regs->ep_rsp);
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun }
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun } else if (ep->dma) {
1093*4882a593Smuzhiyun int valid = 1;
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun if (ep->is_in) {
1096*4882a593Smuzhiyun int expect;
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun /* preventing magic zlps is per-engine state, not
1099*4882a593Smuzhiyun * per-transfer; irq logic must recover hiccups.
1100*4882a593Smuzhiyun */
1101*4882a593Smuzhiyun expect = likely(req->req.zero ||
1102*4882a593Smuzhiyun (req->req.length % ep->ep.maxpacket));
1103*4882a593Smuzhiyun if (expect != ep->in_fifo_validate)
1104*4882a593Smuzhiyun valid = 0;
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun queue_dma(ep, req, valid);
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun } /* else the irq handler advances the queue. */
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun ep->responded = 1;
1111*4882a593Smuzhiyun if (req)
1112*4882a593Smuzhiyun list_add_tail(&req->queue, &ep->queue);
1113*4882a593Smuzhiyun done:
1114*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun /* pci writes may still be posted */
1117*4882a593Smuzhiyun return ret;
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun print_err:
1120*4882a593Smuzhiyun dev_err(&ep->dev->pdev->dev, "%s: error=%d\n", __func__, ret);
1121*4882a593Smuzhiyun return ret;
1122*4882a593Smuzhiyun }
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun static inline void
dma_done(struct net2280_ep * ep,struct net2280_request * req,u32 dmacount,int status)1125*4882a593Smuzhiyun dma_done(struct net2280_ep *ep, struct net2280_request *req, u32 dmacount,
1126*4882a593Smuzhiyun int status)
1127*4882a593Smuzhiyun {
1128*4882a593Smuzhiyun req->req.actual = req->req.length - (DMA_BYTE_COUNT_MASK & dmacount);
1129*4882a593Smuzhiyun done(ep, req, status);
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun
scan_dma_completions(struct net2280_ep * ep)1132*4882a593Smuzhiyun static int scan_dma_completions(struct net2280_ep *ep)
1133*4882a593Smuzhiyun {
1134*4882a593Smuzhiyun int num_completed = 0;
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun /* only look at descriptors that were "naturally" retired,
1137*4882a593Smuzhiyun * so fifo and list head state won't matter
1138*4882a593Smuzhiyun */
1139*4882a593Smuzhiyun while (!list_empty(&ep->queue)) {
1140*4882a593Smuzhiyun struct net2280_request *req;
1141*4882a593Smuzhiyun u32 req_dma_count;
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun req = list_entry(ep->queue.next,
1144*4882a593Smuzhiyun struct net2280_request, queue);
1145*4882a593Smuzhiyun if (!req->valid)
1146*4882a593Smuzhiyun break;
1147*4882a593Smuzhiyun rmb();
1148*4882a593Smuzhiyun req_dma_count = le32_to_cpup(&req->td->dmacount);
1149*4882a593Smuzhiyun if ((req_dma_count & BIT(VALID_BIT)) != 0)
1150*4882a593Smuzhiyun break;
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun /* SHORT_PACKET_TRANSFERRED_INTERRUPT handles "usb-short"
1153*4882a593Smuzhiyun * cases where DMA must be aborted; this code handles
1154*4882a593Smuzhiyun * all non-abort DMA completions.
1155*4882a593Smuzhiyun */
1156*4882a593Smuzhiyun if (unlikely(req->td->dmadesc == 0)) {
1157*4882a593Smuzhiyun /* paranoia */
1158*4882a593Smuzhiyun u32 const ep_dmacount = readl(&ep->dma->dmacount);
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun if (ep_dmacount & DMA_BYTE_COUNT_MASK)
1161*4882a593Smuzhiyun break;
1162*4882a593Smuzhiyun /* single transfer mode */
1163*4882a593Smuzhiyun dma_done(ep, req, req_dma_count, 0);
1164*4882a593Smuzhiyun num_completed++;
1165*4882a593Smuzhiyun break;
1166*4882a593Smuzhiyun } else if (!ep->is_in &&
1167*4882a593Smuzhiyun (req->req.length % ep->ep.maxpacket) &&
1168*4882a593Smuzhiyun !(ep->dev->quirks & PLX_PCIE)) {
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun u32 const ep_stat = readl(&ep->regs->ep_stat);
1171*4882a593Smuzhiyun /* AVOID TROUBLE HERE by not issuing short reads from
1172*4882a593Smuzhiyun * your gadget driver. That helps avoids errata 0121,
1173*4882a593Smuzhiyun * 0122, and 0124; not all cases trigger the warning.
1174*4882a593Smuzhiyun */
1175*4882a593Smuzhiyun if ((ep_stat & BIT(NAK_OUT_PACKETS)) == 0) {
1176*4882a593Smuzhiyun ep_warn(ep->dev, "%s lost packet sync!\n",
1177*4882a593Smuzhiyun ep->ep.name);
1178*4882a593Smuzhiyun req->req.status = -EOVERFLOW;
1179*4882a593Smuzhiyun } else {
1180*4882a593Smuzhiyun u32 const ep_avail = readl(&ep->regs->ep_avail);
1181*4882a593Smuzhiyun if (ep_avail) {
1182*4882a593Smuzhiyun /* fifo gets flushed later */
1183*4882a593Smuzhiyun ep->out_overflow = 1;
1184*4882a593Smuzhiyun ep_dbg(ep->dev,
1185*4882a593Smuzhiyun "%s dma, discard %d len %d\n",
1186*4882a593Smuzhiyun ep->ep.name, ep_avail,
1187*4882a593Smuzhiyun req->req.length);
1188*4882a593Smuzhiyun req->req.status = -EOVERFLOW;
1189*4882a593Smuzhiyun }
1190*4882a593Smuzhiyun }
1191*4882a593Smuzhiyun }
1192*4882a593Smuzhiyun dma_done(ep, req, req_dma_count, 0);
1193*4882a593Smuzhiyun num_completed++;
1194*4882a593Smuzhiyun }
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun return num_completed;
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun
restart_dma(struct net2280_ep * ep)1199*4882a593Smuzhiyun static void restart_dma(struct net2280_ep *ep)
1200*4882a593Smuzhiyun {
1201*4882a593Smuzhiyun struct net2280_request *req;
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun if (ep->stopped)
1204*4882a593Smuzhiyun return;
1205*4882a593Smuzhiyun req = list_entry(ep->queue.next, struct net2280_request, queue);
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun start_dma(ep, req);
1208*4882a593Smuzhiyun }
1209*4882a593Smuzhiyun
abort_dma(struct net2280_ep * ep)1210*4882a593Smuzhiyun static void abort_dma(struct net2280_ep *ep)
1211*4882a593Smuzhiyun {
1212*4882a593Smuzhiyun /* abort the current transfer */
1213*4882a593Smuzhiyun if (likely(!list_empty(&ep->queue))) {
1214*4882a593Smuzhiyun /* FIXME work around errata 0121, 0122, 0124 */
1215*4882a593Smuzhiyun writel(BIT(DMA_ABORT), &ep->dma->dmastat);
1216*4882a593Smuzhiyun spin_stop_dma(ep->dma);
1217*4882a593Smuzhiyun } else
1218*4882a593Smuzhiyun stop_dma(ep->dma);
1219*4882a593Smuzhiyun scan_dma_completions(ep);
1220*4882a593Smuzhiyun }
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun /* dequeue ALL requests */
nuke(struct net2280_ep * ep)1223*4882a593Smuzhiyun static void nuke(struct net2280_ep *ep)
1224*4882a593Smuzhiyun {
1225*4882a593Smuzhiyun struct net2280_request *req;
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun /* called with spinlock held */
1228*4882a593Smuzhiyun ep->stopped = 1;
1229*4882a593Smuzhiyun if (ep->dma)
1230*4882a593Smuzhiyun abort_dma(ep);
1231*4882a593Smuzhiyun while (!list_empty(&ep->queue)) {
1232*4882a593Smuzhiyun req = list_entry(ep->queue.next,
1233*4882a593Smuzhiyun struct net2280_request,
1234*4882a593Smuzhiyun queue);
1235*4882a593Smuzhiyun done(ep, req, -ESHUTDOWN);
1236*4882a593Smuzhiyun }
1237*4882a593Smuzhiyun }
1238*4882a593Smuzhiyun
1239*4882a593Smuzhiyun /* dequeue JUST ONE request */
net2280_dequeue(struct usb_ep * _ep,struct usb_request * _req)1240*4882a593Smuzhiyun static int net2280_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1241*4882a593Smuzhiyun {
1242*4882a593Smuzhiyun struct net2280_ep *ep;
1243*4882a593Smuzhiyun struct net2280_request *req;
1244*4882a593Smuzhiyun unsigned long flags;
1245*4882a593Smuzhiyun u32 dmactl;
1246*4882a593Smuzhiyun int stopped;
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun ep = container_of(_ep, struct net2280_ep, ep);
1249*4882a593Smuzhiyun if (!_ep || (!ep->desc && ep->num != 0) || !_req) {
1250*4882a593Smuzhiyun pr_err("%s: Invalid ep=%p or ep->desc or req=%p\n",
1251*4882a593Smuzhiyun __func__, _ep, _req);
1252*4882a593Smuzhiyun return -EINVAL;
1253*4882a593Smuzhiyun }
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun spin_lock_irqsave(&ep->dev->lock, flags);
1256*4882a593Smuzhiyun stopped = ep->stopped;
1257*4882a593Smuzhiyun
1258*4882a593Smuzhiyun /* quiesce dma while we patch the queue */
1259*4882a593Smuzhiyun dmactl = 0;
1260*4882a593Smuzhiyun ep->stopped = 1;
1261*4882a593Smuzhiyun if (ep->dma) {
1262*4882a593Smuzhiyun dmactl = readl(&ep->dma->dmactl);
1263*4882a593Smuzhiyun /* WARNING erratum 0127 may kick in ... */
1264*4882a593Smuzhiyun stop_dma(ep->dma);
1265*4882a593Smuzhiyun scan_dma_completions(ep);
1266*4882a593Smuzhiyun }
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun /* make sure it's still queued on this endpoint */
1269*4882a593Smuzhiyun list_for_each_entry(req, &ep->queue, queue) {
1270*4882a593Smuzhiyun if (&req->req == _req)
1271*4882a593Smuzhiyun break;
1272*4882a593Smuzhiyun }
1273*4882a593Smuzhiyun if (&req->req != _req) {
1274*4882a593Smuzhiyun ep->stopped = stopped;
1275*4882a593Smuzhiyun spin_unlock_irqrestore(&ep->dev->lock, flags);
1276*4882a593Smuzhiyun ep_dbg(ep->dev, "%s: Request mismatch\n", __func__);
1277*4882a593Smuzhiyun return -EINVAL;
1278*4882a593Smuzhiyun }
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun /* queue head may be partially complete. */
1281*4882a593Smuzhiyun if (ep->queue.next == &req->queue) {
1282*4882a593Smuzhiyun if (ep->dma) {
1283*4882a593Smuzhiyun ep_dbg(ep->dev, "unlink (%s) dma\n", _ep->name);
1284*4882a593Smuzhiyun _req->status = -ECONNRESET;
1285*4882a593Smuzhiyun abort_dma(ep);
1286*4882a593Smuzhiyun if (likely(ep->queue.next == &req->queue)) {
1287*4882a593Smuzhiyun /* NOTE: misreports single-transfer mode*/
1288*4882a593Smuzhiyun req->td->dmacount = 0; /* invalidate */
1289*4882a593Smuzhiyun dma_done(ep, req,
1290*4882a593Smuzhiyun readl(&ep->dma->dmacount),
1291*4882a593Smuzhiyun -ECONNRESET);
1292*4882a593Smuzhiyun }
1293*4882a593Smuzhiyun } else {
1294*4882a593Smuzhiyun ep_dbg(ep->dev, "unlink (%s) pio\n", _ep->name);
1295*4882a593Smuzhiyun done(ep, req, -ECONNRESET);
1296*4882a593Smuzhiyun }
1297*4882a593Smuzhiyun req = NULL;
1298*4882a593Smuzhiyun }
1299*4882a593Smuzhiyun
1300*4882a593Smuzhiyun if (req)
1301*4882a593Smuzhiyun done(ep, req, -ECONNRESET);
1302*4882a593Smuzhiyun ep->stopped = stopped;
1303*4882a593Smuzhiyun
1304*4882a593Smuzhiyun if (ep->dma) {
1305*4882a593Smuzhiyun /* turn off dma on inactive queues */
1306*4882a593Smuzhiyun if (list_empty(&ep->queue))
1307*4882a593Smuzhiyun stop_dma(ep->dma);
1308*4882a593Smuzhiyun else if (!ep->stopped) {
1309*4882a593Smuzhiyun /* resume current request, or start new one */
1310*4882a593Smuzhiyun if (req)
1311*4882a593Smuzhiyun writel(dmactl, &ep->dma->dmactl);
1312*4882a593Smuzhiyun else
1313*4882a593Smuzhiyun start_dma(ep, list_entry(ep->queue.next,
1314*4882a593Smuzhiyun struct net2280_request, queue));
1315*4882a593Smuzhiyun }
1316*4882a593Smuzhiyun }
1317*4882a593Smuzhiyun
1318*4882a593Smuzhiyun spin_unlock_irqrestore(&ep->dev->lock, flags);
1319*4882a593Smuzhiyun return 0;
1320*4882a593Smuzhiyun }
1321*4882a593Smuzhiyun
1322*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
1323*4882a593Smuzhiyun
1324*4882a593Smuzhiyun static int net2280_fifo_status(struct usb_ep *_ep);
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun static int
net2280_set_halt_and_wedge(struct usb_ep * _ep,int value,int wedged)1327*4882a593Smuzhiyun net2280_set_halt_and_wedge(struct usb_ep *_ep, int value, int wedged)
1328*4882a593Smuzhiyun {
1329*4882a593Smuzhiyun struct net2280_ep *ep;
1330*4882a593Smuzhiyun unsigned long flags;
1331*4882a593Smuzhiyun int retval = 0;
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun ep = container_of(_ep, struct net2280_ep, ep);
1334*4882a593Smuzhiyun if (!_ep || (!ep->desc && ep->num != 0)) {
1335*4882a593Smuzhiyun pr_err("%s: Invalid ep=%p or ep->desc\n", __func__, _ep);
1336*4882a593Smuzhiyun return -EINVAL;
1337*4882a593Smuzhiyun }
1338*4882a593Smuzhiyun if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN) {
1339*4882a593Smuzhiyun retval = -ESHUTDOWN;
1340*4882a593Smuzhiyun goto print_err;
1341*4882a593Smuzhiyun }
1342*4882a593Smuzhiyun if (ep->desc /* not ep0 */ && (ep->desc->bmAttributes & 0x03)
1343*4882a593Smuzhiyun == USB_ENDPOINT_XFER_ISOC) {
1344*4882a593Smuzhiyun retval = -EINVAL;
1345*4882a593Smuzhiyun goto print_err;
1346*4882a593Smuzhiyun }
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun spin_lock_irqsave(&ep->dev->lock, flags);
1349*4882a593Smuzhiyun if (!list_empty(&ep->queue)) {
1350*4882a593Smuzhiyun retval = -EAGAIN;
1351*4882a593Smuzhiyun goto print_unlock;
1352*4882a593Smuzhiyun } else if (ep->is_in && value && net2280_fifo_status(_ep) != 0) {
1353*4882a593Smuzhiyun retval = -EAGAIN;
1354*4882a593Smuzhiyun goto print_unlock;
1355*4882a593Smuzhiyun } else {
1356*4882a593Smuzhiyun ep_vdbg(ep->dev, "%s %s %s\n", _ep->name,
1357*4882a593Smuzhiyun value ? "set" : "clear",
1358*4882a593Smuzhiyun wedged ? "wedge" : "halt");
1359*4882a593Smuzhiyun /* set/clear, then synch memory views with the device */
1360*4882a593Smuzhiyun if (value) {
1361*4882a593Smuzhiyun if (ep->num == 0)
1362*4882a593Smuzhiyun ep->dev->protocol_stall = 1;
1363*4882a593Smuzhiyun else
1364*4882a593Smuzhiyun set_halt(ep);
1365*4882a593Smuzhiyun if (wedged)
1366*4882a593Smuzhiyun ep->wedged = 1;
1367*4882a593Smuzhiyun } else {
1368*4882a593Smuzhiyun clear_halt(ep);
1369*4882a593Smuzhiyun if (ep->dev->quirks & PLX_PCIE &&
1370*4882a593Smuzhiyun !list_empty(&ep->queue) && ep->td_dma)
1371*4882a593Smuzhiyun restart_dma(ep);
1372*4882a593Smuzhiyun ep->wedged = 0;
1373*4882a593Smuzhiyun }
1374*4882a593Smuzhiyun (void) readl(&ep->regs->ep_rsp);
1375*4882a593Smuzhiyun }
1376*4882a593Smuzhiyun spin_unlock_irqrestore(&ep->dev->lock, flags);
1377*4882a593Smuzhiyun
1378*4882a593Smuzhiyun return retval;
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun print_unlock:
1381*4882a593Smuzhiyun spin_unlock_irqrestore(&ep->dev->lock, flags);
1382*4882a593Smuzhiyun print_err:
1383*4882a593Smuzhiyun dev_err(&ep->dev->pdev->dev, "%s: error=%d\n", __func__, retval);
1384*4882a593Smuzhiyun return retval;
1385*4882a593Smuzhiyun }
1386*4882a593Smuzhiyun
net2280_set_halt(struct usb_ep * _ep,int value)1387*4882a593Smuzhiyun static int net2280_set_halt(struct usb_ep *_ep, int value)
1388*4882a593Smuzhiyun {
1389*4882a593Smuzhiyun return net2280_set_halt_and_wedge(_ep, value, 0);
1390*4882a593Smuzhiyun }
1391*4882a593Smuzhiyun
net2280_set_wedge(struct usb_ep * _ep)1392*4882a593Smuzhiyun static int net2280_set_wedge(struct usb_ep *_ep)
1393*4882a593Smuzhiyun {
1394*4882a593Smuzhiyun if (!_ep || _ep->name == ep0name) {
1395*4882a593Smuzhiyun pr_err("%s: Invalid ep=%p or ep0\n", __func__, _ep);
1396*4882a593Smuzhiyun return -EINVAL;
1397*4882a593Smuzhiyun }
1398*4882a593Smuzhiyun return net2280_set_halt_and_wedge(_ep, 1, 1);
1399*4882a593Smuzhiyun }
1400*4882a593Smuzhiyun
net2280_fifo_status(struct usb_ep * _ep)1401*4882a593Smuzhiyun static int net2280_fifo_status(struct usb_ep *_ep)
1402*4882a593Smuzhiyun {
1403*4882a593Smuzhiyun struct net2280_ep *ep;
1404*4882a593Smuzhiyun u32 avail;
1405*4882a593Smuzhiyun
1406*4882a593Smuzhiyun ep = container_of(_ep, struct net2280_ep, ep);
1407*4882a593Smuzhiyun if (!_ep || (!ep->desc && ep->num != 0)) {
1408*4882a593Smuzhiyun pr_err("%s: Invalid ep=%p or ep->desc\n", __func__, _ep);
1409*4882a593Smuzhiyun return -ENODEV;
1410*4882a593Smuzhiyun }
1411*4882a593Smuzhiyun if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN) {
1412*4882a593Smuzhiyun dev_err(&ep->dev->pdev->dev,
1413*4882a593Smuzhiyun "%s: Invalid driver=%p or speed=%d\n",
1414*4882a593Smuzhiyun __func__, ep->dev->driver, ep->dev->gadget.speed);
1415*4882a593Smuzhiyun return -ESHUTDOWN;
1416*4882a593Smuzhiyun }
1417*4882a593Smuzhiyun
1418*4882a593Smuzhiyun avail = readl(&ep->regs->ep_avail) & (BIT(12) - 1);
1419*4882a593Smuzhiyun if (avail > ep->fifo_size) {
1420*4882a593Smuzhiyun dev_err(&ep->dev->pdev->dev, "%s: Fifo overflow\n", __func__);
1421*4882a593Smuzhiyun return -EOVERFLOW;
1422*4882a593Smuzhiyun }
1423*4882a593Smuzhiyun if (ep->is_in)
1424*4882a593Smuzhiyun avail = ep->fifo_size - avail;
1425*4882a593Smuzhiyun return avail;
1426*4882a593Smuzhiyun }
1427*4882a593Smuzhiyun
net2280_fifo_flush(struct usb_ep * _ep)1428*4882a593Smuzhiyun static void net2280_fifo_flush(struct usb_ep *_ep)
1429*4882a593Smuzhiyun {
1430*4882a593Smuzhiyun struct net2280_ep *ep;
1431*4882a593Smuzhiyun
1432*4882a593Smuzhiyun ep = container_of(_ep, struct net2280_ep, ep);
1433*4882a593Smuzhiyun if (!_ep || (!ep->desc && ep->num != 0)) {
1434*4882a593Smuzhiyun pr_err("%s: Invalid ep=%p or ep->desc\n", __func__, _ep);
1435*4882a593Smuzhiyun return;
1436*4882a593Smuzhiyun }
1437*4882a593Smuzhiyun if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN) {
1438*4882a593Smuzhiyun dev_err(&ep->dev->pdev->dev,
1439*4882a593Smuzhiyun "%s: Invalid driver=%p or speed=%d\n",
1440*4882a593Smuzhiyun __func__, ep->dev->driver, ep->dev->gadget.speed);
1441*4882a593Smuzhiyun return;
1442*4882a593Smuzhiyun }
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat);
1445*4882a593Smuzhiyun (void) readl(&ep->regs->ep_rsp);
1446*4882a593Smuzhiyun }
1447*4882a593Smuzhiyun
1448*4882a593Smuzhiyun static const struct usb_ep_ops net2280_ep_ops = {
1449*4882a593Smuzhiyun .enable = net2280_enable,
1450*4882a593Smuzhiyun .disable = net2280_disable,
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun .alloc_request = net2280_alloc_request,
1453*4882a593Smuzhiyun .free_request = net2280_free_request,
1454*4882a593Smuzhiyun
1455*4882a593Smuzhiyun .queue = net2280_queue,
1456*4882a593Smuzhiyun .dequeue = net2280_dequeue,
1457*4882a593Smuzhiyun
1458*4882a593Smuzhiyun .set_halt = net2280_set_halt,
1459*4882a593Smuzhiyun .set_wedge = net2280_set_wedge,
1460*4882a593Smuzhiyun .fifo_status = net2280_fifo_status,
1461*4882a593Smuzhiyun .fifo_flush = net2280_fifo_flush,
1462*4882a593Smuzhiyun };
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
1465*4882a593Smuzhiyun
net2280_get_frame(struct usb_gadget * _gadget)1466*4882a593Smuzhiyun static int net2280_get_frame(struct usb_gadget *_gadget)
1467*4882a593Smuzhiyun {
1468*4882a593Smuzhiyun struct net2280 *dev;
1469*4882a593Smuzhiyun unsigned long flags;
1470*4882a593Smuzhiyun u16 retval;
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun if (!_gadget)
1473*4882a593Smuzhiyun return -ENODEV;
1474*4882a593Smuzhiyun dev = container_of(_gadget, struct net2280, gadget);
1475*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
1476*4882a593Smuzhiyun retval = get_idx_reg(dev->regs, REG_FRAME) & 0x03ff;
1477*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
1478*4882a593Smuzhiyun return retval;
1479*4882a593Smuzhiyun }
1480*4882a593Smuzhiyun
net2280_wakeup(struct usb_gadget * _gadget)1481*4882a593Smuzhiyun static int net2280_wakeup(struct usb_gadget *_gadget)
1482*4882a593Smuzhiyun {
1483*4882a593Smuzhiyun struct net2280 *dev;
1484*4882a593Smuzhiyun u32 tmp;
1485*4882a593Smuzhiyun unsigned long flags;
1486*4882a593Smuzhiyun
1487*4882a593Smuzhiyun if (!_gadget)
1488*4882a593Smuzhiyun return 0;
1489*4882a593Smuzhiyun dev = container_of(_gadget, struct net2280, gadget);
1490*4882a593Smuzhiyun
1491*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
1492*4882a593Smuzhiyun tmp = readl(&dev->usb->usbctl);
1493*4882a593Smuzhiyun if (tmp & BIT(DEVICE_REMOTE_WAKEUP_ENABLE))
1494*4882a593Smuzhiyun writel(BIT(GENERATE_RESUME), &dev->usb->usbstat);
1495*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun /* pci writes may still be posted */
1498*4882a593Smuzhiyun return 0;
1499*4882a593Smuzhiyun }
1500*4882a593Smuzhiyun
net2280_set_selfpowered(struct usb_gadget * _gadget,int value)1501*4882a593Smuzhiyun static int net2280_set_selfpowered(struct usb_gadget *_gadget, int value)
1502*4882a593Smuzhiyun {
1503*4882a593Smuzhiyun struct net2280 *dev;
1504*4882a593Smuzhiyun u32 tmp;
1505*4882a593Smuzhiyun unsigned long flags;
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun if (!_gadget)
1508*4882a593Smuzhiyun return 0;
1509*4882a593Smuzhiyun dev = container_of(_gadget, struct net2280, gadget);
1510*4882a593Smuzhiyun
1511*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
1512*4882a593Smuzhiyun tmp = readl(&dev->usb->usbctl);
1513*4882a593Smuzhiyun if (value) {
1514*4882a593Smuzhiyun tmp |= BIT(SELF_POWERED_STATUS);
1515*4882a593Smuzhiyun _gadget->is_selfpowered = 1;
1516*4882a593Smuzhiyun } else {
1517*4882a593Smuzhiyun tmp &= ~BIT(SELF_POWERED_STATUS);
1518*4882a593Smuzhiyun _gadget->is_selfpowered = 0;
1519*4882a593Smuzhiyun }
1520*4882a593Smuzhiyun writel(tmp, &dev->usb->usbctl);
1521*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
1522*4882a593Smuzhiyun
1523*4882a593Smuzhiyun return 0;
1524*4882a593Smuzhiyun }
1525*4882a593Smuzhiyun
net2280_pullup(struct usb_gadget * _gadget,int is_on)1526*4882a593Smuzhiyun static int net2280_pullup(struct usb_gadget *_gadget, int is_on)
1527*4882a593Smuzhiyun {
1528*4882a593Smuzhiyun struct net2280 *dev;
1529*4882a593Smuzhiyun u32 tmp;
1530*4882a593Smuzhiyun unsigned long flags;
1531*4882a593Smuzhiyun
1532*4882a593Smuzhiyun if (!_gadget)
1533*4882a593Smuzhiyun return -ENODEV;
1534*4882a593Smuzhiyun dev = container_of(_gadget, struct net2280, gadget);
1535*4882a593Smuzhiyun
1536*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
1537*4882a593Smuzhiyun tmp = readl(&dev->usb->usbctl);
1538*4882a593Smuzhiyun dev->softconnect = (is_on != 0);
1539*4882a593Smuzhiyun if (is_on) {
1540*4882a593Smuzhiyun ep0_start(dev);
1541*4882a593Smuzhiyun writel(tmp | BIT(USB_DETECT_ENABLE), &dev->usb->usbctl);
1542*4882a593Smuzhiyun } else {
1543*4882a593Smuzhiyun writel(tmp & ~BIT(USB_DETECT_ENABLE), &dev->usb->usbctl);
1544*4882a593Smuzhiyun stop_activity(dev, NULL);
1545*4882a593Smuzhiyun }
1546*4882a593Smuzhiyun
1547*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
1548*4882a593Smuzhiyun
1549*4882a593Smuzhiyun return 0;
1550*4882a593Smuzhiyun }
1551*4882a593Smuzhiyun
net2280_match_ep(struct usb_gadget * _gadget,struct usb_endpoint_descriptor * desc,struct usb_ss_ep_comp_descriptor * ep_comp)1552*4882a593Smuzhiyun static struct usb_ep *net2280_match_ep(struct usb_gadget *_gadget,
1553*4882a593Smuzhiyun struct usb_endpoint_descriptor *desc,
1554*4882a593Smuzhiyun struct usb_ss_ep_comp_descriptor *ep_comp)
1555*4882a593Smuzhiyun {
1556*4882a593Smuzhiyun char name[8];
1557*4882a593Smuzhiyun struct usb_ep *ep;
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT) {
1560*4882a593Smuzhiyun /* ep-e, ep-f are PIO with only 64 byte fifos */
1561*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep-e");
1562*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1563*4882a593Smuzhiyun return ep;
1564*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep-f");
1565*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1566*4882a593Smuzhiyun return ep;
1567*4882a593Smuzhiyun }
1568*4882a593Smuzhiyun
1569*4882a593Smuzhiyun /* USB3380: Only first four endpoints have DMA channels. Allocate
1570*4882a593Smuzhiyun * slower interrupt endpoints from PIO hw endpoints, to allow bulk/isoc
1571*4882a593Smuzhiyun * endpoints use DMA hw endpoints.
1572*4882a593Smuzhiyun */
1573*4882a593Smuzhiyun if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
1574*4882a593Smuzhiyun usb_endpoint_dir_in(desc)) {
1575*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep2in");
1576*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1577*4882a593Smuzhiyun return ep;
1578*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep4in");
1579*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1580*4882a593Smuzhiyun return ep;
1581*4882a593Smuzhiyun } else if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
1582*4882a593Smuzhiyun !usb_endpoint_dir_in(desc)) {
1583*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep1out");
1584*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1585*4882a593Smuzhiyun return ep;
1586*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep3out");
1587*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1588*4882a593Smuzhiyun return ep;
1589*4882a593Smuzhiyun } else if (usb_endpoint_type(desc) != USB_ENDPOINT_XFER_BULK &&
1590*4882a593Smuzhiyun usb_endpoint_dir_in(desc)) {
1591*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep1in");
1592*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1593*4882a593Smuzhiyun return ep;
1594*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep3in");
1595*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1596*4882a593Smuzhiyun return ep;
1597*4882a593Smuzhiyun } else if (usb_endpoint_type(desc) != USB_ENDPOINT_XFER_BULK &&
1598*4882a593Smuzhiyun !usb_endpoint_dir_in(desc)) {
1599*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep2out");
1600*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1601*4882a593Smuzhiyun return ep;
1602*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, "ep4out");
1603*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1604*4882a593Smuzhiyun return ep;
1605*4882a593Smuzhiyun }
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun /* USB3380: use same address for usb and hardware endpoints */
1608*4882a593Smuzhiyun snprintf(name, sizeof(name), "ep%d%s", usb_endpoint_num(desc),
1609*4882a593Smuzhiyun usb_endpoint_dir_in(desc) ? "in" : "out");
1610*4882a593Smuzhiyun ep = gadget_find_ep_by_name(_gadget, name);
1611*4882a593Smuzhiyun if (ep && usb_gadget_ep_match_desc(_gadget, ep, desc, ep_comp))
1612*4882a593Smuzhiyun return ep;
1613*4882a593Smuzhiyun
1614*4882a593Smuzhiyun return NULL;
1615*4882a593Smuzhiyun }
1616*4882a593Smuzhiyun
1617*4882a593Smuzhiyun static int net2280_start(struct usb_gadget *_gadget,
1618*4882a593Smuzhiyun struct usb_gadget_driver *driver);
1619*4882a593Smuzhiyun static int net2280_stop(struct usb_gadget *_gadget);
1620*4882a593Smuzhiyun
1621*4882a593Smuzhiyun static const struct usb_gadget_ops net2280_ops = {
1622*4882a593Smuzhiyun .get_frame = net2280_get_frame,
1623*4882a593Smuzhiyun .wakeup = net2280_wakeup,
1624*4882a593Smuzhiyun .set_selfpowered = net2280_set_selfpowered,
1625*4882a593Smuzhiyun .pullup = net2280_pullup,
1626*4882a593Smuzhiyun .udc_start = net2280_start,
1627*4882a593Smuzhiyun .udc_stop = net2280_stop,
1628*4882a593Smuzhiyun .match_ep = net2280_match_ep,
1629*4882a593Smuzhiyun };
1630*4882a593Smuzhiyun
1631*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
1632*4882a593Smuzhiyun
1633*4882a593Smuzhiyun #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1634*4882a593Smuzhiyun
1635*4882a593Smuzhiyun /* FIXME move these into procfs, and use seq_file.
1636*4882a593Smuzhiyun * Sysfs _still_ doesn't behave for arbitrarily sized files,
1637*4882a593Smuzhiyun * and also doesn't help products using this with 2.4 kernels.
1638*4882a593Smuzhiyun */
1639*4882a593Smuzhiyun
1640*4882a593Smuzhiyun /* "function" sysfs attribute */
function_show(struct device * _dev,struct device_attribute * attr,char * buf)1641*4882a593Smuzhiyun static ssize_t function_show(struct device *_dev, struct device_attribute *attr,
1642*4882a593Smuzhiyun char *buf)
1643*4882a593Smuzhiyun {
1644*4882a593Smuzhiyun struct net2280 *dev = dev_get_drvdata(_dev);
1645*4882a593Smuzhiyun
1646*4882a593Smuzhiyun if (!dev->driver || !dev->driver->function ||
1647*4882a593Smuzhiyun strlen(dev->driver->function) > PAGE_SIZE)
1648*4882a593Smuzhiyun return 0;
1649*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
1650*4882a593Smuzhiyun }
1651*4882a593Smuzhiyun static DEVICE_ATTR_RO(function);
1652*4882a593Smuzhiyun
registers_show(struct device * _dev,struct device_attribute * attr,char * buf)1653*4882a593Smuzhiyun static ssize_t registers_show(struct device *_dev,
1654*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
1655*4882a593Smuzhiyun {
1656*4882a593Smuzhiyun struct net2280 *dev;
1657*4882a593Smuzhiyun char *next;
1658*4882a593Smuzhiyun unsigned size, t;
1659*4882a593Smuzhiyun unsigned long flags;
1660*4882a593Smuzhiyun int i;
1661*4882a593Smuzhiyun u32 t1, t2;
1662*4882a593Smuzhiyun const char *s;
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun dev = dev_get_drvdata(_dev);
1665*4882a593Smuzhiyun next = buf;
1666*4882a593Smuzhiyun size = PAGE_SIZE;
1667*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
1668*4882a593Smuzhiyun
1669*4882a593Smuzhiyun if (dev->driver)
1670*4882a593Smuzhiyun s = dev->driver->driver.name;
1671*4882a593Smuzhiyun else
1672*4882a593Smuzhiyun s = "(none)";
1673*4882a593Smuzhiyun
1674*4882a593Smuzhiyun /* Main Control Registers */
1675*4882a593Smuzhiyun t = scnprintf(next, size, "%s version " DRIVER_VERSION
1676*4882a593Smuzhiyun ", chiprev %04x\n\n"
1677*4882a593Smuzhiyun "devinit %03x fifoctl %08x gadget '%s'\n"
1678*4882a593Smuzhiyun "pci irqenb0 %02x irqenb1 %08x "
1679*4882a593Smuzhiyun "irqstat0 %04x irqstat1 %08x\n",
1680*4882a593Smuzhiyun driver_name, dev->chiprev,
1681*4882a593Smuzhiyun readl(&dev->regs->devinit),
1682*4882a593Smuzhiyun readl(&dev->regs->fifoctl),
1683*4882a593Smuzhiyun s,
1684*4882a593Smuzhiyun readl(&dev->regs->pciirqenb0),
1685*4882a593Smuzhiyun readl(&dev->regs->pciirqenb1),
1686*4882a593Smuzhiyun readl(&dev->regs->irqstat0),
1687*4882a593Smuzhiyun readl(&dev->regs->irqstat1));
1688*4882a593Smuzhiyun size -= t;
1689*4882a593Smuzhiyun next += t;
1690*4882a593Smuzhiyun
1691*4882a593Smuzhiyun /* USB Control Registers */
1692*4882a593Smuzhiyun t1 = readl(&dev->usb->usbctl);
1693*4882a593Smuzhiyun t2 = readl(&dev->usb->usbstat);
1694*4882a593Smuzhiyun if (t1 & BIT(VBUS_PIN)) {
1695*4882a593Smuzhiyun if (t2 & BIT(HIGH_SPEED))
1696*4882a593Smuzhiyun s = "high speed";
1697*4882a593Smuzhiyun else if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1698*4882a593Smuzhiyun s = "powered";
1699*4882a593Smuzhiyun else
1700*4882a593Smuzhiyun s = "full speed";
1701*4882a593Smuzhiyun /* full speed bit (6) not working?? */
1702*4882a593Smuzhiyun } else
1703*4882a593Smuzhiyun s = "not attached";
1704*4882a593Smuzhiyun t = scnprintf(next, size,
1705*4882a593Smuzhiyun "stdrsp %08x usbctl %08x usbstat %08x "
1706*4882a593Smuzhiyun "addr 0x%02x (%s)\n",
1707*4882a593Smuzhiyun readl(&dev->usb->stdrsp), t1, t2,
1708*4882a593Smuzhiyun readl(&dev->usb->ouraddr), s);
1709*4882a593Smuzhiyun size -= t;
1710*4882a593Smuzhiyun next += t;
1711*4882a593Smuzhiyun
1712*4882a593Smuzhiyun /* PCI Master Control Registers */
1713*4882a593Smuzhiyun
1714*4882a593Smuzhiyun /* DMA Control Registers */
1715*4882a593Smuzhiyun
1716*4882a593Smuzhiyun /* Configurable EP Control Registers */
1717*4882a593Smuzhiyun for (i = 0; i < dev->n_ep; i++) {
1718*4882a593Smuzhiyun struct net2280_ep *ep;
1719*4882a593Smuzhiyun
1720*4882a593Smuzhiyun ep = &dev->ep[i];
1721*4882a593Smuzhiyun if (i && !ep->desc)
1722*4882a593Smuzhiyun continue;
1723*4882a593Smuzhiyun
1724*4882a593Smuzhiyun t1 = readl(&ep->cfg->ep_cfg);
1725*4882a593Smuzhiyun t2 = readl(&ep->regs->ep_rsp) & 0xff;
1726*4882a593Smuzhiyun t = scnprintf(next, size,
1727*4882a593Smuzhiyun "\n%s\tcfg %05x rsp (%02x) %s%s%s%s%s%s%s%s"
1728*4882a593Smuzhiyun "irqenb %02x\n",
1729*4882a593Smuzhiyun ep->ep.name, t1, t2,
1730*4882a593Smuzhiyun (t2 & BIT(CLEAR_NAK_OUT_PACKETS))
1731*4882a593Smuzhiyun ? "NAK " : "",
1732*4882a593Smuzhiyun (t2 & BIT(CLEAR_EP_HIDE_STATUS_PHASE))
1733*4882a593Smuzhiyun ? "hide " : "",
1734*4882a593Smuzhiyun (t2 & BIT(CLEAR_EP_FORCE_CRC_ERROR))
1735*4882a593Smuzhiyun ? "CRC " : "",
1736*4882a593Smuzhiyun (t2 & BIT(CLEAR_INTERRUPT_MODE))
1737*4882a593Smuzhiyun ? "interrupt " : "",
1738*4882a593Smuzhiyun (t2 & BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE))
1739*4882a593Smuzhiyun ? "status " : "",
1740*4882a593Smuzhiyun (t2 & BIT(CLEAR_NAK_OUT_PACKETS_MODE))
1741*4882a593Smuzhiyun ? "NAKmode " : "",
1742*4882a593Smuzhiyun (t2 & BIT(CLEAR_ENDPOINT_TOGGLE))
1743*4882a593Smuzhiyun ? "DATA1 " : "DATA0 ",
1744*4882a593Smuzhiyun (t2 & BIT(CLEAR_ENDPOINT_HALT))
1745*4882a593Smuzhiyun ? "HALT " : "",
1746*4882a593Smuzhiyun readl(&ep->regs->ep_irqenb));
1747*4882a593Smuzhiyun size -= t;
1748*4882a593Smuzhiyun next += t;
1749*4882a593Smuzhiyun
1750*4882a593Smuzhiyun t = scnprintf(next, size,
1751*4882a593Smuzhiyun "\tstat %08x avail %04x "
1752*4882a593Smuzhiyun "(ep%d%s-%s)%s\n",
1753*4882a593Smuzhiyun readl(&ep->regs->ep_stat),
1754*4882a593Smuzhiyun readl(&ep->regs->ep_avail),
1755*4882a593Smuzhiyun t1 & 0x0f, DIR_STRING(t1),
1756*4882a593Smuzhiyun type_string(t1 >> 8),
1757*4882a593Smuzhiyun ep->stopped ? "*" : "");
1758*4882a593Smuzhiyun size -= t;
1759*4882a593Smuzhiyun next += t;
1760*4882a593Smuzhiyun
1761*4882a593Smuzhiyun if (!ep->dma)
1762*4882a593Smuzhiyun continue;
1763*4882a593Smuzhiyun
1764*4882a593Smuzhiyun t = scnprintf(next, size,
1765*4882a593Smuzhiyun " dma\tctl %08x stat %08x count %08x\n"
1766*4882a593Smuzhiyun "\taddr %08x desc %08x\n",
1767*4882a593Smuzhiyun readl(&ep->dma->dmactl),
1768*4882a593Smuzhiyun readl(&ep->dma->dmastat),
1769*4882a593Smuzhiyun readl(&ep->dma->dmacount),
1770*4882a593Smuzhiyun readl(&ep->dma->dmaaddr),
1771*4882a593Smuzhiyun readl(&ep->dma->dmadesc));
1772*4882a593Smuzhiyun size -= t;
1773*4882a593Smuzhiyun next += t;
1774*4882a593Smuzhiyun
1775*4882a593Smuzhiyun }
1776*4882a593Smuzhiyun
1777*4882a593Smuzhiyun /* Indexed Registers (none yet) */
1778*4882a593Smuzhiyun
1779*4882a593Smuzhiyun /* Statistics */
1780*4882a593Smuzhiyun t = scnprintf(next, size, "\nirqs: ");
1781*4882a593Smuzhiyun size -= t;
1782*4882a593Smuzhiyun next += t;
1783*4882a593Smuzhiyun for (i = 0; i < dev->n_ep; i++) {
1784*4882a593Smuzhiyun struct net2280_ep *ep;
1785*4882a593Smuzhiyun
1786*4882a593Smuzhiyun ep = &dev->ep[i];
1787*4882a593Smuzhiyun if (i && !ep->irqs)
1788*4882a593Smuzhiyun continue;
1789*4882a593Smuzhiyun t = scnprintf(next, size, " %s/%lu", ep->ep.name, ep->irqs);
1790*4882a593Smuzhiyun size -= t;
1791*4882a593Smuzhiyun next += t;
1792*4882a593Smuzhiyun
1793*4882a593Smuzhiyun }
1794*4882a593Smuzhiyun t = scnprintf(next, size, "\n");
1795*4882a593Smuzhiyun size -= t;
1796*4882a593Smuzhiyun next += t;
1797*4882a593Smuzhiyun
1798*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
1799*4882a593Smuzhiyun
1800*4882a593Smuzhiyun return PAGE_SIZE - size;
1801*4882a593Smuzhiyun }
1802*4882a593Smuzhiyun static DEVICE_ATTR_RO(registers);
1803*4882a593Smuzhiyun
queues_show(struct device * _dev,struct device_attribute * attr,char * buf)1804*4882a593Smuzhiyun static ssize_t queues_show(struct device *_dev, struct device_attribute *attr,
1805*4882a593Smuzhiyun char *buf)
1806*4882a593Smuzhiyun {
1807*4882a593Smuzhiyun struct net2280 *dev;
1808*4882a593Smuzhiyun char *next;
1809*4882a593Smuzhiyun unsigned size;
1810*4882a593Smuzhiyun unsigned long flags;
1811*4882a593Smuzhiyun int i;
1812*4882a593Smuzhiyun
1813*4882a593Smuzhiyun dev = dev_get_drvdata(_dev);
1814*4882a593Smuzhiyun next = buf;
1815*4882a593Smuzhiyun size = PAGE_SIZE;
1816*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
1817*4882a593Smuzhiyun
1818*4882a593Smuzhiyun for (i = 0; i < dev->n_ep; i++) {
1819*4882a593Smuzhiyun struct net2280_ep *ep = &dev->ep[i];
1820*4882a593Smuzhiyun struct net2280_request *req;
1821*4882a593Smuzhiyun int t;
1822*4882a593Smuzhiyun
1823*4882a593Smuzhiyun if (i != 0) {
1824*4882a593Smuzhiyun const struct usb_endpoint_descriptor *d;
1825*4882a593Smuzhiyun
1826*4882a593Smuzhiyun d = ep->desc;
1827*4882a593Smuzhiyun if (!d)
1828*4882a593Smuzhiyun continue;
1829*4882a593Smuzhiyun t = d->bEndpointAddress;
1830*4882a593Smuzhiyun t = scnprintf(next, size,
1831*4882a593Smuzhiyun "\n%s (ep%d%s-%s) max %04x %s fifo %d\n",
1832*4882a593Smuzhiyun ep->ep.name, t & USB_ENDPOINT_NUMBER_MASK,
1833*4882a593Smuzhiyun (t & USB_DIR_IN) ? "in" : "out",
1834*4882a593Smuzhiyun type_string(d->bmAttributes),
1835*4882a593Smuzhiyun usb_endpoint_maxp(d),
1836*4882a593Smuzhiyun ep->dma ? "dma" : "pio", ep->fifo_size
1837*4882a593Smuzhiyun );
1838*4882a593Smuzhiyun } else /* ep0 should only have one transfer queued */
1839*4882a593Smuzhiyun t = scnprintf(next, size, "ep0 max 64 pio %s\n",
1840*4882a593Smuzhiyun ep->is_in ? "in" : "out");
1841*4882a593Smuzhiyun if (t <= 0 || t > size)
1842*4882a593Smuzhiyun goto done;
1843*4882a593Smuzhiyun size -= t;
1844*4882a593Smuzhiyun next += t;
1845*4882a593Smuzhiyun
1846*4882a593Smuzhiyun if (list_empty(&ep->queue)) {
1847*4882a593Smuzhiyun t = scnprintf(next, size, "\t(nothing queued)\n");
1848*4882a593Smuzhiyun if (t <= 0 || t > size)
1849*4882a593Smuzhiyun goto done;
1850*4882a593Smuzhiyun size -= t;
1851*4882a593Smuzhiyun next += t;
1852*4882a593Smuzhiyun continue;
1853*4882a593Smuzhiyun }
1854*4882a593Smuzhiyun list_for_each_entry(req, &ep->queue, queue) {
1855*4882a593Smuzhiyun if (ep->dma && req->td_dma == readl(&ep->dma->dmadesc))
1856*4882a593Smuzhiyun t = scnprintf(next, size,
1857*4882a593Smuzhiyun "\treq %p len %d/%d "
1858*4882a593Smuzhiyun "buf %p (dmacount %08x)\n",
1859*4882a593Smuzhiyun &req->req, req->req.actual,
1860*4882a593Smuzhiyun req->req.length, req->req.buf,
1861*4882a593Smuzhiyun readl(&ep->dma->dmacount));
1862*4882a593Smuzhiyun else
1863*4882a593Smuzhiyun t = scnprintf(next, size,
1864*4882a593Smuzhiyun "\treq %p len %d/%d buf %p\n",
1865*4882a593Smuzhiyun &req->req, req->req.actual,
1866*4882a593Smuzhiyun req->req.length, req->req.buf);
1867*4882a593Smuzhiyun if (t <= 0 || t > size)
1868*4882a593Smuzhiyun goto done;
1869*4882a593Smuzhiyun size -= t;
1870*4882a593Smuzhiyun next += t;
1871*4882a593Smuzhiyun
1872*4882a593Smuzhiyun if (ep->dma) {
1873*4882a593Smuzhiyun struct net2280_dma *td;
1874*4882a593Smuzhiyun
1875*4882a593Smuzhiyun td = req->td;
1876*4882a593Smuzhiyun t = scnprintf(next, size, "\t td %08x "
1877*4882a593Smuzhiyun " count %08x buf %08x desc %08x\n",
1878*4882a593Smuzhiyun (u32) req->td_dma,
1879*4882a593Smuzhiyun le32_to_cpu(td->dmacount),
1880*4882a593Smuzhiyun le32_to_cpu(td->dmaaddr),
1881*4882a593Smuzhiyun le32_to_cpu(td->dmadesc));
1882*4882a593Smuzhiyun if (t <= 0 || t > size)
1883*4882a593Smuzhiyun goto done;
1884*4882a593Smuzhiyun size -= t;
1885*4882a593Smuzhiyun next += t;
1886*4882a593Smuzhiyun }
1887*4882a593Smuzhiyun }
1888*4882a593Smuzhiyun }
1889*4882a593Smuzhiyun
1890*4882a593Smuzhiyun done:
1891*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
1892*4882a593Smuzhiyun return PAGE_SIZE - size;
1893*4882a593Smuzhiyun }
1894*4882a593Smuzhiyun static DEVICE_ATTR_RO(queues);
1895*4882a593Smuzhiyun
1896*4882a593Smuzhiyun
1897*4882a593Smuzhiyun #else
1898*4882a593Smuzhiyun
1899*4882a593Smuzhiyun #define device_create_file(a, b) (0)
1900*4882a593Smuzhiyun #define device_remove_file(a, b) do { } while (0)
1901*4882a593Smuzhiyun
1902*4882a593Smuzhiyun #endif
1903*4882a593Smuzhiyun
1904*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
1905*4882a593Smuzhiyun
1906*4882a593Smuzhiyun /* another driver-specific mode might be a request type doing dma
1907*4882a593Smuzhiyun * to/from another device fifo instead of to/from memory.
1908*4882a593Smuzhiyun */
1909*4882a593Smuzhiyun
set_fifo_mode(struct net2280 * dev,int mode)1910*4882a593Smuzhiyun static void set_fifo_mode(struct net2280 *dev, int mode)
1911*4882a593Smuzhiyun {
1912*4882a593Smuzhiyun /* keeping high bits preserves BAR2 */
1913*4882a593Smuzhiyun writel((0xffff << PCI_BASE2_RANGE) | mode, &dev->regs->fifoctl);
1914*4882a593Smuzhiyun
1915*4882a593Smuzhiyun /* always ep-{a,b,e,f} ... maybe not ep-c or ep-d */
1916*4882a593Smuzhiyun INIT_LIST_HEAD(&dev->gadget.ep_list);
1917*4882a593Smuzhiyun list_add_tail(&dev->ep[1].ep.ep_list, &dev->gadget.ep_list);
1918*4882a593Smuzhiyun list_add_tail(&dev->ep[2].ep.ep_list, &dev->gadget.ep_list);
1919*4882a593Smuzhiyun switch (mode) {
1920*4882a593Smuzhiyun case 0:
1921*4882a593Smuzhiyun list_add_tail(&dev->ep[3].ep.ep_list, &dev->gadget.ep_list);
1922*4882a593Smuzhiyun list_add_tail(&dev->ep[4].ep.ep_list, &dev->gadget.ep_list);
1923*4882a593Smuzhiyun dev->ep[1].fifo_size = dev->ep[2].fifo_size = 1024;
1924*4882a593Smuzhiyun break;
1925*4882a593Smuzhiyun case 1:
1926*4882a593Smuzhiyun dev->ep[1].fifo_size = dev->ep[2].fifo_size = 2048;
1927*4882a593Smuzhiyun break;
1928*4882a593Smuzhiyun case 2:
1929*4882a593Smuzhiyun list_add_tail(&dev->ep[3].ep.ep_list, &dev->gadget.ep_list);
1930*4882a593Smuzhiyun dev->ep[1].fifo_size = 2048;
1931*4882a593Smuzhiyun dev->ep[2].fifo_size = 1024;
1932*4882a593Smuzhiyun break;
1933*4882a593Smuzhiyun }
1934*4882a593Smuzhiyun /* fifo sizes for ep0, ep-c, ep-d, ep-e, and ep-f never change */
1935*4882a593Smuzhiyun list_add_tail(&dev->ep[5].ep.ep_list, &dev->gadget.ep_list);
1936*4882a593Smuzhiyun list_add_tail(&dev->ep[6].ep.ep_list, &dev->gadget.ep_list);
1937*4882a593Smuzhiyun }
1938*4882a593Smuzhiyun
defect7374_disable_data_eps(struct net2280 * dev)1939*4882a593Smuzhiyun static void defect7374_disable_data_eps(struct net2280 *dev)
1940*4882a593Smuzhiyun {
1941*4882a593Smuzhiyun /*
1942*4882a593Smuzhiyun * For Defect 7374, disable data EPs (and more):
1943*4882a593Smuzhiyun * - This phase undoes the earlier phase of the Defect 7374 workaround,
1944*4882a593Smuzhiyun * returing ep regs back to normal.
1945*4882a593Smuzhiyun */
1946*4882a593Smuzhiyun struct net2280_ep *ep;
1947*4882a593Smuzhiyun int i;
1948*4882a593Smuzhiyun unsigned char ep_sel;
1949*4882a593Smuzhiyun u32 tmp_reg;
1950*4882a593Smuzhiyun
1951*4882a593Smuzhiyun for (i = 1; i < 5; i++) {
1952*4882a593Smuzhiyun ep = &dev->ep[i];
1953*4882a593Smuzhiyun writel(i, &ep->cfg->ep_cfg);
1954*4882a593Smuzhiyun }
1955*4882a593Smuzhiyun
1956*4882a593Smuzhiyun /* CSROUT, CSRIN, PCIOUT, PCIIN, STATIN, RCIN */
1957*4882a593Smuzhiyun for (i = 0; i < 6; i++)
1958*4882a593Smuzhiyun writel(0, &dev->dep[i].dep_cfg);
1959*4882a593Smuzhiyun
1960*4882a593Smuzhiyun for (ep_sel = 0; ep_sel <= 21; ep_sel++) {
1961*4882a593Smuzhiyun /* Select an endpoint for subsequent operations: */
1962*4882a593Smuzhiyun tmp_reg = readl(&dev->plregs->pl_ep_ctrl);
1963*4882a593Smuzhiyun writel(((tmp_reg & ~0x1f) | ep_sel), &dev->plregs->pl_ep_ctrl);
1964*4882a593Smuzhiyun
1965*4882a593Smuzhiyun if (ep_sel < 2 || (ep_sel > 9 && ep_sel < 14) ||
1966*4882a593Smuzhiyun ep_sel == 18 || ep_sel == 20)
1967*4882a593Smuzhiyun continue;
1968*4882a593Smuzhiyun
1969*4882a593Smuzhiyun /* Change settings on some selected endpoints */
1970*4882a593Smuzhiyun tmp_reg = readl(&dev->plregs->pl_ep_cfg_4);
1971*4882a593Smuzhiyun tmp_reg &= ~BIT(NON_CTRL_IN_TOLERATE_BAD_DIR);
1972*4882a593Smuzhiyun writel(tmp_reg, &dev->plregs->pl_ep_cfg_4);
1973*4882a593Smuzhiyun tmp_reg = readl(&dev->plregs->pl_ep_ctrl);
1974*4882a593Smuzhiyun tmp_reg |= BIT(EP_INITIALIZED);
1975*4882a593Smuzhiyun writel(tmp_reg, &dev->plregs->pl_ep_ctrl);
1976*4882a593Smuzhiyun }
1977*4882a593Smuzhiyun }
1978*4882a593Smuzhiyun
defect7374_enable_data_eps_zero(struct net2280 * dev)1979*4882a593Smuzhiyun static void defect7374_enable_data_eps_zero(struct net2280 *dev)
1980*4882a593Smuzhiyun {
1981*4882a593Smuzhiyun u32 tmp = 0, tmp_reg;
1982*4882a593Smuzhiyun u32 scratch;
1983*4882a593Smuzhiyun int i;
1984*4882a593Smuzhiyun unsigned char ep_sel;
1985*4882a593Smuzhiyun
1986*4882a593Smuzhiyun scratch = get_idx_reg(dev->regs, SCRATCH);
1987*4882a593Smuzhiyun
1988*4882a593Smuzhiyun WARN_ON((scratch & (0xf << DEFECT7374_FSM_FIELD))
1989*4882a593Smuzhiyun == DEFECT7374_FSM_SS_CONTROL_READ);
1990*4882a593Smuzhiyun
1991*4882a593Smuzhiyun scratch &= ~(0xf << DEFECT7374_FSM_FIELD);
1992*4882a593Smuzhiyun
1993*4882a593Smuzhiyun ep_warn(dev, "Operate Defect 7374 workaround soft this time");
1994*4882a593Smuzhiyun ep_warn(dev, "It will operate on cold-reboot and SS connect");
1995*4882a593Smuzhiyun
1996*4882a593Smuzhiyun /*GPEPs:*/
1997*4882a593Smuzhiyun tmp = ((0 << ENDPOINT_NUMBER) | BIT(ENDPOINT_DIRECTION) |
1998*4882a593Smuzhiyun (2 << OUT_ENDPOINT_TYPE) | (2 << IN_ENDPOINT_TYPE) |
1999*4882a593Smuzhiyun ((dev->enhanced_mode) ?
2000*4882a593Smuzhiyun BIT(OUT_ENDPOINT_ENABLE) | BIT(IN_ENDPOINT_ENABLE) :
2001*4882a593Smuzhiyun BIT(ENDPOINT_ENABLE)));
2002*4882a593Smuzhiyun
2003*4882a593Smuzhiyun for (i = 1; i < 5; i++)
2004*4882a593Smuzhiyun writel(tmp, &dev->ep[i].cfg->ep_cfg);
2005*4882a593Smuzhiyun
2006*4882a593Smuzhiyun /* CSRIN, PCIIN, STATIN, RCIN*/
2007*4882a593Smuzhiyun tmp = ((0 << ENDPOINT_NUMBER) | BIT(ENDPOINT_ENABLE));
2008*4882a593Smuzhiyun writel(tmp, &dev->dep[1].dep_cfg);
2009*4882a593Smuzhiyun writel(tmp, &dev->dep[3].dep_cfg);
2010*4882a593Smuzhiyun writel(tmp, &dev->dep[4].dep_cfg);
2011*4882a593Smuzhiyun writel(tmp, &dev->dep[5].dep_cfg);
2012*4882a593Smuzhiyun
2013*4882a593Smuzhiyun /*Implemented for development and debug.
2014*4882a593Smuzhiyun * Can be refined/tuned later.*/
2015*4882a593Smuzhiyun for (ep_sel = 0; ep_sel <= 21; ep_sel++) {
2016*4882a593Smuzhiyun /* Select an endpoint for subsequent operations: */
2017*4882a593Smuzhiyun tmp_reg = readl(&dev->plregs->pl_ep_ctrl);
2018*4882a593Smuzhiyun writel(((tmp_reg & ~0x1f) | ep_sel),
2019*4882a593Smuzhiyun &dev->plregs->pl_ep_ctrl);
2020*4882a593Smuzhiyun
2021*4882a593Smuzhiyun if (ep_sel == 1) {
2022*4882a593Smuzhiyun tmp =
2023*4882a593Smuzhiyun (readl(&dev->plregs->pl_ep_ctrl) |
2024*4882a593Smuzhiyun BIT(CLEAR_ACK_ERROR_CODE) | 0);
2025*4882a593Smuzhiyun writel(tmp, &dev->plregs->pl_ep_ctrl);
2026*4882a593Smuzhiyun continue;
2027*4882a593Smuzhiyun }
2028*4882a593Smuzhiyun
2029*4882a593Smuzhiyun if (ep_sel == 0 || (ep_sel > 9 && ep_sel < 14) ||
2030*4882a593Smuzhiyun ep_sel == 18 || ep_sel == 20)
2031*4882a593Smuzhiyun continue;
2032*4882a593Smuzhiyun
2033*4882a593Smuzhiyun tmp = (readl(&dev->plregs->pl_ep_cfg_4) |
2034*4882a593Smuzhiyun BIT(NON_CTRL_IN_TOLERATE_BAD_DIR) | 0);
2035*4882a593Smuzhiyun writel(tmp, &dev->plregs->pl_ep_cfg_4);
2036*4882a593Smuzhiyun
2037*4882a593Smuzhiyun tmp = readl(&dev->plregs->pl_ep_ctrl) &
2038*4882a593Smuzhiyun ~BIT(EP_INITIALIZED);
2039*4882a593Smuzhiyun writel(tmp, &dev->plregs->pl_ep_ctrl);
2040*4882a593Smuzhiyun
2041*4882a593Smuzhiyun }
2042*4882a593Smuzhiyun
2043*4882a593Smuzhiyun /* Set FSM to focus on the first Control Read:
2044*4882a593Smuzhiyun * - Tip: Connection speed is known upon the first
2045*4882a593Smuzhiyun * setup request.*/
2046*4882a593Smuzhiyun scratch |= DEFECT7374_FSM_WAITING_FOR_CONTROL_READ;
2047*4882a593Smuzhiyun set_idx_reg(dev->regs, SCRATCH, scratch);
2048*4882a593Smuzhiyun
2049*4882a593Smuzhiyun }
2050*4882a593Smuzhiyun
2051*4882a593Smuzhiyun /* keeping it simple:
2052*4882a593Smuzhiyun * - one bus driver, initted first;
2053*4882a593Smuzhiyun * - one function driver, initted second
2054*4882a593Smuzhiyun *
2055*4882a593Smuzhiyun * most of the work to support multiple net2280 controllers would
2056*4882a593Smuzhiyun * be to associate this gadget driver (yes?) with all of them, or
2057*4882a593Smuzhiyun * perhaps to bind specific drivers to specific devices.
2058*4882a593Smuzhiyun */
2059*4882a593Smuzhiyun
usb_reset_228x(struct net2280 * dev)2060*4882a593Smuzhiyun static void usb_reset_228x(struct net2280 *dev)
2061*4882a593Smuzhiyun {
2062*4882a593Smuzhiyun u32 tmp;
2063*4882a593Smuzhiyun
2064*4882a593Smuzhiyun dev->gadget.speed = USB_SPEED_UNKNOWN;
2065*4882a593Smuzhiyun (void) readl(&dev->usb->usbctl);
2066*4882a593Smuzhiyun
2067*4882a593Smuzhiyun net2280_led_init(dev);
2068*4882a593Smuzhiyun
2069*4882a593Smuzhiyun /* disable automatic responses, and irqs */
2070*4882a593Smuzhiyun writel(0, &dev->usb->stdrsp);
2071*4882a593Smuzhiyun writel(0, &dev->regs->pciirqenb0);
2072*4882a593Smuzhiyun writel(0, &dev->regs->pciirqenb1);
2073*4882a593Smuzhiyun
2074*4882a593Smuzhiyun /* clear old dma and irq state */
2075*4882a593Smuzhiyun for (tmp = 0; tmp < 4; tmp++) {
2076*4882a593Smuzhiyun struct net2280_ep *ep = &dev->ep[tmp + 1];
2077*4882a593Smuzhiyun if (ep->dma)
2078*4882a593Smuzhiyun abort_dma(ep);
2079*4882a593Smuzhiyun }
2080*4882a593Smuzhiyun
2081*4882a593Smuzhiyun writel(~0, &dev->regs->irqstat0),
2082*4882a593Smuzhiyun writel(~(u32)BIT(SUSPEND_REQUEST_INTERRUPT), &dev->regs->irqstat1),
2083*4882a593Smuzhiyun
2084*4882a593Smuzhiyun /* reset, and enable pci */
2085*4882a593Smuzhiyun tmp = readl(&dev->regs->devinit) |
2086*4882a593Smuzhiyun BIT(PCI_ENABLE) |
2087*4882a593Smuzhiyun BIT(FIFO_SOFT_RESET) |
2088*4882a593Smuzhiyun BIT(USB_SOFT_RESET) |
2089*4882a593Smuzhiyun BIT(M8051_RESET);
2090*4882a593Smuzhiyun writel(tmp, &dev->regs->devinit);
2091*4882a593Smuzhiyun
2092*4882a593Smuzhiyun /* standard fifo and endpoint allocations */
2093*4882a593Smuzhiyun set_fifo_mode(dev, (fifo_mode <= 2) ? fifo_mode : 0);
2094*4882a593Smuzhiyun }
2095*4882a593Smuzhiyun
usb_reset_338x(struct net2280 * dev)2096*4882a593Smuzhiyun static void usb_reset_338x(struct net2280 *dev)
2097*4882a593Smuzhiyun {
2098*4882a593Smuzhiyun u32 tmp;
2099*4882a593Smuzhiyun
2100*4882a593Smuzhiyun dev->gadget.speed = USB_SPEED_UNKNOWN;
2101*4882a593Smuzhiyun (void)readl(&dev->usb->usbctl);
2102*4882a593Smuzhiyun
2103*4882a593Smuzhiyun net2280_led_init(dev);
2104*4882a593Smuzhiyun
2105*4882a593Smuzhiyun if (dev->bug7734_patched) {
2106*4882a593Smuzhiyun /* disable automatic responses, and irqs */
2107*4882a593Smuzhiyun writel(0, &dev->usb->stdrsp);
2108*4882a593Smuzhiyun writel(0, &dev->regs->pciirqenb0);
2109*4882a593Smuzhiyun writel(0, &dev->regs->pciirqenb1);
2110*4882a593Smuzhiyun }
2111*4882a593Smuzhiyun
2112*4882a593Smuzhiyun /* clear old dma and irq state */
2113*4882a593Smuzhiyun for (tmp = 0; tmp < 4; tmp++) {
2114*4882a593Smuzhiyun struct net2280_ep *ep = &dev->ep[tmp + 1];
2115*4882a593Smuzhiyun struct net2280_dma_regs __iomem *dma;
2116*4882a593Smuzhiyun
2117*4882a593Smuzhiyun if (ep->dma) {
2118*4882a593Smuzhiyun abort_dma(ep);
2119*4882a593Smuzhiyun } else {
2120*4882a593Smuzhiyun dma = &dev->dma[tmp];
2121*4882a593Smuzhiyun writel(BIT(DMA_ABORT), &dma->dmastat);
2122*4882a593Smuzhiyun writel(0, &dma->dmactl);
2123*4882a593Smuzhiyun }
2124*4882a593Smuzhiyun }
2125*4882a593Smuzhiyun
2126*4882a593Smuzhiyun writel(~0, &dev->regs->irqstat0), writel(~0, &dev->regs->irqstat1);
2127*4882a593Smuzhiyun
2128*4882a593Smuzhiyun if (dev->bug7734_patched) {
2129*4882a593Smuzhiyun /* reset, and enable pci */
2130*4882a593Smuzhiyun tmp = readl(&dev->regs->devinit) |
2131*4882a593Smuzhiyun BIT(PCI_ENABLE) |
2132*4882a593Smuzhiyun BIT(FIFO_SOFT_RESET) |
2133*4882a593Smuzhiyun BIT(USB_SOFT_RESET) |
2134*4882a593Smuzhiyun BIT(M8051_RESET);
2135*4882a593Smuzhiyun
2136*4882a593Smuzhiyun writel(tmp, &dev->regs->devinit);
2137*4882a593Smuzhiyun }
2138*4882a593Smuzhiyun
2139*4882a593Smuzhiyun /* always ep-{1,2,3,4} ... maybe not ep-3 or ep-4 */
2140*4882a593Smuzhiyun INIT_LIST_HEAD(&dev->gadget.ep_list);
2141*4882a593Smuzhiyun
2142*4882a593Smuzhiyun for (tmp = 1; tmp < dev->n_ep; tmp++)
2143*4882a593Smuzhiyun list_add_tail(&dev->ep[tmp].ep.ep_list, &dev->gadget.ep_list);
2144*4882a593Smuzhiyun
2145*4882a593Smuzhiyun }
2146*4882a593Smuzhiyun
usb_reset(struct net2280 * dev)2147*4882a593Smuzhiyun static void usb_reset(struct net2280 *dev)
2148*4882a593Smuzhiyun {
2149*4882a593Smuzhiyun if (dev->quirks & PLX_LEGACY)
2150*4882a593Smuzhiyun return usb_reset_228x(dev);
2151*4882a593Smuzhiyun return usb_reset_338x(dev);
2152*4882a593Smuzhiyun }
2153*4882a593Smuzhiyun
usb_reinit_228x(struct net2280 * dev)2154*4882a593Smuzhiyun static void usb_reinit_228x(struct net2280 *dev)
2155*4882a593Smuzhiyun {
2156*4882a593Smuzhiyun u32 tmp;
2157*4882a593Smuzhiyun
2158*4882a593Smuzhiyun /* basic endpoint init */
2159*4882a593Smuzhiyun for (tmp = 0; tmp < 7; tmp++) {
2160*4882a593Smuzhiyun struct net2280_ep *ep = &dev->ep[tmp];
2161*4882a593Smuzhiyun
2162*4882a593Smuzhiyun ep->ep.name = ep_info_dft[tmp].name;
2163*4882a593Smuzhiyun ep->ep.caps = ep_info_dft[tmp].caps;
2164*4882a593Smuzhiyun ep->dev = dev;
2165*4882a593Smuzhiyun ep->num = tmp;
2166*4882a593Smuzhiyun
2167*4882a593Smuzhiyun if (tmp > 0 && tmp <= 4) {
2168*4882a593Smuzhiyun ep->fifo_size = 1024;
2169*4882a593Smuzhiyun ep->dma = &dev->dma[tmp - 1];
2170*4882a593Smuzhiyun } else
2171*4882a593Smuzhiyun ep->fifo_size = 64;
2172*4882a593Smuzhiyun ep->regs = &dev->epregs[tmp];
2173*4882a593Smuzhiyun ep->cfg = &dev->epregs[tmp];
2174*4882a593Smuzhiyun ep_reset_228x(dev->regs, ep);
2175*4882a593Smuzhiyun }
2176*4882a593Smuzhiyun usb_ep_set_maxpacket_limit(&dev->ep[0].ep, 64);
2177*4882a593Smuzhiyun usb_ep_set_maxpacket_limit(&dev->ep[5].ep, 64);
2178*4882a593Smuzhiyun usb_ep_set_maxpacket_limit(&dev->ep[6].ep, 64);
2179*4882a593Smuzhiyun
2180*4882a593Smuzhiyun dev->gadget.ep0 = &dev->ep[0].ep;
2181*4882a593Smuzhiyun dev->ep[0].stopped = 0;
2182*4882a593Smuzhiyun INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2183*4882a593Smuzhiyun
2184*4882a593Smuzhiyun /* we want to prevent lowlevel/insecure access from the USB host,
2185*4882a593Smuzhiyun * but erratum 0119 means this enable bit is ignored
2186*4882a593Smuzhiyun */
2187*4882a593Smuzhiyun for (tmp = 0; tmp < 5; tmp++)
2188*4882a593Smuzhiyun writel(EP_DONTUSE, &dev->dep[tmp].dep_cfg);
2189*4882a593Smuzhiyun }
2190*4882a593Smuzhiyun
usb_reinit_338x(struct net2280 * dev)2191*4882a593Smuzhiyun static void usb_reinit_338x(struct net2280 *dev)
2192*4882a593Smuzhiyun {
2193*4882a593Smuzhiyun int i;
2194*4882a593Smuzhiyun u32 tmp, val;
2195*4882a593Smuzhiyun static const u32 ne[9] = { 0, 1, 2, 3, 4, 1, 2, 3, 4 };
2196*4882a593Smuzhiyun static const u32 ep_reg_addr[9] = { 0x00, 0xC0, 0x00, 0xC0, 0x00,
2197*4882a593Smuzhiyun 0x00, 0xC0, 0x00, 0xC0 };
2198*4882a593Smuzhiyun
2199*4882a593Smuzhiyun /* basic endpoint init */
2200*4882a593Smuzhiyun for (i = 0; i < dev->n_ep; i++) {
2201*4882a593Smuzhiyun struct net2280_ep *ep = &dev->ep[i];
2202*4882a593Smuzhiyun
2203*4882a593Smuzhiyun ep->ep.name = dev->enhanced_mode ? ep_info_adv[i].name :
2204*4882a593Smuzhiyun ep_info_dft[i].name;
2205*4882a593Smuzhiyun ep->ep.caps = dev->enhanced_mode ? ep_info_adv[i].caps :
2206*4882a593Smuzhiyun ep_info_dft[i].caps;
2207*4882a593Smuzhiyun ep->dev = dev;
2208*4882a593Smuzhiyun ep->num = i;
2209*4882a593Smuzhiyun
2210*4882a593Smuzhiyun if (i > 0 && i <= 4)
2211*4882a593Smuzhiyun ep->dma = &dev->dma[i - 1];
2212*4882a593Smuzhiyun
2213*4882a593Smuzhiyun if (dev->enhanced_mode) {
2214*4882a593Smuzhiyun ep->cfg = &dev->epregs[ne[i]];
2215*4882a593Smuzhiyun /*
2216*4882a593Smuzhiyun * Set USB endpoint number, hardware allows same number
2217*4882a593Smuzhiyun * in both directions.
2218*4882a593Smuzhiyun */
2219*4882a593Smuzhiyun if (i > 0 && i < 5)
2220*4882a593Smuzhiyun writel(ne[i], &ep->cfg->ep_cfg);
2221*4882a593Smuzhiyun ep->regs = (struct net2280_ep_regs __iomem *)
2222*4882a593Smuzhiyun (((void __iomem *)&dev->epregs[ne[i]]) +
2223*4882a593Smuzhiyun ep_reg_addr[i]);
2224*4882a593Smuzhiyun } else {
2225*4882a593Smuzhiyun ep->cfg = &dev->epregs[i];
2226*4882a593Smuzhiyun ep->regs = &dev->epregs[i];
2227*4882a593Smuzhiyun }
2228*4882a593Smuzhiyun
2229*4882a593Smuzhiyun ep->fifo_size = (i != 0) ? 2048 : 512;
2230*4882a593Smuzhiyun
2231*4882a593Smuzhiyun ep_reset_338x(dev->regs, ep);
2232*4882a593Smuzhiyun }
2233*4882a593Smuzhiyun usb_ep_set_maxpacket_limit(&dev->ep[0].ep, 512);
2234*4882a593Smuzhiyun
2235*4882a593Smuzhiyun dev->gadget.ep0 = &dev->ep[0].ep;
2236*4882a593Smuzhiyun dev->ep[0].stopped = 0;
2237*4882a593Smuzhiyun
2238*4882a593Smuzhiyun /* Link layer set up */
2239*4882a593Smuzhiyun if (dev->bug7734_patched) {
2240*4882a593Smuzhiyun tmp = readl(&dev->usb_ext->usbctl2) &
2241*4882a593Smuzhiyun ~(BIT(U1_ENABLE) | BIT(U2_ENABLE) | BIT(LTM_ENABLE));
2242*4882a593Smuzhiyun writel(tmp, &dev->usb_ext->usbctl2);
2243*4882a593Smuzhiyun }
2244*4882a593Smuzhiyun
2245*4882a593Smuzhiyun /* Hardware Defect and Workaround */
2246*4882a593Smuzhiyun val = readl(&dev->llregs->ll_lfps_5);
2247*4882a593Smuzhiyun val &= ~(0xf << TIMER_LFPS_6US);
2248*4882a593Smuzhiyun val |= 0x5 << TIMER_LFPS_6US;
2249*4882a593Smuzhiyun writel(val, &dev->llregs->ll_lfps_5);
2250*4882a593Smuzhiyun
2251*4882a593Smuzhiyun val = readl(&dev->llregs->ll_lfps_6);
2252*4882a593Smuzhiyun val &= ~(0xffff << TIMER_LFPS_80US);
2253*4882a593Smuzhiyun val |= 0x0100 << TIMER_LFPS_80US;
2254*4882a593Smuzhiyun writel(val, &dev->llregs->ll_lfps_6);
2255*4882a593Smuzhiyun
2256*4882a593Smuzhiyun /*
2257*4882a593Smuzhiyun * AA_AB Errata. Issue 4. Workaround for SuperSpeed USB
2258*4882a593Smuzhiyun * Hot Reset Exit Handshake may Fail in Specific Case using
2259*4882a593Smuzhiyun * Default Register Settings. Workaround for Enumeration test.
2260*4882a593Smuzhiyun */
2261*4882a593Smuzhiyun val = readl(&dev->llregs->ll_tsn_counters_2);
2262*4882a593Smuzhiyun val &= ~(0x1f << HOT_TX_NORESET_TS2);
2263*4882a593Smuzhiyun val |= 0x10 << HOT_TX_NORESET_TS2;
2264*4882a593Smuzhiyun writel(val, &dev->llregs->ll_tsn_counters_2);
2265*4882a593Smuzhiyun
2266*4882a593Smuzhiyun val = readl(&dev->llregs->ll_tsn_counters_3);
2267*4882a593Smuzhiyun val &= ~(0x1f << HOT_RX_RESET_TS2);
2268*4882a593Smuzhiyun val |= 0x3 << HOT_RX_RESET_TS2;
2269*4882a593Smuzhiyun writel(val, &dev->llregs->ll_tsn_counters_3);
2270*4882a593Smuzhiyun
2271*4882a593Smuzhiyun /*
2272*4882a593Smuzhiyun * AB errata. Errata 11. Workaround for Default Duration of LFPS
2273*4882a593Smuzhiyun * Handshake Signaling for Device-Initiated U1 Exit is too short.
2274*4882a593Smuzhiyun * Without this, various enumeration failures observed with
2275*4882a593Smuzhiyun * modern superspeed hosts.
2276*4882a593Smuzhiyun */
2277*4882a593Smuzhiyun val = readl(&dev->llregs->ll_lfps_timers_2);
2278*4882a593Smuzhiyun writel((val & 0xffff0000) | LFPS_TIMERS_2_WORKAROUND_VALUE,
2279*4882a593Smuzhiyun &dev->llregs->ll_lfps_timers_2);
2280*4882a593Smuzhiyun
2281*4882a593Smuzhiyun /*
2282*4882a593Smuzhiyun * Set Recovery Idle to Recover bit:
2283*4882a593Smuzhiyun * - On SS connections, setting Recovery Idle to Recover Fmw improves
2284*4882a593Smuzhiyun * link robustness with various hosts and hubs.
2285*4882a593Smuzhiyun * - It is safe to set for all connection speeds; all chip revisions.
2286*4882a593Smuzhiyun * - R-M-W to leave other bits undisturbed.
2287*4882a593Smuzhiyun * - Reference PLX TT-7372
2288*4882a593Smuzhiyun */
2289*4882a593Smuzhiyun val = readl(&dev->llregs->ll_tsn_chicken_bit);
2290*4882a593Smuzhiyun val |= BIT(RECOVERY_IDLE_TO_RECOVER_FMW);
2291*4882a593Smuzhiyun writel(val, &dev->llregs->ll_tsn_chicken_bit);
2292*4882a593Smuzhiyun
2293*4882a593Smuzhiyun INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2294*4882a593Smuzhiyun
2295*4882a593Smuzhiyun /* disable dedicated endpoints */
2296*4882a593Smuzhiyun writel(0x0D, &dev->dep[0].dep_cfg);
2297*4882a593Smuzhiyun writel(0x0D, &dev->dep[1].dep_cfg);
2298*4882a593Smuzhiyun writel(0x0E, &dev->dep[2].dep_cfg);
2299*4882a593Smuzhiyun writel(0x0E, &dev->dep[3].dep_cfg);
2300*4882a593Smuzhiyun writel(0x0F, &dev->dep[4].dep_cfg);
2301*4882a593Smuzhiyun writel(0x0C, &dev->dep[5].dep_cfg);
2302*4882a593Smuzhiyun }
2303*4882a593Smuzhiyun
usb_reinit(struct net2280 * dev)2304*4882a593Smuzhiyun static void usb_reinit(struct net2280 *dev)
2305*4882a593Smuzhiyun {
2306*4882a593Smuzhiyun if (dev->quirks & PLX_LEGACY)
2307*4882a593Smuzhiyun return usb_reinit_228x(dev);
2308*4882a593Smuzhiyun return usb_reinit_338x(dev);
2309*4882a593Smuzhiyun }
2310*4882a593Smuzhiyun
ep0_start_228x(struct net2280 * dev)2311*4882a593Smuzhiyun static void ep0_start_228x(struct net2280 *dev)
2312*4882a593Smuzhiyun {
2313*4882a593Smuzhiyun writel(BIT(CLEAR_EP_HIDE_STATUS_PHASE) |
2314*4882a593Smuzhiyun BIT(CLEAR_NAK_OUT_PACKETS) |
2315*4882a593Smuzhiyun BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE),
2316*4882a593Smuzhiyun &dev->epregs[0].ep_rsp);
2317*4882a593Smuzhiyun
2318*4882a593Smuzhiyun /*
2319*4882a593Smuzhiyun * hardware optionally handles a bunch of standard requests
2320*4882a593Smuzhiyun * that the API hides from drivers anyway. have it do so.
2321*4882a593Smuzhiyun * endpoint status/features are handled in software, to
2322*4882a593Smuzhiyun * help pass tests for some dubious behavior.
2323*4882a593Smuzhiyun */
2324*4882a593Smuzhiyun writel(BIT(SET_TEST_MODE) |
2325*4882a593Smuzhiyun BIT(SET_ADDRESS) |
2326*4882a593Smuzhiyun BIT(DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP) |
2327*4882a593Smuzhiyun BIT(GET_DEVICE_STATUS) |
2328*4882a593Smuzhiyun BIT(GET_INTERFACE_STATUS),
2329*4882a593Smuzhiyun &dev->usb->stdrsp);
2330*4882a593Smuzhiyun writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) |
2331*4882a593Smuzhiyun BIT(SELF_POWERED_USB_DEVICE) |
2332*4882a593Smuzhiyun BIT(REMOTE_WAKEUP_SUPPORT) |
2333*4882a593Smuzhiyun (dev->softconnect << USB_DETECT_ENABLE) |
2334*4882a593Smuzhiyun BIT(SELF_POWERED_STATUS),
2335*4882a593Smuzhiyun &dev->usb->usbctl);
2336*4882a593Smuzhiyun
2337*4882a593Smuzhiyun /* enable irqs so we can see ep0 and general operation */
2338*4882a593Smuzhiyun writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) |
2339*4882a593Smuzhiyun BIT(ENDPOINT_0_INTERRUPT_ENABLE),
2340*4882a593Smuzhiyun &dev->regs->pciirqenb0);
2341*4882a593Smuzhiyun writel(BIT(PCI_INTERRUPT_ENABLE) |
2342*4882a593Smuzhiyun BIT(PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE) |
2343*4882a593Smuzhiyun BIT(PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE) |
2344*4882a593Smuzhiyun BIT(PCI_RETRY_ABORT_INTERRUPT_ENABLE) |
2345*4882a593Smuzhiyun BIT(VBUS_INTERRUPT_ENABLE) |
2346*4882a593Smuzhiyun BIT(ROOT_PORT_RESET_INTERRUPT_ENABLE) |
2347*4882a593Smuzhiyun BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE),
2348*4882a593Smuzhiyun &dev->regs->pciirqenb1);
2349*4882a593Smuzhiyun
2350*4882a593Smuzhiyun /* don't leave any writes posted */
2351*4882a593Smuzhiyun (void) readl(&dev->usb->usbctl);
2352*4882a593Smuzhiyun }
2353*4882a593Smuzhiyun
ep0_start_338x(struct net2280 * dev)2354*4882a593Smuzhiyun static void ep0_start_338x(struct net2280 *dev)
2355*4882a593Smuzhiyun {
2356*4882a593Smuzhiyun
2357*4882a593Smuzhiyun if (dev->bug7734_patched)
2358*4882a593Smuzhiyun writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE) |
2359*4882a593Smuzhiyun BIT(SET_EP_HIDE_STATUS_PHASE),
2360*4882a593Smuzhiyun &dev->epregs[0].ep_rsp);
2361*4882a593Smuzhiyun
2362*4882a593Smuzhiyun /*
2363*4882a593Smuzhiyun * hardware optionally handles a bunch of standard requests
2364*4882a593Smuzhiyun * that the API hides from drivers anyway. have it do so.
2365*4882a593Smuzhiyun * endpoint status/features are handled in software, to
2366*4882a593Smuzhiyun * help pass tests for some dubious behavior.
2367*4882a593Smuzhiyun */
2368*4882a593Smuzhiyun writel(BIT(SET_ISOCHRONOUS_DELAY) |
2369*4882a593Smuzhiyun BIT(SET_SEL) |
2370*4882a593Smuzhiyun BIT(SET_TEST_MODE) |
2371*4882a593Smuzhiyun BIT(SET_ADDRESS) |
2372*4882a593Smuzhiyun BIT(GET_INTERFACE_STATUS) |
2373*4882a593Smuzhiyun BIT(GET_DEVICE_STATUS),
2374*4882a593Smuzhiyun &dev->usb->stdrsp);
2375*4882a593Smuzhiyun dev->wakeup_enable = 1;
2376*4882a593Smuzhiyun writel(BIT(USB_ROOT_PORT_WAKEUP_ENABLE) |
2377*4882a593Smuzhiyun (dev->softconnect << USB_DETECT_ENABLE) |
2378*4882a593Smuzhiyun BIT(DEVICE_REMOTE_WAKEUP_ENABLE),
2379*4882a593Smuzhiyun &dev->usb->usbctl);
2380*4882a593Smuzhiyun
2381*4882a593Smuzhiyun /* enable irqs so we can see ep0 and general operation */
2382*4882a593Smuzhiyun writel(BIT(SETUP_PACKET_INTERRUPT_ENABLE) |
2383*4882a593Smuzhiyun BIT(ENDPOINT_0_INTERRUPT_ENABLE),
2384*4882a593Smuzhiyun &dev->regs->pciirqenb0);
2385*4882a593Smuzhiyun writel(BIT(PCI_INTERRUPT_ENABLE) |
2386*4882a593Smuzhiyun BIT(ROOT_PORT_RESET_INTERRUPT_ENABLE) |
2387*4882a593Smuzhiyun BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE) |
2388*4882a593Smuzhiyun BIT(VBUS_INTERRUPT_ENABLE),
2389*4882a593Smuzhiyun &dev->regs->pciirqenb1);
2390*4882a593Smuzhiyun
2391*4882a593Smuzhiyun /* don't leave any writes posted */
2392*4882a593Smuzhiyun (void)readl(&dev->usb->usbctl);
2393*4882a593Smuzhiyun }
2394*4882a593Smuzhiyun
ep0_start(struct net2280 * dev)2395*4882a593Smuzhiyun static void ep0_start(struct net2280 *dev)
2396*4882a593Smuzhiyun {
2397*4882a593Smuzhiyun if (dev->quirks & PLX_LEGACY)
2398*4882a593Smuzhiyun return ep0_start_228x(dev);
2399*4882a593Smuzhiyun return ep0_start_338x(dev);
2400*4882a593Smuzhiyun }
2401*4882a593Smuzhiyun
2402*4882a593Smuzhiyun /* when a driver is successfully registered, it will receive
2403*4882a593Smuzhiyun * control requests including set_configuration(), which enables
2404*4882a593Smuzhiyun * non-control requests. then usb traffic follows until a
2405*4882a593Smuzhiyun * disconnect is reported. then a host may connect again, or
2406*4882a593Smuzhiyun * the driver might get unbound.
2407*4882a593Smuzhiyun */
net2280_start(struct usb_gadget * _gadget,struct usb_gadget_driver * driver)2408*4882a593Smuzhiyun static int net2280_start(struct usb_gadget *_gadget,
2409*4882a593Smuzhiyun struct usb_gadget_driver *driver)
2410*4882a593Smuzhiyun {
2411*4882a593Smuzhiyun struct net2280 *dev;
2412*4882a593Smuzhiyun int retval;
2413*4882a593Smuzhiyun unsigned i;
2414*4882a593Smuzhiyun
2415*4882a593Smuzhiyun /* insist on high speed support from the driver, since
2416*4882a593Smuzhiyun * (dev->usb->xcvrdiag & FORCE_FULL_SPEED_MODE)
2417*4882a593Smuzhiyun * "must not be used in normal operation"
2418*4882a593Smuzhiyun */
2419*4882a593Smuzhiyun if (!driver || driver->max_speed < USB_SPEED_HIGH ||
2420*4882a593Smuzhiyun !driver->setup)
2421*4882a593Smuzhiyun return -EINVAL;
2422*4882a593Smuzhiyun
2423*4882a593Smuzhiyun dev = container_of(_gadget, struct net2280, gadget);
2424*4882a593Smuzhiyun
2425*4882a593Smuzhiyun for (i = 0; i < dev->n_ep; i++)
2426*4882a593Smuzhiyun dev->ep[i].irqs = 0;
2427*4882a593Smuzhiyun
2428*4882a593Smuzhiyun /* hook up the driver ... */
2429*4882a593Smuzhiyun driver->driver.bus = NULL;
2430*4882a593Smuzhiyun dev->driver = driver;
2431*4882a593Smuzhiyun
2432*4882a593Smuzhiyun retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
2433*4882a593Smuzhiyun if (retval)
2434*4882a593Smuzhiyun goto err_unbind;
2435*4882a593Smuzhiyun retval = device_create_file(&dev->pdev->dev, &dev_attr_queues);
2436*4882a593Smuzhiyun if (retval)
2437*4882a593Smuzhiyun goto err_func;
2438*4882a593Smuzhiyun
2439*4882a593Smuzhiyun /* enable host detection and ep0; and we're ready
2440*4882a593Smuzhiyun * for set_configuration as well as eventual disconnect.
2441*4882a593Smuzhiyun */
2442*4882a593Smuzhiyun net2280_led_active(dev, 1);
2443*4882a593Smuzhiyun
2444*4882a593Smuzhiyun if ((dev->quirks & PLX_PCIE) && !dev->bug7734_patched)
2445*4882a593Smuzhiyun defect7374_enable_data_eps_zero(dev);
2446*4882a593Smuzhiyun
2447*4882a593Smuzhiyun ep0_start(dev);
2448*4882a593Smuzhiyun
2449*4882a593Smuzhiyun /* pci writes may still be posted */
2450*4882a593Smuzhiyun return 0;
2451*4882a593Smuzhiyun
2452*4882a593Smuzhiyun err_func:
2453*4882a593Smuzhiyun device_remove_file(&dev->pdev->dev, &dev_attr_function);
2454*4882a593Smuzhiyun err_unbind:
2455*4882a593Smuzhiyun dev->driver = NULL;
2456*4882a593Smuzhiyun return retval;
2457*4882a593Smuzhiyun }
2458*4882a593Smuzhiyun
stop_activity(struct net2280 * dev,struct usb_gadget_driver * driver)2459*4882a593Smuzhiyun static void stop_activity(struct net2280 *dev, struct usb_gadget_driver *driver)
2460*4882a593Smuzhiyun {
2461*4882a593Smuzhiyun int i;
2462*4882a593Smuzhiyun
2463*4882a593Smuzhiyun /* don't disconnect if it's not connected */
2464*4882a593Smuzhiyun if (dev->gadget.speed == USB_SPEED_UNKNOWN)
2465*4882a593Smuzhiyun driver = NULL;
2466*4882a593Smuzhiyun
2467*4882a593Smuzhiyun /* stop hardware; prevent new request submissions;
2468*4882a593Smuzhiyun * and kill any outstanding requests.
2469*4882a593Smuzhiyun */
2470*4882a593Smuzhiyun usb_reset(dev);
2471*4882a593Smuzhiyun for (i = 0; i < dev->n_ep; i++)
2472*4882a593Smuzhiyun nuke(&dev->ep[i]);
2473*4882a593Smuzhiyun
2474*4882a593Smuzhiyun /* report disconnect; the driver is already quiesced */
2475*4882a593Smuzhiyun if (driver) {
2476*4882a593Smuzhiyun spin_unlock(&dev->lock);
2477*4882a593Smuzhiyun driver->disconnect(&dev->gadget);
2478*4882a593Smuzhiyun spin_lock(&dev->lock);
2479*4882a593Smuzhiyun }
2480*4882a593Smuzhiyun
2481*4882a593Smuzhiyun usb_reinit(dev);
2482*4882a593Smuzhiyun }
2483*4882a593Smuzhiyun
net2280_stop(struct usb_gadget * _gadget)2484*4882a593Smuzhiyun static int net2280_stop(struct usb_gadget *_gadget)
2485*4882a593Smuzhiyun {
2486*4882a593Smuzhiyun struct net2280 *dev;
2487*4882a593Smuzhiyun unsigned long flags;
2488*4882a593Smuzhiyun
2489*4882a593Smuzhiyun dev = container_of(_gadget, struct net2280, gadget);
2490*4882a593Smuzhiyun
2491*4882a593Smuzhiyun spin_lock_irqsave(&dev->lock, flags);
2492*4882a593Smuzhiyun stop_activity(dev, NULL);
2493*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->lock, flags);
2494*4882a593Smuzhiyun
2495*4882a593Smuzhiyun net2280_led_active(dev, 0);
2496*4882a593Smuzhiyun
2497*4882a593Smuzhiyun device_remove_file(&dev->pdev->dev, &dev_attr_function);
2498*4882a593Smuzhiyun device_remove_file(&dev->pdev->dev, &dev_attr_queues);
2499*4882a593Smuzhiyun
2500*4882a593Smuzhiyun dev->driver = NULL;
2501*4882a593Smuzhiyun
2502*4882a593Smuzhiyun return 0;
2503*4882a593Smuzhiyun }
2504*4882a593Smuzhiyun
2505*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
2506*4882a593Smuzhiyun
2507*4882a593Smuzhiyun /* handle ep0, ep-e, ep-f with 64 byte packets: packet per irq.
2508*4882a593Smuzhiyun * also works for dma-capable endpoints, in pio mode or just
2509*4882a593Smuzhiyun * to manually advance the queue after short OUT transfers.
2510*4882a593Smuzhiyun */
handle_ep_small(struct net2280_ep * ep)2511*4882a593Smuzhiyun static void handle_ep_small(struct net2280_ep *ep)
2512*4882a593Smuzhiyun {
2513*4882a593Smuzhiyun struct net2280_request *req;
2514*4882a593Smuzhiyun u32 t;
2515*4882a593Smuzhiyun /* 0 error, 1 mid-data, 2 done */
2516*4882a593Smuzhiyun int mode = 1;
2517*4882a593Smuzhiyun
2518*4882a593Smuzhiyun if (!list_empty(&ep->queue))
2519*4882a593Smuzhiyun req = list_entry(ep->queue.next,
2520*4882a593Smuzhiyun struct net2280_request, queue);
2521*4882a593Smuzhiyun else
2522*4882a593Smuzhiyun req = NULL;
2523*4882a593Smuzhiyun
2524*4882a593Smuzhiyun /* ack all, and handle what we care about */
2525*4882a593Smuzhiyun t = readl(&ep->regs->ep_stat);
2526*4882a593Smuzhiyun ep->irqs++;
2527*4882a593Smuzhiyun
2528*4882a593Smuzhiyun ep_vdbg(ep->dev, "%s ack ep_stat %08x, req %p\n",
2529*4882a593Smuzhiyun ep->ep.name, t, req ? &req->req : NULL);
2530*4882a593Smuzhiyun
2531*4882a593Smuzhiyun if (!ep->is_in || (ep->dev->quirks & PLX_2280))
2532*4882a593Smuzhiyun writel(t & ~BIT(NAK_OUT_PACKETS), &ep->regs->ep_stat);
2533*4882a593Smuzhiyun else
2534*4882a593Smuzhiyun /* Added for 2282 */
2535*4882a593Smuzhiyun writel(t, &ep->regs->ep_stat);
2536*4882a593Smuzhiyun
2537*4882a593Smuzhiyun /* for ep0, monitor token irqs to catch data stage length errors
2538*4882a593Smuzhiyun * and to synchronize on status.
2539*4882a593Smuzhiyun *
2540*4882a593Smuzhiyun * also, to defer reporting of protocol stalls ... here's where
2541*4882a593Smuzhiyun * data or status first appears, handling stalls here should never
2542*4882a593Smuzhiyun * cause trouble on the host side..
2543*4882a593Smuzhiyun *
2544*4882a593Smuzhiyun * control requests could be slightly faster without token synch for
2545*4882a593Smuzhiyun * status, but status can jam up that way.
2546*4882a593Smuzhiyun */
2547*4882a593Smuzhiyun if (unlikely(ep->num == 0)) {
2548*4882a593Smuzhiyun if (ep->is_in) {
2549*4882a593Smuzhiyun /* status; stop NAKing */
2550*4882a593Smuzhiyun if (t & BIT(DATA_OUT_PING_TOKEN_INTERRUPT)) {
2551*4882a593Smuzhiyun if (ep->dev->protocol_stall) {
2552*4882a593Smuzhiyun ep->stopped = 1;
2553*4882a593Smuzhiyun set_halt(ep);
2554*4882a593Smuzhiyun }
2555*4882a593Smuzhiyun if (!req)
2556*4882a593Smuzhiyun allow_status(ep);
2557*4882a593Smuzhiyun mode = 2;
2558*4882a593Smuzhiyun /* reply to extra IN data tokens with a zlp */
2559*4882a593Smuzhiyun } else if (t & BIT(DATA_IN_TOKEN_INTERRUPT)) {
2560*4882a593Smuzhiyun if (ep->dev->protocol_stall) {
2561*4882a593Smuzhiyun ep->stopped = 1;
2562*4882a593Smuzhiyun set_halt(ep);
2563*4882a593Smuzhiyun mode = 2;
2564*4882a593Smuzhiyun } else if (ep->responded &&
2565*4882a593Smuzhiyun !req && !ep->stopped)
2566*4882a593Smuzhiyun write_fifo(ep, NULL);
2567*4882a593Smuzhiyun }
2568*4882a593Smuzhiyun } else {
2569*4882a593Smuzhiyun /* status; stop NAKing */
2570*4882a593Smuzhiyun if (t & BIT(DATA_IN_TOKEN_INTERRUPT)) {
2571*4882a593Smuzhiyun if (ep->dev->protocol_stall) {
2572*4882a593Smuzhiyun ep->stopped = 1;
2573*4882a593Smuzhiyun set_halt(ep);
2574*4882a593Smuzhiyun }
2575*4882a593Smuzhiyun mode = 2;
2576*4882a593Smuzhiyun /* an extra OUT token is an error */
2577*4882a593Smuzhiyun } else if (((t & BIT(DATA_OUT_PING_TOKEN_INTERRUPT)) &&
2578*4882a593Smuzhiyun req &&
2579*4882a593Smuzhiyun req->req.actual == req->req.length) ||
2580*4882a593Smuzhiyun (ep->responded && !req)) {
2581*4882a593Smuzhiyun ep->dev->protocol_stall = 1;
2582*4882a593Smuzhiyun set_halt(ep);
2583*4882a593Smuzhiyun ep->stopped = 1;
2584*4882a593Smuzhiyun if (req)
2585*4882a593Smuzhiyun done(ep, req, -EOVERFLOW);
2586*4882a593Smuzhiyun req = NULL;
2587*4882a593Smuzhiyun }
2588*4882a593Smuzhiyun }
2589*4882a593Smuzhiyun }
2590*4882a593Smuzhiyun
2591*4882a593Smuzhiyun if (unlikely(!req))
2592*4882a593Smuzhiyun return;
2593*4882a593Smuzhiyun
2594*4882a593Smuzhiyun /* manual DMA queue advance after short OUT */
2595*4882a593Smuzhiyun if (likely(ep->dma)) {
2596*4882a593Smuzhiyun if (t & BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT)) {
2597*4882a593Smuzhiyun struct net2280_request *stuck_req = NULL;
2598*4882a593Smuzhiyun int stopped = ep->stopped;
2599*4882a593Smuzhiyun int num_completed;
2600*4882a593Smuzhiyun int stuck = 0;
2601*4882a593Smuzhiyun u32 count;
2602*4882a593Smuzhiyun
2603*4882a593Smuzhiyun /* TRANSFERRED works around OUT_DONE erratum 0112.
2604*4882a593Smuzhiyun * we expect (N <= maxpacket) bytes; host wrote M.
2605*4882a593Smuzhiyun * iff (M < N) we won't ever see a DMA interrupt.
2606*4882a593Smuzhiyun */
2607*4882a593Smuzhiyun ep->stopped = 1;
2608*4882a593Smuzhiyun for (count = 0; ; t = readl(&ep->regs->ep_stat)) {
2609*4882a593Smuzhiyun
2610*4882a593Smuzhiyun /* any preceding dma transfers must finish.
2611*4882a593Smuzhiyun * dma handles (M >= N), may empty the queue
2612*4882a593Smuzhiyun */
2613*4882a593Smuzhiyun num_completed = scan_dma_completions(ep);
2614*4882a593Smuzhiyun if (unlikely(list_empty(&ep->queue) ||
2615*4882a593Smuzhiyun ep->out_overflow)) {
2616*4882a593Smuzhiyun req = NULL;
2617*4882a593Smuzhiyun break;
2618*4882a593Smuzhiyun }
2619*4882a593Smuzhiyun req = list_entry(ep->queue.next,
2620*4882a593Smuzhiyun struct net2280_request, queue);
2621*4882a593Smuzhiyun
2622*4882a593Smuzhiyun /* here either (M < N), a "real" short rx;
2623*4882a593Smuzhiyun * or (M == N) and the queue didn't empty
2624*4882a593Smuzhiyun */
2625*4882a593Smuzhiyun if (likely(t & BIT(FIFO_EMPTY))) {
2626*4882a593Smuzhiyun count = readl(&ep->dma->dmacount);
2627*4882a593Smuzhiyun count &= DMA_BYTE_COUNT_MASK;
2628*4882a593Smuzhiyun if (readl(&ep->dma->dmadesc)
2629*4882a593Smuzhiyun != req->td_dma)
2630*4882a593Smuzhiyun req = NULL;
2631*4882a593Smuzhiyun break;
2632*4882a593Smuzhiyun }
2633*4882a593Smuzhiyun
2634*4882a593Smuzhiyun /* Escape loop if no dma transfers completed
2635*4882a593Smuzhiyun * after few retries.
2636*4882a593Smuzhiyun */
2637*4882a593Smuzhiyun if (num_completed == 0) {
2638*4882a593Smuzhiyun if (stuck_req == req &&
2639*4882a593Smuzhiyun readl(&ep->dma->dmadesc) !=
2640*4882a593Smuzhiyun req->td_dma && stuck++ > 5) {
2641*4882a593Smuzhiyun count = readl(
2642*4882a593Smuzhiyun &ep->dma->dmacount);
2643*4882a593Smuzhiyun count &= DMA_BYTE_COUNT_MASK;
2644*4882a593Smuzhiyun req = NULL;
2645*4882a593Smuzhiyun ep_dbg(ep->dev, "%s escape stuck %d, count %u\n",
2646*4882a593Smuzhiyun ep->ep.name, stuck,
2647*4882a593Smuzhiyun count);
2648*4882a593Smuzhiyun break;
2649*4882a593Smuzhiyun } else if (stuck_req != req) {
2650*4882a593Smuzhiyun stuck_req = req;
2651*4882a593Smuzhiyun stuck = 0;
2652*4882a593Smuzhiyun }
2653*4882a593Smuzhiyun } else {
2654*4882a593Smuzhiyun stuck_req = NULL;
2655*4882a593Smuzhiyun stuck = 0;
2656*4882a593Smuzhiyun }
2657*4882a593Smuzhiyun
2658*4882a593Smuzhiyun udelay(1);
2659*4882a593Smuzhiyun }
2660*4882a593Smuzhiyun
2661*4882a593Smuzhiyun /* stop DMA, leave ep NAKing */
2662*4882a593Smuzhiyun writel(BIT(DMA_ABORT), &ep->dma->dmastat);
2663*4882a593Smuzhiyun spin_stop_dma(ep->dma);
2664*4882a593Smuzhiyun
2665*4882a593Smuzhiyun if (likely(req)) {
2666*4882a593Smuzhiyun req->td->dmacount = 0;
2667*4882a593Smuzhiyun t = readl(&ep->regs->ep_avail);
2668*4882a593Smuzhiyun dma_done(ep, req, count,
2669*4882a593Smuzhiyun (ep->out_overflow || t)
2670*4882a593Smuzhiyun ? -EOVERFLOW : 0);
2671*4882a593Smuzhiyun }
2672*4882a593Smuzhiyun
2673*4882a593Smuzhiyun /* also flush to prevent erratum 0106 trouble */
2674*4882a593Smuzhiyun if (unlikely(ep->out_overflow ||
2675*4882a593Smuzhiyun (ep->dev->chiprev == 0x0100 &&
2676*4882a593Smuzhiyun ep->dev->gadget.speed
2677*4882a593Smuzhiyun == USB_SPEED_FULL))) {
2678*4882a593Smuzhiyun out_flush(ep);
2679*4882a593Smuzhiyun ep->out_overflow = 0;
2680*4882a593Smuzhiyun }
2681*4882a593Smuzhiyun
2682*4882a593Smuzhiyun /* (re)start dma if needed, stop NAKing */
2683*4882a593Smuzhiyun ep->stopped = stopped;
2684*4882a593Smuzhiyun if (!list_empty(&ep->queue))
2685*4882a593Smuzhiyun restart_dma(ep);
2686*4882a593Smuzhiyun } else
2687*4882a593Smuzhiyun ep_dbg(ep->dev, "%s dma ep_stat %08x ??\n",
2688*4882a593Smuzhiyun ep->ep.name, t);
2689*4882a593Smuzhiyun return;
2690*4882a593Smuzhiyun
2691*4882a593Smuzhiyun /* data packet(s) received (in the fifo, OUT) */
2692*4882a593Smuzhiyun } else if (t & BIT(DATA_PACKET_RECEIVED_INTERRUPT)) {
2693*4882a593Smuzhiyun if (read_fifo(ep, req) && ep->num != 0)
2694*4882a593Smuzhiyun mode = 2;
2695*4882a593Smuzhiyun
2696*4882a593Smuzhiyun /* data packet(s) transmitted (IN) */
2697*4882a593Smuzhiyun } else if (t & BIT(DATA_PACKET_TRANSMITTED_INTERRUPT)) {
2698*4882a593Smuzhiyun unsigned len;
2699*4882a593Smuzhiyun
2700*4882a593Smuzhiyun len = req->req.length - req->req.actual;
2701*4882a593Smuzhiyun if (len > ep->ep.maxpacket)
2702*4882a593Smuzhiyun len = ep->ep.maxpacket;
2703*4882a593Smuzhiyun req->req.actual += len;
2704*4882a593Smuzhiyun
2705*4882a593Smuzhiyun /* if we wrote it all, we're usually done */
2706*4882a593Smuzhiyun /* send zlps until the status stage */
2707*4882a593Smuzhiyun if ((req->req.actual == req->req.length) &&
2708*4882a593Smuzhiyun (!req->req.zero || len != ep->ep.maxpacket) && ep->num)
2709*4882a593Smuzhiyun mode = 2;
2710*4882a593Smuzhiyun
2711*4882a593Smuzhiyun /* there was nothing to do ... */
2712*4882a593Smuzhiyun } else if (mode == 1)
2713*4882a593Smuzhiyun return;
2714*4882a593Smuzhiyun
2715*4882a593Smuzhiyun /* done */
2716*4882a593Smuzhiyun if (mode == 2) {
2717*4882a593Smuzhiyun /* stream endpoints often resubmit/unlink in completion */
2718*4882a593Smuzhiyun done(ep, req, 0);
2719*4882a593Smuzhiyun
2720*4882a593Smuzhiyun /* maybe advance queue to next request */
2721*4882a593Smuzhiyun if (ep->num == 0) {
2722*4882a593Smuzhiyun /* NOTE: net2280 could let gadget driver start the
2723*4882a593Smuzhiyun * status stage later. since not all controllers let
2724*4882a593Smuzhiyun * them control that, the api doesn't (yet) allow it.
2725*4882a593Smuzhiyun */
2726*4882a593Smuzhiyun if (!ep->stopped)
2727*4882a593Smuzhiyun allow_status(ep);
2728*4882a593Smuzhiyun req = NULL;
2729*4882a593Smuzhiyun } else {
2730*4882a593Smuzhiyun if (!list_empty(&ep->queue) && !ep->stopped)
2731*4882a593Smuzhiyun req = list_entry(ep->queue.next,
2732*4882a593Smuzhiyun struct net2280_request, queue);
2733*4882a593Smuzhiyun else
2734*4882a593Smuzhiyun req = NULL;
2735*4882a593Smuzhiyun if (req && !ep->is_in)
2736*4882a593Smuzhiyun stop_out_naking(ep);
2737*4882a593Smuzhiyun }
2738*4882a593Smuzhiyun }
2739*4882a593Smuzhiyun
2740*4882a593Smuzhiyun /* is there a buffer for the next packet?
2741*4882a593Smuzhiyun * for best streaming performance, make sure there is one.
2742*4882a593Smuzhiyun */
2743*4882a593Smuzhiyun if (req && !ep->stopped) {
2744*4882a593Smuzhiyun
2745*4882a593Smuzhiyun /* load IN fifo with next packet (may be zlp) */
2746*4882a593Smuzhiyun if (t & BIT(DATA_PACKET_TRANSMITTED_INTERRUPT))
2747*4882a593Smuzhiyun write_fifo(ep, &req->req);
2748*4882a593Smuzhiyun }
2749*4882a593Smuzhiyun }
2750*4882a593Smuzhiyun
get_ep_by_addr(struct net2280 * dev,u16 wIndex)2751*4882a593Smuzhiyun static struct net2280_ep *get_ep_by_addr(struct net2280 *dev, u16 wIndex)
2752*4882a593Smuzhiyun {
2753*4882a593Smuzhiyun struct net2280_ep *ep;
2754*4882a593Smuzhiyun
2755*4882a593Smuzhiyun if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
2756*4882a593Smuzhiyun return &dev->ep[0];
2757*4882a593Smuzhiyun list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
2758*4882a593Smuzhiyun u8 bEndpointAddress;
2759*4882a593Smuzhiyun
2760*4882a593Smuzhiyun if (!ep->desc)
2761*4882a593Smuzhiyun continue;
2762*4882a593Smuzhiyun bEndpointAddress = ep->desc->bEndpointAddress;
2763*4882a593Smuzhiyun if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
2764*4882a593Smuzhiyun continue;
2765*4882a593Smuzhiyun if ((wIndex & 0x0f) == (bEndpointAddress & 0x0f))
2766*4882a593Smuzhiyun return ep;
2767*4882a593Smuzhiyun }
2768*4882a593Smuzhiyun return NULL;
2769*4882a593Smuzhiyun }
2770*4882a593Smuzhiyun
defect7374_workaround(struct net2280 * dev,struct usb_ctrlrequest r)2771*4882a593Smuzhiyun static void defect7374_workaround(struct net2280 *dev, struct usb_ctrlrequest r)
2772*4882a593Smuzhiyun {
2773*4882a593Smuzhiyun u32 scratch, fsmvalue;
2774*4882a593Smuzhiyun u32 ack_wait_timeout, state;
2775*4882a593Smuzhiyun
2776*4882a593Smuzhiyun /* Workaround for Defect 7374 (U1/U2 erroneously rejected): */
2777*4882a593Smuzhiyun scratch = get_idx_reg(dev->regs, SCRATCH);
2778*4882a593Smuzhiyun fsmvalue = scratch & (0xf << DEFECT7374_FSM_FIELD);
2779*4882a593Smuzhiyun scratch &= ~(0xf << DEFECT7374_FSM_FIELD);
2780*4882a593Smuzhiyun
2781*4882a593Smuzhiyun if (!((fsmvalue == DEFECT7374_FSM_WAITING_FOR_CONTROL_READ) &&
2782*4882a593Smuzhiyun (r.bRequestType & USB_DIR_IN)))
2783*4882a593Smuzhiyun return;
2784*4882a593Smuzhiyun
2785*4882a593Smuzhiyun /* This is the first Control Read for this connection: */
2786*4882a593Smuzhiyun if (!(readl(&dev->usb->usbstat) & BIT(SUPER_SPEED_MODE))) {
2787*4882a593Smuzhiyun /*
2788*4882a593Smuzhiyun * Connection is NOT SS:
2789*4882a593Smuzhiyun * - Connection must be FS or HS.
2790*4882a593Smuzhiyun * - This FSM state should allow workaround software to
2791*4882a593Smuzhiyun * run after the next USB connection.
2792*4882a593Smuzhiyun */
2793*4882a593Smuzhiyun scratch |= DEFECT7374_FSM_NON_SS_CONTROL_READ;
2794*4882a593Smuzhiyun dev->bug7734_patched = 1;
2795*4882a593Smuzhiyun goto restore_data_eps;
2796*4882a593Smuzhiyun }
2797*4882a593Smuzhiyun
2798*4882a593Smuzhiyun /* Connection is SS: */
2799*4882a593Smuzhiyun for (ack_wait_timeout = 0;
2800*4882a593Smuzhiyun ack_wait_timeout < DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS;
2801*4882a593Smuzhiyun ack_wait_timeout++) {
2802*4882a593Smuzhiyun
2803*4882a593Smuzhiyun state = readl(&dev->plregs->pl_ep_status_1)
2804*4882a593Smuzhiyun & (0xff << STATE);
2805*4882a593Smuzhiyun if ((state >= (ACK_GOOD_NORMAL << STATE)) &&
2806*4882a593Smuzhiyun (state <= (ACK_GOOD_MORE_ACKS_TO_COME << STATE))) {
2807*4882a593Smuzhiyun scratch |= DEFECT7374_FSM_SS_CONTROL_READ;
2808*4882a593Smuzhiyun dev->bug7734_patched = 1;
2809*4882a593Smuzhiyun break;
2810*4882a593Smuzhiyun }
2811*4882a593Smuzhiyun
2812*4882a593Smuzhiyun /*
2813*4882a593Smuzhiyun * We have not yet received host's Data Phase ACK
2814*4882a593Smuzhiyun * - Wait and try again.
2815*4882a593Smuzhiyun */
2816*4882a593Smuzhiyun udelay(DEFECT_7374_PROCESSOR_WAIT_TIME);
2817*4882a593Smuzhiyun
2818*4882a593Smuzhiyun continue;
2819*4882a593Smuzhiyun }
2820*4882a593Smuzhiyun
2821*4882a593Smuzhiyun
2822*4882a593Smuzhiyun if (ack_wait_timeout >= DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS) {
2823*4882a593Smuzhiyun ep_err(dev, "FAIL: Defect 7374 workaround waited but failed "
2824*4882a593Smuzhiyun "to detect SS host's data phase ACK.");
2825*4882a593Smuzhiyun ep_err(dev, "PL_EP_STATUS_1(23:16):.Expected from 0x11 to 0x16"
2826*4882a593Smuzhiyun "got 0x%2.2x.\n", state >> STATE);
2827*4882a593Smuzhiyun } else {
2828*4882a593Smuzhiyun ep_warn(dev, "INFO: Defect 7374 workaround waited about\n"
2829*4882a593Smuzhiyun "%duSec for Control Read Data Phase ACK\n",
2830*4882a593Smuzhiyun DEFECT_7374_PROCESSOR_WAIT_TIME * ack_wait_timeout);
2831*4882a593Smuzhiyun }
2832*4882a593Smuzhiyun
2833*4882a593Smuzhiyun restore_data_eps:
2834*4882a593Smuzhiyun /*
2835*4882a593Smuzhiyun * Restore data EPs to their pre-workaround settings (disabled,
2836*4882a593Smuzhiyun * initialized, and other details).
2837*4882a593Smuzhiyun */
2838*4882a593Smuzhiyun defect7374_disable_data_eps(dev);
2839*4882a593Smuzhiyun
2840*4882a593Smuzhiyun set_idx_reg(dev->regs, SCRATCH, scratch);
2841*4882a593Smuzhiyun
2842*4882a593Smuzhiyun return;
2843*4882a593Smuzhiyun }
2844*4882a593Smuzhiyun
ep_clear_seqnum(struct net2280_ep * ep)2845*4882a593Smuzhiyun static void ep_clear_seqnum(struct net2280_ep *ep)
2846*4882a593Smuzhiyun {
2847*4882a593Smuzhiyun struct net2280 *dev = ep->dev;
2848*4882a593Smuzhiyun u32 val;
2849*4882a593Smuzhiyun static const u32 ep_pl[9] = { 0, 3, 4, 7, 8, 2, 5, 6, 9 };
2850*4882a593Smuzhiyun
2851*4882a593Smuzhiyun val = readl(&dev->plregs->pl_ep_ctrl) & ~0x1f;
2852*4882a593Smuzhiyun val |= ep_pl[ep->num];
2853*4882a593Smuzhiyun writel(val, &dev->plregs->pl_ep_ctrl);
2854*4882a593Smuzhiyun val |= BIT(SEQUENCE_NUMBER_RESET);
2855*4882a593Smuzhiyun writel(val, &dev->plregs->pl_ep_ctrl);
2856*4882a593Smuzhiyun
2857*4882a593Smuzhiyun return;
2858*4882a593Smuzhiyun }
2859*4882a593Smuzhiyun
handle_stat0_irqs_superspeed(struct net2280 * dev,struct net2280_ep * ep,struct usb_ctrlrequest r)2860*4882a593Smuzhiyun static void handle_stat0_irqs_superspeed(struct net2280 *dev,
2861*4882a593Smuzhiyun struct net2280_ep *ep, struct usb_ctrlrequest r)
2862*4882a593Smuzhiyun {
2863*4882a593Smuzhiyun struct net2280_ep *e;
2864*4882a593Smuzhiyun u16 status;
2865*4882a593Smuzhiyun int tmp = 0;
2866*4882a593Smuzhiyun
2867*4882a593Smuzhiyun #define w_value le16_to_cpu(r.wValue)
2868*4882a593Smuzhiyun #define w_index le16_to_cpu(r.wIndex)
2869*4882a593Smuzhiyun #define w_length le16_to_cpu(r.wLength)
2870*4882a593Smuzhiyun
2871*4882a593Smuzhiyun switch (r.bRequest) {
2872*4882a593Smuzhiyun case USB_REQ_SET_CONFIGURATION:
2873*4882a593Smuzhiyun dev->addressed_state = !w_value;
2874*4882a593Smuzhiyun goto usb3_delegate;
2875*4882a593Smuzhiyun
2876*4882a593Smuzhiyun case USB_REQ_GET_STATUS:
2877*4882a593Smuzhiyun switch (r.bRequestType) {
2878*4882a593Smuzhiyun case (USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2879*4882a593Smuzhiyun status = dev->wakeup_enable ? 0x02 : 0x00;
2880*4882a593Smuzhiyun if (dev->gadget.is_selfpowered)
2881*4882a593Smuzhiyun status |= BIT(0);
2882*4882a593Smuzhiyun status |= (dev->u1_enable << 2 | dev->u2_enable << 3 |
2883*4882a593Smuzhiyun dev->ltm_enable << 4);
2884*4882a593Smuzhiyun writel(0, &dev->epregs[0].ep_irqenb);
2885*4882a593Smuzhiyun set_fifo_bytecount(ep, sizeof(status));
2886*4882a593Smuzhiyun writel((__force u32) status, &dev->epregs[0].ep_data);
2887*4882a593Smuzhiyun allow_status_338x(ep);
2888*4882a593Smuzhiyun break;
2889*4882a593Smuzhiyun
2890*4882a593Smuzhiyun case (USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2891*4882a593Smuzhiyun e = get_ep_by_addr(dev, w_index);
2892*4882a593Smuzhiyun if (!e)
2893*4882a593Smuzhiyun goto do_stall3;
2894*4882a593Smuzhiyun status = readl(&e->regs->ep_rsp) &
2895*4882a593Smuzhiyun BIT(CLEAR_ENDPOINT_HALT);
2896*4882a593Smuzhiyun writel(0, &dev->epregs[0].ep_irqenb);
2897*4882a593Smuzhiyun set_fifo_bytecount(ep, sizeof(status));
2898*4882a593Smuzhiyun writel((__force u32) status, &dev->epregs[0].ep_data);
2899*4882a593Smuzhiyun allow_status_338x(ep);
2900*4882a593Smuzhiyun break;
2901*4882a593Smuzhiyun
2902*4882a593Smuzhiyun default:
2903*4882a593Smuzhiyun goto usb3_delegate;
2904*4882a593Smuzhiyun }
2905*4882a593Smuzhiyun break;
2906*4882a593Smuzhiyun
2907*4882a593Smuzhiyun case USB_REQ_CLEAR_FEATURE:
2908*4882a593Smuzhiyun switch (r.bRequestType) {
2909*4882a593Smuzhiyun case (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2910*4882a593Smuzhiyun if (!dev->addressed_state) {
2911*4882a593Smuzhiyun switch (w_value) {
2912*4882a593Smuzhiyun case USB_DEVICE_U1_ENABLE:
2913*4882a593Smuzhiyun dev->u1_enable = 0;
2914*4882a593Smuzhiyun writel(readl(&dev->usb_ext->usbctl2) &
2915*4882a593Smuzhiyun ~BIT(U1_ENABLE),
2916*4882a593Smuzhiyun &dev->usb_ext->usbctl2);
2917*4882a593Smuzhiyun allow_status_338x(ep);
2918*4882a593Smuzhiyun goto next_endpoints3;
2919*4882a593Smuzhiyun
2920*4882a593Smuzhiyun case USB_DEVICE_U2_ENABLE:
2921*4882a593Smuzhiyun dev->u2_enable = 0;
2922*4882a593Smuzhiyun writel(readl(&dev->usb_ext->usbctl2) &
2923*4882a593Smuzhiyun ~BIT(U2_ENABLE),
2924*4882a593Smuzhiyun &dev->usb_ext->usbctl2);
2925*4882a593Smuzhiyun allow_status_338x(ep);
2926*4882a593Smuzhiyun goto next_endpoints3;
2927*4882a593Smuzhiyun
2928*4882a593Smuzhiyun case USB_DEVICE_LTM_ENABLE:
2929*4882a593Smuzhiyun dev->ltm_enable = 0;
2930*4882a593Smuzhiyun writel(readl(&dev->usb_ext->usbctl2) &
2931*4882a593Smuzhiyun ~BIT(LTM_ENABLE),
2932*4882a593Smuzhiyun &dev->usb_ext->usbctl2);
2933*4882a593Smuzhiyun allow_status_338x(ep);
2934*4882a593Smuzhiyun goto next_endpoints3;
2935*4882a593Smuzhiyun
2936*4882a593Smuzhiyun default:
2937*4882a593Smuzhiyun break;
2938*4882a593Smuzhiyun }
2939*4882a593Smuzhiyun }
2940*4882a593Smuzhiyun if (w_value == USB_DEVICE_REMOTE_WAKEUP) {
2941*4882a593Smuzhiyun dev->wakeup_enable = 0;
2942*4882a593Smuzhiyun writel(readl(&dev->usb->usbctl) &
2943*4882a593Smuzhiyun ~BIT(DEVICE_REMOTE_WAKEUP_ENABLE),
2944*4882a593Smuzhiyun &dev->usb->usbctl);
2945*4882a593Smuzhiyun allow_status_338x(ep);
2946*4882a593Smuzhiyun break;
2947*4882a593Smuzhiyun }
2948*4882a593Smuzhiyun goto usb3_delegate;
2949*4882a593Smuzhiyun
2950*4882a593Smuzhiyun case (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2951*4882a593Smuzhiyun e = get_ep_by_addr(dev, w_index);
2952*4882a593Smuzhiyun if (!e)
2953*4882a593Smuzhiyun goto do_stall3;
2954*4882a593Smuzhiyun if (w_value != USB_ENDPOINT_HALT)
2955*4882a593Smuzhiyun goto do_stall3;
2956*4882a593Smuzhiyun ep_vdbg(dev, "%s clear halt\n", e->ep.name);
2957*4882a593Smuzhiyun /*
2958*4882a593Smuzhiyun * Workaround for SS SeqNum not cleared via
2959*4882a593Smuzhiyun * Endpoint Halt (Clear) bit. select endpoint
2960*4882a593Smuzhiyun */
2961*4882a593Smuzhiyun ep_clear_seqnum(e);
2962*4882a593Smuzhiyun clear_halt(e);
2963*4882a593Smuzhiyun if (!list_empty(&e->queue) && e->td_dma)
2964*4882a593Smuzhiyun restart_dma(e);
2965*4882a593Smuzhiyun allow_status(ep);
2966*4882a593Smuzhiyun ep->stopped = 1;
2967*4882a593Smuzhiyun break;
2968*4882a593Smuzhiyun
2969*4882a593Smuzhiyun default:
2970*4882a593Smuzhiyun goto usb3_delegate;
2971*4882a593Smuzhiyun }
2972*4882a593Smuzhiyun break;
2973*4882a593Smuzhiyun case USB_REQ_SET_FEATURE:
2974*4882a593Smuzhiyun switch (r.bRequestType) {
2975*4882a593Smuzhiyun case (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2976*4882a593Smuzhiyun if (!dev->addressed_state) {
2977*4882a593Smuzhiyun switch (w_value) {
2978*4882a593Smuzhiyun case USB_DEVICE_U1_ENABLE:
2979*4882a593Smuzhiyun dev->u1_enable = 1;
2980*4882a593Smuzhiyun writel(readl(&dev->usb_ext->usbctl2) |
2981*4882a593Smuzhiyun BIT(U1_ENABLE),
2982*4882a593Smuzhiyun &dev->usb_ext->usbctl2);
2983*4882a593Smuzhiyun allow_status_338x(ep);
2984*4882a593Smuzhiyun goto next_endpoints3;
2985*4882a593Smuzhiyun
2986*4882a593Smuzhiyun case USB_DEVICE_U2_ENABLE:
2987*4882a593Smuzhiyun dev->u2_enable = 1;
2988*4882a593Smuzhiyun writel(readl(&dev->usb_ext->usbctl2) |
2989*4882a593Smuzhiyun BIT(U2_ENABLE),
2990*4882a593Smuzhiyun &dev->usb_ext->usbctl2);
2991*4882a593Smuzhiyun allow_status_338x(ep);
2992*4882a593Smuzhiyun goto next_endpoints3;
2993*4882a593Smuzhiyun
2994*4882a593Smuzhiyun case USB_DEVICE_LTM_ENABLE:
2995*4882a593Smuzhiyun dev->ltm_enable = 1;
2996*4882a593Smuzhiyun writel(readl(&dev->usb_ext->usbctl2) |
2997*4882a593Smuzhiyun BIT(LTM_ENABLE),
2998*4882a593Smuzhiyun &dev->usb_ext->usbctl2);
2999*4882a593Smuzhiyun allow_status_338x(ep);
3000*4882a593Smuzhiyun goto next_endpoints3;
3001*4882a593Smuzhiyun default:
3002*4882a593Smuzhiyun break;
3003*4882a593Smuzhiyun }
3004*4882a593Smuzhiyun }
3005*4882a593Smuzhiyun
3006*4882a593Smuzhiyun if (w_value == USB_DEVICE_REMOTE_WAKEUP) {
3007*4882a593Smuzhiyun dev->wakeup_enable = 1;
3008*4882a593Smuzhiyun writel(readl(&dev->usb->usbctl) |
3009*4882a593Smuzhiyun BIT(DEVICE_REMOTE_WAKEUP_ENABLE),
3010*4882a593Smuzhiyun &dev->usb->usbctl);
3011*4882a593Smuzhiyun allow_status_338x(ep);
3012*4882a593Smuzhiyun break;
3013*4882a593Smuzhiyun }
3014*4882a593Smuzhiyun goto usb3_delegate;
3015*4882a593Smuzhiyun
3016*4882a593Smuzhiyun case (USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
3017*4882a593Smuzhiyun e = get_ep_by_addr(dev, w_index);
3018*4882a593Smuzhiyun if (!e || (w_value != USB_ENDPOINT_HALT))
3019*4882a593Smuzhiyun goto do_stall3;
3020*4882a593Smuzhiyun ep->stopped = 1;
3021*4882a593Smuzhiyun if (ep->num == 0)
3022*4882a593Smuzhiyun ep->dev->protocol_stall = 1;
3023*4882a593Smuzhiyun else {
3024*4882a593Smuzhiyun if (ep->dma)
3025*4882a593Smuzhiyun abort_dma(ep);
3026*4882a593Smuzhiyun set_halt(ep);
3027*4882a593Smuzhiyun }
3028*4882a593Smuzhiyun allow_status_338x(ep);
3029*4882a593Smuzhiyun break;
3030*4882a593Smuzhiyun
3031*4882a593Smuzhiyun default:
3032*4882a593Smuzhiyun goto usb3_delegate;
3033*4882a593Smuzhiyun }
3034*4882a593Smuzhiyun
3035*4882a593Smuzhiyun break;
3036*4882a593Smuzhiyun default:
3037*4882a593Smuzhiyun
3038*4882a593Smuzhiyun usb3_delegate:
3039*4882a593Smuzhiyun ep_vdbg(dev, "setup %02x.%02x v%04x i%04x l%04x ep_cfg %08x\n",
3040*4882a593Smuzhiyun r.bRequestType, r.bRequest,
3041*4882a593Smuzhiyun w_value, w_index, w_length,
3042*4882a593Smuzhiyun readl(&ep->cfg->ep_cfg));
3043*4882a593Smuzhiyun
3044*4882a593Smuzhiyun ep->responded = 0;
3045*4882a593Smuzhiyun spin_unlock(&dev->lock);
3046*4882a593Smuzhiyun tmp = dev->driver->setup(&dev->gadget, &r);
3047*4882a593Smuzhiyun spin_lock(&dev->lock);
3048*4882a593Smuzhiyun }
3049*4882a593Smuzhiyun do_stall3:
3050*4882a593Smuzhiyun if (tmp < 0) {
3051*4882a593Smuzhiyun ep_vdbg(dev, "req %02x.%02x protocol STALL; stat %d\n",
3052*4882a593Smuzhiyun r.bRequestType, r.bRequest, tmp);
3053*4882a593Smuzhiyun dev->protocol_stall = 1;
3054*4882a593Smuzhiyun /* TD 9.9 Halt Endpoint test. TD 9.22 Set feature test */
3055*4882a593Smuzhiyun set_halt(ep);
3056*4882a593Smuzhiyun }
3057*4882a593Smuzhiyun
3058*4882a593Smuzhiyun next_endpoints3:
3059*4882a593Smuzhiyun
3060*4882a593Smuzhiyun #undef w_value
3061*4882a593Smuzhiyun #undef w_index
3062*4882a593Smuzhiyun #undef w_length
3063*4882a593Smuzhiyun
3064*4882a593Smuzhiyun return;
3065*4882a593Smuzhiyun }
3066*4882a593Smuzhiyun
usb338x_handle_ep_intr(struct net2280 * dev,u32 stat0)3067*4882a593Smuzhiyun static void usb338x_handle_ep_intr(struct net2280 *dev, u32 stat0)
3068*4882a593Smuzhiyun {
3069*4882a593Smuzhiyun u32 index;
3070*4882a593Smuzhiyun u32 bit;
3071*4882a593Smuzhiyun
3072*4882a593Smuzhiyun for (index = 0; index < ARRAY_SIZE(ep_bit); index++) {
3073*4882a593Smuzhiyun bit = BIT(ep_bit[index]);
3074*4882a593Smuzhiyun
3075*4882a593Smuzhiyun if (!stat0)
3076*4882a593Smuzhiyun break;
3077*4882a593Smuzhiyun
3078*4882a593Smuzhiyun if (!(stat0 & bit))
3079*4882a593Smuzhiyun continue;
3080*4882a593Smuzhiyun
3081*4882a593Smuzhiyun stat0 &= ~bit;
3082*4882a593Smuzhiyun
3083*4882a593Smuzhiyun handle_ep_small(&dev->ep[index]);
3084*4882a593Smuzhiyun }
3085*4882a593Smuzhiyun }
3086*4882a593Smuzhiyun
handle_stat0_irqs(struct net2280 * dev,u32 stat)3087*4882a593Smuzhiyun static void handle_stat0_irqs(struct net2280 *dev, u32 stat)
3088*4882a593Smuzhiyun {
3089*4882a593Smuzhiyun struct net2280_ep *ep;
3090*4882a593Smuzhiyun u32 num, scratch;
3091*4882a593Smuzhiyun
3092*4882a593Smuzhiyun /* most of these don't need individual acks */
3093*4882a593Smuzhiyun stat &= ~BIT(INTA_ASSERTED);
3094*4882a593Smuzhiyun if (!stat)
3095*4882a593Smuzhiyun return;
3096*4882a593Smuzhiyun /* ep_dbg(dev, "irqstat0 %04x\n", stat); */
3097*4882a593Smuzhiyun
3098*4882a593Smuzhiyun /* starting a control request? */
3099*4882a593Smuzhiyun if (unlikely(stat & BIT(SETUP_PACKET_INTERRUPT))) {
3100*4882a593Smuzhiyun union {
3101*4882a593Smuzhiyun u32 raw[2];
3102*4882a593Smuzhiyun struct usb_ctrlrequest r;
3103*4882a593Smuzhiyun } u;
3104*4882a593Smuzhiyun int tmp;
3105*4882a593Smuzhiyun struct net2280_request *req;
3106*4882a593Smuzhiyun
3107*4882a593Smuzhiyun if (dev->gadget.speed == USB_SPEED_UNKNOWN) {
3108*4882a593Smuzhiyun u32 val = readl(&dev->usb->usbstat);
3109*4882a593Smuzhiyun if (val & BIT(SUPER_SPEED)) {
3110*4882a593Smuzhiyun dev->gadget.speed = USB_SPEED_SUPER;
3111*4882a593Smuzhiyun usb_ep_set_maxpacket_limit(&dev->ep[0].ep,
3112*4882a593Smuzhiyun EP0_SS_MAX_PACKET_SIZE);
3113*4882a593Smuzhiyun } else if (val & BIT(HIGH_SPEED)) {
3114*4882a593Smuzhiyun dev->gadget.speed = USB_SPEED_HIGH;
3115*4882a593Smuzhiyun usb_ep_set_maxpacket_limit(&dev->ep[0].ep,
3116*4882a593Smuzhiyun EP0_HS_MAX_PACKET_SIZE);
3117*4882a593Smuzhiyun } else {
3118*4882a593Smuzhiyun dev->gadget.speed = USB_SPEED_FULL;
3119*4882a593Smuzhiyun usb_ep_set_maxpacket_limit(&dev->ep[0].ep,
3120*4882a593Smuzhiyun EP0_HS_MAX_PACKET_SIZE);
3121*4882a593Smuzhiyun }
3122*4882a593Smuzhiyun net2280_led_speed(dev, dev->gadget.speed);
3123*4882a593Smuzhiyun ep_dbg(dev, "%s\n",
3124*4882a593Smuzhiyun usb_speed_string(dev->gadget.speed));
3125*4882a593Smuzhiyun }
3126*4882a593Smuzhiyun
3127*4882a593Smuzhiyun ep = &dev->ep[0];
3128*4882a593Smuzhiyun ep->irqs++;
3129*4882a593Smuzhiyun
3130*4882a593Smuzhiyun /* make sure any leftover request state is cleared */
3131*4882a593Smuzhiyun stat &= ~BIT(ENDPOINT_0_INTERRUPT);
3132*4882a593Smuzhiyun while (!list_empty(&ep->queue)) {
3133*4882a593Smuzhiyun req = list_entry(ep->queue.next,
3134*4882a593Smuzhiyun struct net2280_request, queue);
3135*4882a593Smuzhiyun done(ep, req, (req->req.actual == req->req.length)
3136*4882a593Smuzhiyun ? 0 : -EPROTO);
3137*4882a593Smuzhiyun }
3138*4882a593Smuzhiyun ep->stopped = 0;
3139*4882a593Smuzhiyun dev->protocol_stall = 0;
3140*4882a593Smuzhiyun if (!(dev->quirks & PLX_PCIE)) {
3141*4882a593Smuzhiyun if (ep->dev->quirks & PLX_2280)
3142*4882a593Smuzhiyun tmp = BIT(FIFO_OVERFLOW) |
3143*4882a593Smuzhiyun BIT(FIFO_UNDERFLOW);
3144*4882a593Smuzhiyun else
3145*4882a593Smuzhiyun tmp = 0;
3146*4882a593Smuzhiyun
3147*4882a593Smuzhiyun writel(tmp | BIT(TIMEOUT) |
3148*4882a593Smuzhiyun BIT(USB_STALL_SENT) |
3149*4882a593Smuzhiyun BIT(USB_IN_NAK_SENT) |
3150*4882a593Smuzhiyun BIT(USB_IN_ACK_RCVD) |
3151*4882a593Smuzhiyun BIT(USB_OUT_PING_NAK_SENT) |
3152*4882a593Smuzhiyun BIT(USB_OUT_ACK_SENT) |
3153*4882a593Smuzhiyun BIT(SHORT_PACKET_OUT_DONE_INTERRUPT) |
3154*4882a593Smuzhiyun BIT(SHORT_PACKET_TRANSFERRED_INTERRUPT) |
3155*4882a593Smuzhiyun BIT(DATA_PACKET_RECEIVED_INTERRUPT) |
3156*4882a593Smuzhiyun BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) |
3157*4882a593Smuzhiyun BIT(DATA_OUT_PING_TOKEN_INTERRUPT) |
3158*4882a593Smuzhiyun BIT(DATA_IN_TOKEN_INTERRUPT),
3159*4882a593Smuzhiyun &ep->regs->ep_stat);
3160*4882a593Smuzhiyun }
3161*4882a593Smuzhiyun u.raw[0] = readl(&dev->usb->setup0123);
3162*4882a593Smuzhiyun u.raw[1] = readl(&dev->usb->setup4567);
3163*4882a593Smuzhiyun
3164*4882a593Smuzhiyun cpu_to_le32s(&u.raw[0]);
3165*4882a593Smuzhiyun cpu_to_le32s(&u.raw[1]);
3166*4882a593Smuzhiyun
3167*4882a593Smuzhiyun if ((dev->quirks & PLX_PCIE) && !dev->bug7734_patched)
3168*4882a593Smuzhiyun defect7374_workaround(dev, u.r);
3169*4882a593Smuzhiyun
3170*4882a593Smuzhiyun tmp = 0;
3171*4882a593Smuzhiyun
3172*4882a593Smuzhiyun #define w_value le16_to_cpu(u.r.wValue)
3173*4882a593Smuzhiyun #define w_index le16_to_cpu(u.r.wIndex)
3174*4882a593Smuzhiyun #define w_length le16_to_cpu(u.r.wLength)
3175*4882a593Smuzhiyun
3176*4882a593Smuzhiyun /* ack the irq */
3177*4882a593Smuzhiyun writel(BIT(SETUP_PACKET_INTERRUPT), &dev->regs->irqstat0);
3178*4882a593Smuzhiyun stat ^= BIT(SETUP_PACKET_INTERRUPT);
3179*4882a593Smuzhiyun
3180*4882a593Smuzhiyun /* watch control traffic at the token level, and force
3181*4882a593Smuzhiyun * synchronization before letting the status stage happen.
3182*4882a593Smuzhiyun * FIXME ignore tokens we'll NAK, until driver responds.
3183*4882a593Smuzhiyun * that'll mean a lot less irqs for some drivers.
3184*4882a593Smuzhiyun */
3185*4882a593Smuzhiyun ep->is_in = (u.r.bRequestType & USB_DIR_IN) != 0;
3186*4882a593Smuzhiyun if (ep->is_in) {
3187*4882a593Smuzhiyun scratch = BIT(DATA_PACKET_TRANSMITTED_INTERRUPT) |
3188*4882a593Smuzhiyun BIT(DATA_OUT_PING_TOKEN_INTERRUPT) |
3189*4882a593Smuzhiyun BIT(DATA_IN_TOKEN_INTERRUPT);
3190*4882a593Smuzhiyun stop_out_naking(ep);
3191*4882a593Smuzhiyun } else
3192*4882a593Smuzhiyun scratch = BIT(DATA_PACKET_RECEIVED_INTERRUPT) |
3193*4882a593Smuzhiyun BIT(DATA_OUT_PING_TOKEN_INTERRUPT) |
3194*4882a593Smuzhiyun BIT(DATA_IN_TOKEN_INTERRUPT);
3195*4882a593Smuzhiyun writel(scratch, &dev->epregs[0].ep_irqenb);
3196*4882a593Smuzhiyun
3197*4882a593Smuzhiyun /* we made the hardware handle most lowlevel requests;
3198*4882a593Smuzhiyun * everything else goes uplevel to the gadget code.
3199*4882a593Smuzhiyun */
3200*4882a593Smuzhiyun ep->responded = 1;
3201*4882a593Smuzhiyun
3202*4882a593Smuzhiyun if (dev->gadget.speed == USB_SPEED_SUPER) {
3203*4882a593Smuzhiyun handle_stat0_irqs_superspeed(dev, ep, u.r);
3204*4882a593Smuzhiyun goto next_endpoints;
3205*4882a593Smuzhiyun }
3206*4882a593Smuzhiyun
3207*4882a593Smuzhiyun switch (u.r.bRequest) {
3208*4882a593Smuzhiyun case USB_REQ_GET_STATUS: {
3209*4882a593Smuzhiyun struct net2280_ep *e;
3210*4882a593Smuzhiyun __le32 status;
3211*4882a593Smuzhiyun
3212*4882a593Smuzhiyun /* hw handles device and interface status */
3213*4882a593Smuzhiyun if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
3214*4882a593Smuzhiyun goto delegate;
3215*4882a593Smuzhiyun e = get_ep_by_addr(dev, w_index);
3216*4882a593Smuzhiyun if (!e || w_length > 2)
3217*4882a593Smuzhiyun goto do_stall;
3218*4882a593Smuzhiyun
3219*4882a593Smuzhiyun if (readl(&e->regs->ep_rsp) & BIT(SET_ENDPOINT_HALT))
3220*4882a593Smuzhiyun status = cpu_to_le32(1);
3221*4882a593Smuzhiyun else
3222*4882a593Smuzhiyun status = cpu_to_le32(0);
3223*4882a593Smuzhiyun
3224*4882a593Smuzhiyun /* don't bother with a request object! */
3225*4882a593Smuzhiyun writel(0, &dev->epregs[0].ep_irqenb);
3226*4882a593Smuzhiyun set_fifo_bytecount(ep, w_length);
3227*4882a593Smuzhiyun writel((__force u32)status, &dev->epregs[0].ep_data);
3228*4882a593Smuzhiyun allow_status(ep);
3229*4882a593Smuzhiyun ep_vdbg(dev, "%s stat %02x\n", ep->ep.name, status);
3230*4882a593Smuzhiyun goto next_endpoints;
3231*4882a593Smuzhiyun }
3232*4882a593Smuzhiyun break;
3233*4882a593Smuzhiyun case USB_REQ_CLEAR_FEATURE: {
3234*4882a593Smuzhiyun struct net2280_ep *e;
3235*4882a593Smuzhiyun
3236*4882a593Smuzhiyun /* hw handles device features */
3237*4882a593Smuzhiyun if (u.r.bRequestType != USB_RECIP_ENDPOINT)
3238*4882a593Smuzhiyun goto delegate;
3239*4882a593Smuzhiyun if (w_value != USB_ENDPOINT_HALT || w_length != 0)
3240*4882a593Smuzhiyun goto do_stall;
3241*4882a593Smuzhiyun e = get_ep_by_addr(dev, w_index);
3242*4882a593Smuzhiyun if (!e)
3243*4882a593Smuzhiyun goto do_stall;
3244*4882a593Smuzhiyun if (e->wedged) {
3245*4882a593Smuzhiyun ep_vdbg(dev, "%s wedged, halt not cleared\n",
3246*4882a593Smuzhiyun ep->ep.name);
3247*4882a593Smuzhiyun } else {
3248*4882a593Smuzhiyun ep_vdbg(dev, "%s clear halt\n", e->ep.name);
3249*4882a593Smuzhiyun clear_halt(e);
3250*4882a593Smuzhiyun if ((ep->dev->quirks & PLX_PCIE) &&
3251*4882a593Smuzhiyun !list_empty(&e->queue) && e->td_dma)
3252*4882a593Smuzhiyun restart_dma(e);
3253*4882a593Smuzhiyun }
3254*4882a593Smuzhiyun allow_status(ep);
3255*4882a593Smuzhiyun goto next_endpoints;
3256*4882a593Smuzhiyun }
3257*4882a593Smuzhiyun break;
3258*4882a593Smuzhiyun case USB_REQ_SET_FEATURE: {
3259*4882a593Smuzhiyun struct net2280_ep *e;
3260*4882a593Smuzhiyun
3261*4882a593Smuzhiyun /* hw handles device features */
3262*4882a593Smuzhiyun if (u.r.bRequestType != USB_RECIP_ENDPOINT)
3263*4882a593Smuzhiyun goto delegate;
3264*4882a593Smuzhiyun if (w_value != USB_ENDPOINT_HALT || w_length != 0)
3265*4882a593Smuzhiyun goto do_stall;
3266*4882a593Smuzhiyun e = get_ep_by_addr(dev, w_index);
3267*4882a593Smuzhiyun if (!e)
3268*4882a593Smuzhiyun goto do_stall;
3269*4882a593Smuzhiyun if (e->ep.name == ep0name)
3270*4882a593Smuzhiyun goto do_stall;
3271*4882a593Smuzhiyun set_halt(e);
3272*4882a593Smuzhiyun if ((dev->quirks & PLX_PCIE) && e->dma)
3273*4882a593Smuzhiyun abort_dma(e);
3274*4882a593Smuzhiyun allow_status(ep);
3275*4882a593Smuzhiyun ep_vdbg(dev, "%s set halt\n", ep->ep.name);
3276*4882a593Smuzhiyun goto next_endpoints;
3277*4882a593Smuzhiyun }
3278*4882a593Smuzhiyun break;
3279*4882a593Smuzhiyun default:
3280*4882a593Smuzhiyun delegate:
3281*4882a593Smuzhiyun ep_vdbg(dev, "setup %02x.%02x v%04x i%04x l%04x "
3282*4882a593Smuzhiyun "ep_cfg %08x\n",
3283*4882a593Smuzhiyun u.r.bRequestType, u.r.bRequest,
3284*4882a593Smuzhiyun w_value, w_index, w_length,
3285*4882a593Smuzhiyun readl(&ep->cfg->ep_cfg));
3286*4882a593Smuzhiyun ep->responded = 0;
3287*4882a593Smuzhiyun spin_unlock(&dev->lock);
3288*4882a593Smuzhiyun tmp = dev->driver->setup(&dev->gadget, &u.r);
3289*4882a593Smuzhiyun spin_lock(&dev->lock);
3290*4882a593Smuzhiyun }
3291*4882a593Smuzhiyun
3292*4882a593Smuzhiyun /* stall ep0 on error */
3293*4882a593Smuzhiyun if (tmp < 0) {
3294*4882a593Smuzhiyun do_stall:
3295*4882a593Smuzhiyun ep_vdbg(dev, "req %02x.%02x protocol STALL; stat %d\n",
3296*4882a593Smuzhiyun u.r.bRequestType, u.r.bRequest, tmp);
3297*4882a593Smuzhiyun dev->protocol_stall = 1;
3298*4882a593Smuzhiyun }
3299*4882a593Smuzhiyun
3300*4882a593Smuzhiyun /* some in/out token irq should follow; maybe stall then.
3301*4882a593Smuzhiyun * driver must queue a request (even zlp) or halt ep0
3302*4882a593Smuzhiyun * before the host times out.
3303*4882a593Smuzhiyun */
3304*4882a593Smuzhiyun }
3305*4882a593Smuzhiyun
3306*4882a593Smuzhiyun #undef w_value
3307*4882a593Smuzhiyun #undef w_index
3308*4882a593Smuzhiyun #undef w_length
3309*4882a593Smuzhiyun
3310*4882a593Smuzhiyun next_endpoints:
3311*4882a593Smuzhiyun if ((dev->quirks & PLX_PCIE) && dev->enhanced_mode) {
3312*4882a593Smuzhiyun u32 mask = (BIT(ENDPOINT_0_INTERRUPT) |
3313*4882a593Smuzhiyun USB3380_IRQSTAT0_EP_INTR_MASK_IN |
3314*4882a593Smuzhiyun USB3380_IRQSTAT0_EP_INTR_MASK_OUT);
3315*4882a593Smuzhiyun
3316*4882a593Smuzhiyun if (stat & mask) {
3317*4882a593Smuzhiyun usb338x_handle_ep_intr(dev, stat & mask);
3318*4882a593Smuzhiyun stat &= ~mask;
3319*4882a593Smuzhiyun }
3320*4882a593Smuzhiyun } else {
3321*4882a593Smuzhiyun /* endpoint data irq ? */
3322*4882a593Smuzhiyun scratch = stat & 0x7f;
3323*4882a593Smuzhiyun stat &= ~0x7f;
3324*4882a593Smuzhiyun for (num = 0; scratch; num++) {
3325*4882a593Smuzhiyun u32 t;
3326*4882a593Smuzhiyun
3327*4882a593Smuzhiyun /* do this endpoint's FIFO and queue need tending? */
3328*4882a593Smuzhiyun t = BIT(num);
3329*4882a593Smuzhiyun if ((scratch & t) == 0)
3330*4882a593Smuzhiyun continue;
3331*4882a593Smuzhiyun scratch ^= t;
3332*4882a593Smuzhiyun
3333*4882a593Smuzhiyun ep = &dev->ep[num];
3334*4882a593Smuzhiyun handle_ep_small(ep);
3335*4882a593Smuzhiyun }
3336*4882a593Smuzhiyun }
3337*4882a593Smuzhiyun
3338*4882a593Smuzhiyun if (stat)
3339*4882a593Smuzhiyun ep_dbg(dev, "unhandled irqstat0 %08x\n", stat);
3340*4882a593Smuzhiyun }
3341*4882a593Smuzhiyun
3342*4882a593Smuzhiyun #define DMA_INTERRUPTS (BIT(DMA_D_INTERRUPT) | \
3343*4882a593Smuzhiyun BIT(DMA_C_INTERRUPT) | \
3344*4882a593Smuzhiyun BIT(DMA_B_INTERRUPT) | \
3345*4882a593Smuzhiyun BIT(DMA_A_INTERRUPT))
3346*4882a593Smuzhiyun #define PCI_ERROR_INTERRUPTS ( \
3347*4882a593Smuzhiyun BIT(PCI_MASTER_ABORT_RECEIVED_INTERRUPT) | \
3348*4882a593Smuzhiyun BIT(PCI_TARGET_ABORT_RECEIVED_INTERRUPT) | \
3349*4882a593Smuzhiyun BIT(PCI_RETRY_ABORT_INTERRUPT))
3350*4882a593Smuzhiyun
handle_stat1_irqs(struct net2280 * dev,u32 stat)3351*4882a593Smuzhiyun static void handle_stat1_irqs(struct net2280 *dev, u32 stat)
3352*4882a593Smuzhiyun __releases(dev->lock)
3353*4882a593Smuzhiyun __acquires(dev->lock)
3354*4882a593Smuzhiyun {
3355*4882a593Smuzhiyun struct net2280_ep *ep;
3356*4882a593Smuzhiyun u32 tmp, num, mask, scratch;
3357*4882a593Smuzhiyun
3358*4882a593Smuzhiyun /* after disconnect there's nothing else to do! */
3359*4882a593Smuzhiyun tmp = BIT(VBUS_INTERRUPT) | BIT(ROOT_PORT_RESET_INTERRUPT);
3360*4882a593Smuzhiyun mask = BIT(SUPER_SPEED) | BIT(HIGH_SPEED) | BIT(FULL_SPEED);
3361*4882a593Smuzhiyun
3362*4882a593Smuzhiyun /* VBUS disconnect is indicated by VBUS_PIN and VBUS_INTERRUPT set.
3363*4882a593Smuzhiyun * Root Port Reset is indicated by ROOT_PORT_RESET_INTERRUPT set and
3364*4882a593Smuzhiyun * both HIGH_SPEED and FULL_SPEED clear (as ROOT_PORT_RESET_INTERRUPT
3365*4882a593Smuzhiyun * only indicates a change in the reset state).
3366*4882a593Smuzhiyun */
3367*4882a593Smuzhiyun if (stat & tmp) {
3368*4882a593Smuzhiyun bool reset = false;
3369*4882a593Smuzhiyun bool disconnect = false;
3370*4882a593Smuzhiyun
3371*4882a593Smuzhiyun /*
3372*4882a593Smuzhiyun * Ignore disconnects and resets if the speed hasn't been set.
3373*4882a593Smuzhiyun * VBUS can bounce and there's always an initial reset.
3374*4882a593Smuzhiyun */
3375*4882a593Smuzhiyun writel(tmp, &dev->regs->irqstat1);
3376*4882a593Smuzhiyun if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
3377*4882a593Smuzhiyun if ((stat & BIT(VBUS_INTERRUPT)) &&
3378*4882a593Smuzhiyun (readl(&dev->usb->usbctl) &
3379*4882a593Smuzhiyun BIT(VBUS_PIN)) == 0) {
3380*4882a593Smuzhiyun disconnect = true;
3381*4882a593Smuzhiyun ep_dbg(dev, "disconnect %s\n",
3382*4882a593Smuzhiyun dev->driver->driver.name);
3383*4882a593Smuzhiyun } else if ((stat & BIT(ROOT_PORT_RESET_INTERRUPT)) &&
3384*4882a593Smuzhiyun (readl(&dev->usb->usbstat) & mask)
3385*4882a593Smuzhiyun == 0) {
3386*4882a593Smuzhiyun reset = true;
3387*4882a593Smuzhiyun ep_dbg(dev, "reset %s\n",
3388*4882a593Smuzhiyun dev->driver->driver.name);
3389*4882a593Smuzhiyun }
3390*4882a593Smuzhiyun
3391*4882a593Smuzhiyun if (disconnect || reset) {
3392*4882a593Smuzhiyun stop_activity(dev, dev->driver);
3393*4882a593Smuzhiyun ep0_start(dev);
3394*4882a593Smuzhiyun spin_unlock(&dev->lock);
3395*4882a593Smuzhiyun if (reset)
3396*4882a593Smuzhiyun usb_gadget_udc_reset
3397*4882a593Smuzhiyun (&dev->gadget, dev->driver);
3398*4882a593Smuzhiyun else
3399*4882a593Smuzhiyun (dev->driver->disconnect)
3400*4882a593Smuzhiyun (&dev->gadget);
3401*4882a593Smuzhiyun spin_lock(&dev->lock);
3402*4882a593Smuzhiyun return;
3403*4882a593Smuzhiyun }
3404*4882a593Smuzhiyun }
3405*4882a593Smuzhiyun stat &= ~tmp;
3406*4882a593Smuzhiyun
3407*4882a593Smuzhiyun /* vBUS can bounce ... one of many reasons to ignore the
3408*4882a593Smuzhiyun * notion of hotplug events on bus connect/disconnect!
3409*4882a593Smuzhiyun */
3410*4882a593Smuzhiyun if (!stat)
3411*4882a593Smuzhiyun return;
3412*4882a593Smuzhiyun }
3413*4882a593Smuzhiyun
3414*4882a593Smuzhiyun /* NOTE: chip stays in PCI D0 state for now, but it could
3415*4882a593Smuzhiyun * enter D1 to save more power
3416*4882a593Smuzhiyun */
3417*4882a593Smuzhiyun tmp = BIT(SUSPEND_REQUEST_CHANGE_INTERRUPT);
3418*4882a593Smuzhiyun if (stat & tmp) {
3419*4882a593Smuzhiyun writel(tmp, &dev->regs->irqstat1);
3420*4882a593Smuzhiyun spin_unlock(&dev->lock);
3421*4882a593Smuzhiyun if (stat & BIT(SUSPEND_REQUEST_INTERRUPT)) {
3422*4882a593Smuzhiyun if (dev->driver->suspend)
3423*4882a593Smuzhiyun dev->driver->suspend(&dev->gadget);
3424*4882a593Smuzhiyun if (!enable_suspend)
3425*4882a593Smuzhiyun stat &= ~BIT(SUSPEND_REQUEST_INTERRUPT);
3426*4882a593Smuzhiyun } else {
3427*4882a593Smuzhiyun if (dev->driver->resume)
3428*4882a593Smuzhiyun dev->driver->resume(&dev->gadget);
3429*4882a593Smuzhiyun /* at high speed, note erratum 0133 */
3430*4882a593Smuzhiyun }
3431*4882a593Smuzhiyun spin_lock(&dev->lock);
3432*4882a593Smuzhiyun stat &= ~tmp;
3433*4882a593Smuzhiyun }
3434*4882a593Smuzhiyun
3435*4882a593Smuzhiyun /* clear any other status/irqs */
3436*4882a593Smuzhiyun if (stat)
3437*4882a593Smuzhiyun writel(stat, &dev->regs->irqstat1);
3438*4882a593Smuzhiyun
3439*4882a593Smuzhiyun /* some status we can just ignore */
3440*4882a593Smuzhiyun if (dev->quirks & PLX_2280)
3441*4882a593Smuzhiyun stat &= ~(BIT(CONTROL_STATUS_INTERRUPT) |
3442*4882a593Smuzhiyun BIT(SUSPEND_REQUEST_INTERRUPT) |
3443*4882a593Smuzhiyun BIT(RESUME_INTERRUPT) |
3444*4882a593Smuzhiyun BIT(SOF_INTERRUPT));
3445*4882a593Smuzhiyun else
3446*4882a593Smuzhiyun stat &= ~(BIT(CONTROL_STATUS_INTERRUPT) |
3447*4882a593Smuzhiyun BIT(RESUME_INTERRUPT) |
3448*4882a593Smuzhiyun BIT(SOF_DOWN_INTERRUPT) |
3449*4882a593Smuzhiyun BIT(SOF_INTERRUPT));
3450*4882a593Smuzhiyun
3451*4882a593Smuzhiyun if (!stat)
3452*4882a593Smuzhiyun return;
3453*4882a593Smuzhiyun /* ep_dbg(dev, "irqstat1 %08x\n", stat);*/
3454*4882a593Smuzhiyun
3455*4882a593Smuzhiyun /* DMA status, for ep-{a,b,c,d} */
3456*4882a593Smuzhiyun scratch = stat & DMA_INTERRUPTS;
3457*4882a593Smuzhiyun stat &= ~DMA_INTERRUPTS;
3458*4882a593Smuzhiyun scratch >>= 9;
3459*4882a593Smuzhiyun for (num = 0; scratch; num++) {
3460*4882a593Smuzhiyun struct net2280_dma_regs __iomem *dma;
3461*4882a593Smuzhiyun
3462*4882a593Smuzhiyun tmp = BIT(num);
3463*4882a593Smuzhiyun if ((tmp & scratch) == 0)
3464*4882a593Smuzhiyun continue;
3465*4882a593Smuzhiyun scratch ^= tmp;
3466*4882a593Smuzhiyun
3467*4882a593Smuzhiyun ep = &dev->ep[num + 1];
3468*4882a593Smuzhiyun dma = ep->dma;
3469*4882a593Smuzhiyun
3470*4882a593Smuzhiyun if (!dma)
3471*4882a593Smuzhiyun continue;
3472*4882a593Smuzhiyun
3473*4882a593Smuzhiyun /* clear ep's dma status */
3474*4882a593Smuzhiyun tmp = readl(&dma->dmastat);
3475*4882a593Smuzhiyun writel(tmp, &dma->dmastat);
3476*4882a593Smuzhiyun
3477*4882a593Smuzhiyun /* dma sync*/
3478*4882a593Smuzhiyun if (dev->quirks & PLX_PCIE) {
3479*4882a593Smuzhiyun u32 r_dmacount = readl(&dma->dmacount);
3480*4882a593Smuzhiyun if (!ep->is_in && (r_dmacount & 0x00FFFFFF) &&
3481*4882a593Smuzhiyun (tmp & BIT(DMA_TRANSACTION_DONE_INTERRUPT)))
3482*4882a593Smuzhiyun continue;
3483*4882a593Smuzhiyun }
3484*4882a593Smuzhiyun
3485*4882a593Smuzhiyun if (!(tmp & BIT(DMA_TRANSACTION_DONE_INTERRUPT))) {
3486*4882a593Smuzhiyun ep_dbg(ep->dev, "%s no xact done? %08x\n",
3487*4882a593Smuzhiyun ep->ep.name, tmp);
3488*4882a593Smuzhiyun continue;
3489*4882a593Smuzhiyun }
3490*4882a593Smuzhiyun stop_dma(ep->dma);
3491*4882a593Smuzhiyun
3492*4882a593Smuzhiyun /* OUT transfers terminate when the data from the
3493*4882a593Smuzhiyun * host is in our memory. Process whatever's done.
3494*4882a593Smuzhiyun * On this path, we know transfer's last packet wasn't
3495*4882a593Smuzhiyun * less than req->length. NAK_OUT_PACKETS may be set,
3496*4882a593Smuzhiyun * or the FIFO may already be holding new packets.
3497*4882a593Smuzhiyun *
3498*4882a593Smuzhiyun * IN transfers can linger in the FIFO for a very
3499*4882a593Smuzhiyun * long time ... we ignore that for now, accounting
3500*4882a593Smuzhiyun * precisely (like PIO does) needs per-packet irqs
3501*4882a593Smuzhiyun */
3502*4882a593Smuzhiyun scan_dma_completions(ep);
3503*4882a593Smuzhiyun
3504*4882a593Smuzhiyun /* disable dma on inactive queues; else maybe restart */
3505*4882a593Smuzhiyun if (!list_empty(&ep->queue)) {
3506*4882a593Smuzhiyun tmp = readl(&dma->dmactl);
3507*4882a593Smuzhiyun restart_dma(ep);
3508*4882a593Smuzhiyun }
3509*4882a593Smuzhiyun ep->irqs++;
3510*4882a593Smuzhiyun }
3511*4882a593Smuzhiyun
3512*4882a593Smuzhiyun /* NOTE: there are other PCI errors we might usefully notice.
3513*4882a593Smuzhiyun * if they appear very often, here's where to try recovering.
3514*4882a593Smuzhiyun */
3515*4882a593Smuzhiyun if (stat & PCI_ERROR_INTERRUPTS) {
3516*4882a593Smuzhiyun ep_err(dev, "pci dma error; stat %08x\n", stat);
3517*4882a593Smuzhiyun stat &= ~PCI_ERROR_INTERRUPTS;
3518*4882a593Smuzhiyun /* these are fatal errors, but "maybe" they won't
3519*4882a593Smuzhiyun * happen again ...
3520*4882a593Smuzhiyun */
3521*4882a593Smuzhiyun stop_activity(dev, dev->driver);
3522*4882a593Smuzhiyun ep0_start(dev);
3523*4882a593Smuzhiyun stat = 0;
3524*4882a593Smuzhiyun }
3525*4882a593Smuzhiyun
3526*4882a593Smuzhiyun if (stat)
3527*4882a593Smuzhiyun ep_dbg(dev, "unhandled irqstat1 %08x\n", stat);
3528*4882a593Smuzhiyun }
3529*4882a593Smuzhiyun
net2280_irq(int irq,void * _dev)3530*4882a593Smuzhiyun static irqreturn_t net2280_irq(int irq, void *_dev)
3531*4882a593Smuzhiyun {
3532*4882a593Smuzhiyun struct net2280 *dev = _dev;
3533*4882a593Smuzhiyun
3534*4882a593Smuzhiyun /* shared interrupt, not ours */
3535*4882a593Smuzhiyun if ((dev->quirks & PLX_LEGACY) &&
3536*4882a593Smuzhiyun (!(readl(&dev->regs->irqstat0) & BIT(INTA_ASSERTED))))
3537*4882a593Smuzhiyun return IRQ_NONE;
3538*4882a593Smuzhiyun
3539*4882a593Smuzhiyun spin_lock(&dev->lock);
3540*4882a593Smuzhiyun
3541*4882a593Smuzhiyun /* handle disconnect, dma, and more */
3542*4882a593Smuzhiyun handle_stat1_irqs(dev, readl(&dev->regs->irqstat1));
3543*4882a593Smuzhiyun
3544*4882a593Smuzhiyun /* control requests and PIO */
3545*4882a593Smuzhiyun handle_stat0_irqs(dev, readl(&dev->regs->irqstat0));
3546*4882a593Smuzhiyun
3547*4882a593Smuzhiyun if (dev->quirks & PLX_PCIE) {
3548*4882a593Smuzhiyun /* re-enable interrupt to trigger any possible new interrupt */
3549*4882a593Smuzhiyun u32 pciirqenb1 = readl(&dev->regs->pciirqenb1);
3550*4882a593Smuzhiyun writel(pciirqenb1 & 0x7FFFFFFF, &dev->regs->pciirqenb1);
3551*4882a593Smuzhiyun writel(pciirqenb1, &dev->regs->pciirqenb1);
3552*4882a593Smuzhiyun }
3553*4882a593Smuzhiyun
3554*4882a593Smuzhiyun spin_unlock(&dev->lock);
3555*4882a593Smuzhiyun
3556*4882a593Smuzhiyun return IRQ_HANDLED;
3557*4882a593Smuzhiyun }
3558*4882a593Smuzhiyun
3559*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
3560*4882a593Smuzhiyun
gadget_release(struct device * _dev)3561*4882a593Smuzhiyun static void gadget_release(struct device *_dev)
3562*4882a593Smuzhiyun {
3563*4882a593Smuzhiyun struct net2280 *dev = container_of(_dev, struct net2280, gadget.dev);
3564*4882a593Smuzhiyun
3565*4882a593Smuzhiyun kfree(dev);
3566*4882a593Smuzhiyun }
3567*4882a593Smuzhiyun
3568*4882a593Smuzhiyun /* tear down the binding between this driver and the pci device */
3569*4882a593Smuzhiyun
net2280_remove(struct pci_dev * pdev)3570*4882a593Smuzhiyun static void net2280_remove(struct pci_dev *pdev)
3571*4882a593Smuzhiyun {
3572*4882a593Smuzhiyun struct net2280 *dev = pci_get_drvdata(pdev);
3573*4882a593Smuzhiyun
3574*4882a593Smuzhiyun if (dev->added)
3575*4882a593Smuzhiyun usb_del_gadget(&dev->gadget);
3576*4882a593Smuzhiyun
3577*4882a593Smuzhiyun BUG_ON(dev->driver);
3578*4882a593Smuzhiyun
3579*4882a593Smuzhiyun /* then clean up the resources we allocated during probe() */
3580*4882a593Smuzhiyun if (dev->requests) {
3581*4882a593Smuzhiyun int i;
3582*4882a593Smuzhiyun for (i = 1; i < 5; i++) {
3583*4882a593Smuzhiyun if (!dev->ep[i].dummy)
3584*4882a593Smuzhiyun continue;
3585*4882a593Smuzhiyun dma_pool_free(dev->requests, dev->ep[i].dummy,
3586*4882a593Smuzhiyun dev->ep[i].td_dma);
3587*4882a593Smuzhiyun }
3588*4882a593Smuzhiyun dma_pool_destroy(dev->requests);
3589*4882a593Smuzhiyun }
3590*4882a593Smuzhiyun if (dev->got_irq)
3591*4882a593Smuzhiyun free_irq(pdev->irq, dev);
3592*4882a593Smuzhiyun if (dev->quirks & PLX_PCIE)
3593*4882a593Smuzhiyun pci_disable_msi(pdev);
3594*4882a593Smuzhiyun if (dev->regs) {
3595*4882a593Smuzhiyun net2280_led_shutdown(dev);
3596*4882a593Smuzhiyun iounmap(dev->regs);
3597*4882a593Smuzhiyun }
3598*4882a593Smuzhiyun if (dev->region)
3599*4882a593Smuzhiyun release_mem_region(pci_resource_start(pdev, 0),
3600*4882a593Smuzhiyun pci_resource_len(pdev, 0));
3601*4882a593Smuzhiyun if (dev->enabled)
3602*4882a593Smuzhiyun pci_disable_device(pdev);
3603*4882a593Smuzhiyun device_remove_file(&pdev->dev, &dev_attr_registers);
3604*4882a593Smuzhiyun
3605*4882a593Smuzhiyun ep_info(dev, "unbind\n");
3606*4882a593Smuzhiyun usb_put_gadget(&dev->gadget);
3607*4882a593Smuzhiyun }
3608*4882a593Smuzhiyun
3609*4882a593Smuzhiyun /* wrap this driver around the specified device, but
3610*4882a593Smuzhiyun * don't respond over USB until a gadget driver binds to us.
3611*4882a593Smuzhiyun */
3612*4882a593Smuzhiyun
net2280_probe(struct pci_dev * pdev,const struct pci_device_id * id)3613*4882a593Smuzhiyun static int net2280_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3614*4882a593Smuzhiyun {
3615*4882a593Smuzhiyun struct net2280 *dev;
3616*4882a593Smuzhiyun unsigned long resource, len;
3617*4882a593Smuzhiyun void __iomem *base = NULL;
3618*4882a593Smuzhiyun int retval, i;
3619*4882a593Smuzhiyun
3620*4882a593Smuzhiyun /* alloc, and start init */
3621*4882a593Smuzhiyun dev = kzalloc(sizeof(*dev), GFP_KERNEL);
3622*4882a593Smuzhiyun if (dev == NULL) {
3623*4882a593Smuzhiyun retval = -ENOMEM;
3624*4882a593Smuzhiyun goto done;
3625*4882a593Smuzhiyun }
3626*4882a593Smuzhiyun
3627*4882a593Smuzhiyun pci_set_drvdata(pdev, dev);
3628*4882a593Smuzhiyun usb_initialize_gadget(&pdev->dev, &dev->gadget, gadget_release);
3629*4882a593Smuzhiyun spin_lock_init(&dev->lock);
3630*4882a593Smuzhiyun dev->quirks = id->driver_data;
3631*4882a593Smuzhiyun dev->pdev = pdev;
3632*4882a593Smuzhiyun dev->gadget.ops = &net2280_ops;
3633*4882a593Smuzhiyun dev->gadget.max_speed = (dev->quirks & PLX_SUPERSPEED) ?
3634*4882a593Smuzhiyun USB_SPEED_SUPER : USB_SPEED_HIGH;
3635*4882a593Smuzhiyun
3636*4882a593Smuzhiyun /* the "gadget" abstracts/virtualizes the controller */
3637*4882a593Smuzhiyun dev->gadget.name = driver_name;
3638*4882a593Smuzhiyun
3639*4882a593Smuzhiyun /* now all the pci goodies ... */
3640*4882a593Smuzhiyun if (pci_enable_device(pdev) < 0) {
3641*4882a593Smuzhiyun retval = -ENODEV;
3642*4882a593Smuzhiyun goto done;
3643*4882a593Smuzhiyun }
3644*4882a593Smuzhiyun dev->enabled = 1;
3645*4882a593Smuzhiyun
3646*4882a593Smuzhiyun /* BAR 0 holds all the registers
3647*4882a593Smuzhiyun * BAR 1 is 8051 memory; unused here (note erratum 0103)
3648*4882a593Smuzhiyun * BAR 2 is fifo memory; unused here
3649*4882a593Smuzhiyun */
3650*4882a593Smuzhiyun resource = pci_resource_start(pdev, 0);
3651*4882a593Smuzhiyun len = pci_resource_len(pdev, 0);
3652*4882a593Smuzhiyun if (!request_mem_region(resource, len, driver_name)) {
3653*4882a593Smuzhiyun ep_dbg(dev, "controller already in use\n");
3654*4882a593Smuzhiyun retval = -EBUSY;
3655*4882a593Smuzhiyun goto done;
3656*4882a593Smuzhiyun }
3657*4882a593Smuzhiyun dev->region = 1;
3658*4882a593Smuzhiyun
3659*4882a593Smuzhiyun /* FIXME provide firmware download interface to put
3660*4882a593Smuzhiyun * 8051 code into the chip, e.g. to turn on PCI PM.
3661*4882a593Smuzhiyun */
3662*4882a593Smuzhiyun
3663*4882a593Smuzhiyun base = ioremap(resource, len);
3664*4882a593Smuzhiyun if (base == NULL) {
3665*4882a593Smuzhiyun ep_dbg(dev, "can't map memory\n");
3666*4882a593Smuzhiyun retval = -EFAULT;
3667*4882a593Smuzhiyun goto done;
3668*4882a593Smuzhiyun }
3669*4882a593Smuzhiyun dev->regs = (struct net2280_regs __iomem *) base;
3670*4882a593Smuzhiyun dev->usb = (struct net2280_usb_regs __iomem *) (base + 0x0080);
3671*4882a593Smuzhiyun dev->pci = (struct net2280_pci_regs __iomem *) (base + 0x0100);
3672*4882a593Smuzhiyun dev->dma = (struct net2280_dma_regs __iomem *) (base + 0x0180);
3673*4882a593Smuzhiyun dev->dep = (struct net2280_dep_regs __iomem *) (base + 0x0200);
3674*4882a593Smuzhiyun dev->epregs = (struct net2280_ep_regs __iomem *) (base + 0x0300);
3675*4882a593Smuzhiyun
3676*4882a593Smuzhiyun if (dev->quirks & PLX_PCIE) {
3677*4882a593Smuzhiyun u32 fsmvalue;
3678*4882a593Smuzhiyun u32 usbstat;
3679*4882a593Smuzhiyun dev->usb_ext = (struct usb338x_usb_ext_regs __iomem *)
3680*4882a593Smuzhiyun (base + 0x00b4);
3681*4882a593Smuzhiyun dev->llregs = (struct usb338x_ll_regs __iomem *)
3682*4882a593Smuzhiyun (base + 0x0700);
3683*4882a593Smuzhiyun dev->plregs = (struct usb338x_pl_regs __iomem *)
3684*4882a593Smuzhiyun (base + 0x0800);
3685*4882a593Smuzhiyun usbstat = readl(&dev->usb->usbstat);
3686*4882a593Smuzhiyun dev->enhanced_mode = !!(usbstat & BIT(11));
3687*4882a593Smuzhiyun dev->n_ep = (dev->enhanced_mode) ? 9 : 5;
3688*4882a593Smuzhiyun /* put into initial config, link up all endpoints */
3689*4882a593Smuzhiyun fsmvalue = get_idx_reg(dev->regs, SCRATCH) &
3690*4882a593Smuzhiyun (0xf << DEFECT7374_FSM_FIELD);
3691*4882a593Smuzhiyun /* See if firmware needs to set up for workaround: */
3692*4882a593Smuzhiyun if (fsmvalue == DEFECT7374_FSM_SS_CONTROL_READ) {
3693*4882a593Smuzhiyun dev->bug7734_patched = 1;
3694*4882a593Smuzhiyun writel(0, &dev->usb->usbctl);
3695*4882a593Smuzhiyun } else
3696*4882a593Smuzhiyun dev->bug7734_patched = 0;
3697*4882a593Smuzhiyun } else {
3698*4882a593Smuzhiyun dev->enhanced_mode = 0;
3699*4882a593Smuzhiyun dev->n_ep = 7;
3700*4882a593Smuzhiyun /* put into initial config, link up all endpoints */
3701*4882a593Smuzhiyun writel(0, &dev->usb->usbctl);
3702*4882a593Smuzhiyun }
3703*4882a593Smuzhiyun
3704*4882a593Smuzhiyun usb_reset(dev);
3705*4882a593Smuzhiyun usb_reinit(dev);
3706*4882a593Smuzhiyun
3707*4882a593Smuzhiyun /* irq setup after old hardware is cleaned up */
3708*4882a593Smuzhiyun if (!pdev->irq) {
3709*4882a593Smuzhiyun ep_err(dev, "No IRQ. Check PCI setup!\n");
3710*4882a593Smuzhiyun retval = -ENODEV;
3711*4882a593Smuzhiyun goto done;
3712*4882a593Smuzhiyun }
3713*4882a593Smuzhiyun
3714*4882a593Smuzhiyun if (dev->quirks & PLX_PCIE)
3715*4882a593Smuzhiyun if (pci_enable_msi(pdev))
3716*4882a593Smuzhiyun ep_err(dev, "Failed to enable MSI mode\n");
3717*4882a593Smuzhiyun
3718*4882a593Smuzhiyun if (request_irq(pdev->irq, net2280_irq, IRQF_SHARED,
3719*4882a593Smuzhiyun driver_name, dev)) {
3720*4882a593Smuzhiyun ep_err(dev, "request interrupt %d failed\n", pdev->irq);
3721*4882a593Smuzhiyun retval = -EBUSY;
3722*4882a593Smuzhiyun goto done;
3723*4882a593Smuzhiyun }
3724*4882a593Smuzhiyun dev->got_irq = 1;
3725*4882a593Smuzhiyun
3726*4882a593Smuzhiyun /* DMA setup */
3727*4882a593Smuzhiyun /* NOTE: we know only the 32 LSBs of dma addresses may be nonzero */
3728*4882a593Smuzhiyun dev->requests = dma_pool_create("requests", &pdev->dev,
3729*4882a593Smuzhiyun sizeof(struct net2280_dma),
3730*4882a593Smuzhiyun 0 /* no alignment requirements */,
3731*4882a593Smuzhiyun 0 /* or page-crossing issues */);
3732*4882a593Smuzhiyun if (!dev->requests) {
3733*4882a593Smuzhiyun ep_dbg(dev, "can't get request pool\n");
3734*4882a593Smuzhiyun retval = -ENOMEM;
3735*4882a593Smuzhiyun goto done;
3736*4882a593Smuzhiyun }
3737*4882a593Smuzhiyun for (i = 1; i < 5; i++) {
3738*4882a593Smuzhiyun struct net2280_dma *td;
3739*4882a593Smuzhiyun
3740*4882a593Smuzhiyun td = dma_pool_alloc(dev->requests, GFP_KERNEL,
3741*4882a593Smuzhiyun &dev->ep[i].td_dma);
3742*4882a593Smuzhiyun if (!td) {
3743*4882a593Smuzhiyun ep_dbg(dev, "can't get dummy %d\n", i);
3744*4882a593Smuzhiyun retval = -ENOMEM;
3745*4882a593Smuzhiyun goto done;
3746*4882a593Smuzhiyun }
3747*4882a593Smuzhiyun td->dmacount = 0; /* not VALID */
3748*4882a593Smuzhiyun td->dmadesc = td->dmaaddr;
3749*4882a593Smuzhiyun dev->ep[i].dummy = td;
3750*4882a593Smuzhiyun }
3751*4882a593Smuzhiyun
3752*4882a593Smuzhiyun /* enable lower-overhead pci memory bursts during DMA */
3753*4882a593Smuzhiyun if (dev->quirks & PLX_LEGACY)
3754*4882a593Smuzhiyun writel(BIT(DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE) |
3755*4882a593Smuzhiyun /*
3756*4882a593Smuzhiyun * 256 write retries may not be enough...
3757*4882a593Smuzhiyun BIT(PCI_RETRY_ABORT_ENABLE) |
3758*4882a593Smuzhiyun */
3759*4882a593Smuzhiyun BIT(DMA_READ_MULTIPLE_ENABLE) |
3760*4882a593Smuzhiyun BIT(DMA_READ_LINE_ENABLE),
3761*4882a593Smuzhiyun &dev->pci->pcimstctl);
3762*4882a593Smuzhiyun /* erratum 0115 shouldn't appear: Linux inits PCI_LATENCY_TIMER */
3763*4882a593Smuzhiyun pci_set_master(pdev);
3764*4882a593Smuzhiyun pci_try_set_mwi(pdev);
3765*4882a593Smuzhiyun
3766*4882a593Smuzhiyun /* ... also flushes any posted pci writes */
3767*4882a593Smuzhiyun dev->chiprev = get_idx_reg(dev->regs, REG_CHIPREV) & 0xffff;
3768*4882a593Smuzhiyun
3769*4882a593Smuzhiyun /* done */
3770*4882a593Smuzhiyun ep_info(dev, "%s\n", driver_desc);
3771*4882a593Smuzhiyun ep_info(dev, "irq %d, pci mem %p, chip rev %04x\n",
3772*4882a593Smuzhiyun pdev->irq, base, dev->chiprev);
3773*4882a593Smuzhiyun ep_info(dev, "version: " DRIVER_VERSION "; %s\n",
3774*4882a593Smuzhiyun dev->enhanced_mode ? "enhanced mode" : "legacy mode");
3775*4882a593Smuzhiyun retval = device_create_file(&pdev->dev, &dev_attr_registers);
3776*4882a593Smuzhiyun if (retval)
3777*4882a593Smuzhiyun goto done;
3778*4882a593Smuzhiyun
3779*4882a593Smuzhiyun retval = usb_add_gadget(&dev->gadget);
3780*4882a593Smuzhiyun if (retval)
3781*4882a593Smuzhiyun goto done;
3782*4882a593Smuzhiyun dev->added = 1;
3783*4882a593Smuzhiyun return 0;
3784*4882a593Smuzhiyun
3785*4882a593Smuzhiyun done:
3786*4882a593Smuzhiyun if (dev) {
3787*4882a593Smuzhiyun net2280_remove(pdev);
3788*4882a593Smuzhiyun kfree(dev);
3789*4882a593Smuzhiyun }
3790*4882a593Smuzhiyun return retval;
3791*4882a593Smuzhiyun }
3792*4882a593Smuzhiyun
3793*4882a593Smuzhiyun /* make sure the board is quiescent; otherwise it will continue
3794*4882a593Smuzhiyun * generating IRQs across the upcoming reboot.
3795*4882a593Smuzhiyun */
3796*4882a593Smuzhiyun
net2280_shutdown(struct pci_dev * pdev)3797*4882a593Smuzhiyun static void net2280_shutdown(struct pci_dev *pdev)
3798*4882a593Smuzhiyun {
3799*4882a593Smuzhiyun struct net2280 *dev = pci_get_drvdata(pdev);
3800*4882a593Smuzhiyun
3801*4882a593Smuzhiyun /* disable IRQs */
3802*4882a593Smuzhiyun writel(0, &dev->regs->pciirqenb0);
3803*4882a593Smuzhiyun writel(0, &dev->regs->pciirqenb1);
3804*4882a593Smuzhiyun
3805*4882a593Smuzhiyun /* disable the pullup so the host will think we're gone */
3806*4882a593Smuzhiyun writel(0, &dev->usb->usbctl);
3807*4882a593Smuzhiyun
3808*4882a593Smuzhiyun }
3809*4882a593Smuzhiyun
3810*4882a593Smuzhiyun
3811*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
3812*4882a593Smuzhiyun
3813*4882a593Smuzhiyun static const struct pci_device_id pci_ids[] = { {
3814*4882a593Smuzhiyun .class = PCI_CLASS_SERIAL_USB_DEVICE,
3815*4882a593Smuzhiyun .class_mask = ~0,
3816*4882a593Smuzhiyun .vendor = PCI_VENDOR_ID_PLX_LEGACY,
3817*4882a593Smuzhiyun .device = 0x2280,
3818*4882a593Smuzhiyun .subvendor = PCI_ANY_ID,
3819*4882a593Smuzhiyun .subdevice = PCI_ANY_ID,
3820*4882a593Smuzhiyun .driver_data = PLX_LEGACY | PLX_2280,
3821*4882a593Smuzhiyun }, {
3822*4882a593Smuzhiyun .class = PCI_CLASS_SERIAL_USB_DEVICE,
3823*4882a593Smuzhiyun .class_mask = ~0,
3824*4882a593Smuzhiyun .vendor = PCI_VENDOR_ID_PLX_LEGACY,
3825*4882a593Smuzhiyun .device = 0x2282,
3826*4882a593Smuzhiyun .subvendor = PCI_ANY_ID,
3827*4882a593Smuzhiyun .subdevice = PCI_ANY_ID,
3828*4882a593Smuzhiyun .driver_data = PLX_LEGACY,
3829*4882a593Smuzhiyun },
3830*4882a593Smuzhiyun {
3831*4882a593Smuzhiyun .class = PCI_CLASS_SERIAL_USB_DEVICE,
3832*4882a593Smuzhiyun .class_mask = ~0,
3833*4882a593Smuzhiyun .vendor = PCI_VENDOR_ID_PLX,
3834*4882a593Smuzhiyun .device = 0x2380,
3835*4882a593Smuzhiyun .subvendor = PCI_ANY_ID,
3836*4882a593Smuzhiyun .subdevice = PCI_ANY_ID,
3837*4882a593Smuzhiyun .driver_data = PLX_PCIE,
3838*4882a593Smuzhiyun },
3839*4882a593Smuzhiyun {
3840*4882a593Smuzhiyun .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
3841*4882a593Smuzhiyun .class_mask = ~0,
3842*4882a593Smuzhiyun .vendor = PCI_VENDOR_ID_PLX,
3843*4882a593Smuzhiyun .device = 0x3380,
3844*4882a593Smuzhiyun .subvendor = PCI_ANY_ID,
3845*4882a593Smuzhiyun .subdevice = PCI_ANY_ID,
3846*4882a593Smuzhiyun .driver_data = PLX_PCIE | PLX_SUPERSPEED,
3847*4882a593Smuzhiyun },
3848*4882a593Smuzhiyun {
3849*4882a593Smuzhiyun .class = PCI_CLASS_SERIAL_USB_DEVICE,
3850*4882a593Smuzhiyun .class_mask = ~0,
3851*4882a593Smuzhiyun .vendor = PCI_VENDOR_ID_PLX,
3852*4882a593Smuzhiyun .device = 0x3382,
3853*4882a593Smuzhiyun .subvendor = PCI_ANY_ID,
3854*4882a593Smuzhiyun .subdevice = PCI_ANY_ID,
3855*4882a593Smuzhiyun .driver_data = PLX_PCIE | PLX_SUPERSPEED,
3856*4882a593Smuzhiyun },
3857*4882a593Smuzhiyun { /* end: all zeroes */ }
3858*4882a593Smuzhiyun };
3859*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, pci_ids);
3860*4882a593Smuzhiyun
3861*4882a593Smuzhiyun /* pci driver glue; this is a "new style" PCI driver module */
3862*4882a593Smuzhiyun static struct pci_driver net2280_pci_driver = {
3863*4882a593Smuzhiyun .name = driver_name,
3864*4882a593Smuzhiyun .id_table = pci_ids,
3865*4882a593Smuzhiyun
3866*4882a593Smuzhiyun .probe = net2280_probe,
3867*4882a593Smuzhiyun .remove = net2280_remove,
3868*4882a593Smuzhiyun .shutdown = net2280_shutdown,
3869*4882a593Smuzhiyun
3870*4882a593Smuzhiyun /* FIXME add power management support */
3871*4882a593Smuzhiyun };
3872*4882a593Smuzhiyun
3873*4882a593Smuzhiyun module_pci_driver(net2280_pci_driver);
3874*4882a593Smuzhiyun
3875*4882a593Smuzhiyun MODULE_DESCRIPTION(DRIVER_DESC);
3876*4882a593Smuzhiyun MODULE_AUTHOR("David Brownell");
3877*4882a593Smuzhiyun MODULE_LICENSE("GPL");
3878