xref: /OK3568_Linux_fs/kernel/drivers/usb/gadget/udc/m66592-udc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * M66592 UDC (USB gadget)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2006-2007 Renesas Solutions Corp.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun #include <linux/usb/ch9.h>
18*4882a593Smuzhiyun #include <linux/usb/gadget.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include "m66592-udc.h"
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun MODULE_DESCRIPTION("M66592 USB gadget driver");
23*4882a593Smuzhiyun MODULE_LICENSE("GPL");
24*4882a593Smuzhiyun MODULE_AUTHOR("Yoshihiro Shimoda");
25*4882a593Smuzhiyun MODULE_ALIAS("platform:m66592_udc");
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define DRIVER_VERSION	"21 July 2009"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static const char udc_name[] = "m66592_udc";
30*4882a593Smuzhiyun static const char *m66592_ep_name[] = {
31*4882a593Smuzhiyun 	"ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static void disable_controller(struct m66592 *m66592);
35*4882a593Smuzhiyun static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
36*4882a593Smuzhiyun static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
37*4882a593Smuzhiyun static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
38*4882a593Smuzhiyun 			gfp_t gfp_flags);
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun static void transfer_complete(struct m66592_ep *ep,
41*4882a593Smuzhiyun 		struct m66592_request *req, int status);
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
get_usb_speed(struct m66592 * m66592)44*4882a593Smuzhiyun static inline u16 get_usb_speed(struct m66592 *m66592)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun 	return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun 
enable_pipe_irq(struct m66592 * m66592,u16 pipenum,unsigned long reg)49*4882a593Smuzhiyun static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
50*4882a593Smuzhiyun 		unsigned long reg)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	u16 tmp;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	tmp = m66592_read(m66592, M66592_INTENB0);
55*4882a593Smuzhiyun 	m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
56*4882a593Smuzhiyun 			M66592_INTENB0);
57*4882a593Smuzhiyun 	m66592_bset(m66592, (1 << pipenum), reg);
58*4882a593Smuzhiyun 	m66592_write(m66592, tmp, M66592_INTENB0);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
disable_pipe_irq(struct m66592 * m66592,u16 pipenum,unsigned long reg)61*4882a593Smuzhiyun static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
62*4882a593Smuzhiyun 		unsigned long reg)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	u16 tmp;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	tmp = m66592_read(m66592, M66592_INTENB0);
67*4882a593Smuzhiyun 	m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
68*4882a593Smuzhiyun 			M66592_INTENB0);
69*4882a593Smuzhiyun 	m66592_bclr(m66592, (1 << pipenum), reg);
70*4882a593Smuzhiyun 	m66592_write(m66592, tmp, M66592_INTENB0);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun 
m66592_usb_connect(struct m66592 * m66592)73*4882a593Smuzhiyun static void m66592_usb_connect(struct m66592 *m66592)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
76*4882a593Smuzhiyun 	m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
77*4882a593Smuzhiyun 			M66592_INTENB0);
78*4882a593Smuzhiyun 	m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
m66592_usb_disconnect(struct m66592 * m66592)83*4882a593Smuzhiyun static void m66592_usb_disconnect(struct m66592 *m66592)
84*4882a593Smuzhiyun __releases(m66592->lock)
85*4882a593Smuzhiyun __acquires(m66592->lock)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
88*4882a593Smuzhiyun 	m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
89*4882a593Smuzhiyun 			M66592_INTENB0);
90*4882a593Smuzhiyun 	m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
91*4882a593Smuzhiyun 	m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	m66592->gadget.speed = USB_SPEED_UNKNOWN;
94*4882a593Smuzhiyun 	spin_unlock(&m66592->lock);
95*4882a593Smuzhiyun 	m66592->driver->disconnect(&m66592->gadget);
96*4882a593Smuzhiyun 	spin_lock(&m66592->lock);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	disable_controller(m66592);
99*4882a593Smuzhiyun 	INIT_LIST_HEAD(&m66592->ep[0].queue);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
control_reg_get_pid(struct m66592 * m66592,u16 pipenum)102*4882a593Smuzhiyun static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	u16 pid = 0;
105*4882a593Smuzhiyun 	unsigned long offset;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	if (pipenum == 0)
108*4882a593Smuzhiyun 		pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
109*4882a593Smuzhiyun 	else if (pipenum < M66592_MAX_NUM_PIPE) {
110*4882a593Smuzhiyun 		offset = get_pipectr_addr(pipenum);
111*4882a593Smuzhiyun 		pid = m66592_read(m66592, offset) & M66592_PID;
112*4882a593Smuzhiyun 	} else
113*4882a593Smuzhiyun 		pr_err("unexpect pipe num (%d)\n", pipenum);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	return pid;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
control_reg_set_pid(struct m66592 * m66592,u16 pipenum,u16 pid)118*4882a593Smuzhiyun static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
119*4882a593Smuzhiyun 		u16 pid)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun 	unsigned long offset;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	if (pipenum == 0)
124*4882a593Smuzhiyun 		m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
125*4882a593Smuzhiyun 	else if (pipenum < M66592_MAX_NUM_PIPE) {
126*4882a593Smuzhiyun 		offset = get_pipectr_addr(pipenum);
127*4882a593Smuzhiyun 		m66592_mdfy(m66592, pid, M66592_PID, offset);
128*4882a593Smuzhiyun 	} else
129*4882a593Smuzhiyun 		pr_err("unexpect pipe num (%d)\n", pipenum);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun 
pipe_start(struct m66592 * m66592,u16 pipenum)132*4882a593Smuzhiyun static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
pipe_stop(struct m66592 * m66592,u16 pipenum)137*4882a593Smuzhiyun static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
pipe_stall(struct m66592 * m66592,u16 pipenum)142*4882a593Smuzhiyun static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun 
control_reg_get(struct m66592 * m66592,u16 pipenum)147*4882a593Smuzhiyun static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun 	u16 ret = 0;
150*4882a593Smuzhiyun 	unsigned long offset;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	if (pipenum == 0)
153*4882a593Smuzhiyun 		ret = m66592_read(m66592, M66592_DCPCTR);
154*4882a593Smuzhiyun 	else if (pipenum < M66592_MAX_NUM_PIPE) {
155*4882a593Smuzhiyun 		offset = get_pipectr_addr(pipenum);
156*4882a593Smuzhiyun 		ret = m66592_read(m66592, offset);
157*4882a593Smuzhiyun 	} else
158*4882a593Smuzhiyun 		pr_err("unexpect pipe num (%d)\n", pipenum);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	return ret;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
control_reg_sqclr(struct m66592 * m66592,u16 pipenum)163*4882a593Smuzhiyun static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun 	unsigned long offset;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	pipe_stop(m66592, pipenum);
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	if (pipenum == 0)
170*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
171*4882a593Smuzhiyun 	else if (pipenum < M66592_MAX_NUM_PIPE) {
172*4882a593Smuzhiyun 		offset = get_pipectr_addr(pipenum);
173*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_SQCLR, offset);
174*4882a593Smuzhiyun 	} else
175*4882a593Smuzhiyun 		pr_err("unexpect pipe num(%d)\n", pipenum);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun 
get_buffer_size(struct m66592 * m66592,u16 pipenum)178*4882a593Smuzhiyun static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun 	u16 tmp;
181*4882a593Smuzhiyun 	int size;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	if (pipenum == 0) {
184*4882a593Smuzhiyun 		tmp = m66592_read(m66592, M66592_DCPCFG);
185*4882a593Smuzhiyun 		if ((tmp & M66592_CNTMD) != 0)
186*4882a593Smuzhiyun 			size = 256;
187*4882a593Smuzhiyun 		else {
188*4882a593Smuzhiyun 			tmp = m66592_read(m66592, M66592_DCPMAXP);
189*4882a593Smuzhiyun 			size = tmp & M66592_MAXP;
190*4882a593Smuzhiyun 		}
191*4882a593Smuzhiyun 	} else {
192*4882a593Smuzhiyun 		m66592_write(m66592, pipenum, M66592_PIPESEL);
193*4882a593Smuzhiyun 		tmp = m66592_read(m66592, M66592_PIPECFG);
194*4882a593Smuzhiyun 		if ((tmp & M66592_CNTMD) != 0) {
195*4882a593Smuzhiyun 			tmp = m66592_read(m66592, M66592_PIPEBUF);
196*4882a593Smuzhiyun 			size = ((tmp >> 10) + 1) * 64;
197*4882a593Smuzhiyun 		} else {
198*4882a593Smuzhiyun 			tmp = m66592_read(m66592, M66592_PIPEMAXP);
199*4882a593Smuzhiyun 			size = tmp & M66592_MXPS;
200*4882a593Smuzhiyun 		}
201*4882a593Smuzhiyun 	}
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	return size;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun 
pipe_change(struct m66592 * m66592,u16 pipenum)206*4882a593Smuzhiyun static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun 	struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
209*4882a593Smuzhiyun 	unsigned short mbw;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	if (ep->use_dma)
212*4882a593Smuzhiyun 		return;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	ndelay(450);
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	if (m66592->pdata->on_chip)
219*4882a593Smuzhiyun 		mbw = M66592_MBW_32;
220*4882a593Smuzhiyun 	else
221*4882a593Smuzhiyun 		mbw = M66592_MBW_16;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	m66592_bset(m66592, mbw, ep->fifosel);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
pipe_buffer_setting(struct m66592 * m66592,struct m66592_pipe_info * info)226*4882a593Smuzhiyun static int pipe_buffer_setting(struct m66592 *m66592,
227*4882a593Smuzhiyun 		struct m66592_pipe_info *info)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun 	u16 bufnum = 0, buf_bsize = 0;
230*4882a593Smuzhiyun 	u16 pipecfg = 0;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	if (info->pipe == 0)
233*4882a593Smuzhiyun 		return -EINVAL;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	m66592_write(m66592, info->pipe, M66592_PIPESEL);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	if (info->dir_in)
238*4882a593Smuzhiyun 		pipecfg |= M66592_DIR;
239*4882a593Smuzhiyun 	pipecfg |= info->type;
240*4882a593Smuzhiyun 	pipecfg |= info->epnum;
241*4882a593Smuzhiyun 	switch (info->type) {
242*4882a593Smuzhiyun 	case M66592_INT:
243*4882a593Smuzhiyun 		bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
244*4882a593Smuzhiyun 		buf_bsize = 0;
245*4882a593Smuzhiyun 		break;
246*4882a593Smuzhiyun 	case M66592_BULK:
247*4882a593Smuzhiyun 		/* isochronous pipes may be used as bulk pipes */
248*4882a593Smuzhiyun 		if (info->pipe >= M66592_BASE_PIPENUM_BULK)
249*4882a593Smuzhiyun 			bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
250*4882a593Smuzhiyun 		else
251*4882a593Smuzhiyun 			bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 		bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
254*4882a593Smuzhiyun 		buf_bsize = 7;
255*4882a593Smuzhiyun 		pipecfg |= M66592_DBLB;
256*4882a593Smuzhiyun 		if (!info->dir_in)
257*4882a593Smuzhiyun 			pipecfg |= M66592_SHTNAK;
258*4882a593Smuzhiyun 		break;
259*4882a593Smuzhiyun 	case M66592_ISO:
260*4882a593Smuzhiyun 		bufnum = M66592_BASE_BUFNUM +
261*4882a593Smuzhiyun 			 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
262*4882a593Smuzhiyun 		buf_bsize = 7;
263*4882a593Smuzhiyun 		break;
264*4882a593Smuzhiyun 	}
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
267*4882a593Smuzhiyun 		pr_err("m66592 pipe memory is insufficient\n");
268*4882a593Smuzhiyun 		return -ENOMEM;
269*4882a593Smuzhiyun 	}
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	m66592_write(m66592, pipecfg, M66592_PIPECFG);
272*4882a593Smuzhiyun 	m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
273*4882a593Smuzhiyun 	m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
274*4882a593Smuzhiyun 	if (info->interval)
275*4882a593Smuzhiyun 		info->interval--;
276*4882a593Smuzhiyun 	m66592_write(m66592, info->interval, M66592_PIPEPERI);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	return 0;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun 
pipe_buffer_release(struct m66592 * m66592,struct m66592_pipe_info * info)281*4882a593Smuzhiyun static void pipe_buffer_release(struct m66592 *m66592,
282*4882a593Smuzhiyun 				struct m66592_pipe_info *info)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun 	if (info->pipe == 0)
285*4882a593Smuzhiyun 		return;
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	if (is_bulk_pipe(info->pipe)) {
288*4882a593Smuzhiyun 		m66592->bulk--;
289*4882a593Smuzhiyun 	} else if (is_interrupt_pipe(info->pipe))
290*4882a593Smuzhiyun 		m66592->interrupt--;
291*4882a593Smuzhiyun 	else if (is_isoc_pipe(info->pipe)) {
292*4882a593Smuzhiyun 		m66592->isochronous--;
293*4882a593Smuzhiyun 		if (info->type == M66592_BULK)
294*4882a593Smuzhiyun 			m66592->bulk--;
295*4882a593Smuzhiyun 	} else
296*4882a593Smuzhiyun 		pr_err("ep_release: unexpect pipenum (%d)\n",
297*4882a593Smuzhiyun 				info->pipe);
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun 
pipe_initialize(struct m66592_ep * ep)300*4882a593Smuzhiyun static void pipe_initialize(struct m66592_ep *ep)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
303*4882a593Smuzhiyun 	unsigned short mbw;
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	m66592_write(m66592, M66592_ACLRM, ep->pipectr);
308*4882a593Smuzhiyun 	m66592_write(m66592, 0, ep->pipectr);
309*4882a593Smuzhiyun 	m66592_write(m66592, M66592_SQCLR, ep->pipectr);
310*4882a593Smuzhiyun 	if (ep->use_dma) {
311*4882a593Smuzhiyun 		m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 		ndelay(450);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 		if (m66592->pdata->on_chip)
316*4882a593Smuzhiyun 			mbw = M66592_MBW_32;
317*4882a593Smuzhiyun 		else
318*4882a593Smuzhiyun 			mbw = M66592_MBW_16;
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 		m66592_bset(m66592, mbw, ep->fifosel);
321*4882a593Smuzhiyun 	}
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
m66592_ep_setting(struct m66592 * m66592,struct m66592_ep * ep,const struct usb_endpoint_descriptor * desc,u16 pipenum,int dma)324*4882a593Smuzhiyun static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
325*4882a593Smuzhiyun 		const struct usb_endpoint_descriptor *desc,
326*4882a593Smuzhiyun 		u16 pipenum, int dma)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun 	if ((pipenum != 0) && dma) {
329*4882a593Smuzhiyun 		if (m66592->num_dma == 0) {
330*4882a593Smuzhiyun 			m66592->num_dma++;
331*4882a593Smuzhiyun 			ep->use_dma = 1;
332*4882a593Smuzhiyun 			ep->fifoaddr = M66592_D0FIFO;
333*4882a593Smuzhiyun 			ep->fifosel = M66592_D0FIFOSEL;
334*4882a593Smuzhiyun 			ep->fifoctr = M66592_D0FIFOCTR;
335*4882a593Smuzhiyun 			ep->fifotrn = M66592_D0FIFOTRN;
336*4882a593Smuzhiyun 		} else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
337*4882a593Smuzhiyun 			m66592->num_dma++;
338*4882a593Smuzhiyun 			ep->use_dma = 1;
339*4882a593Smuzhiyun 			ep->fifoaddr = M66592_D1FIFO;
340*4882a593Smuzhiyun 			ep->fifosel = M66592_D1FIFOSEL;
341*4882a593Smuzhiyun 			ep->fifoctr = M66592_D1FIFOCTR;
342*4882a593Smuzhiyun 			ep->fifotrn = M66592_D1FIFOTRN;
343*4882a593Smuzhiyun 		} else {
344*4882a593Smuzhiyun 			ep->use_dma = 0;
345*4882a593Smuzhiyun 			ep->fifoaddr = M66592_CFIFO;
346*4882a593Smuzhiyun 			ep->fifosel = M66592_CFIFOSEL;
347*4882a593Smuzhiyun 			ep->fifoctr = M66592_CFIFOCTR;
348*4882a593Smuzhiyun 			ep->fifotrn = 0;
349*4882a593Smuzhiyun 		}
350*4882a593Smuzhiyun 	} else {
351*4882a593Smuzhiyun 		ep->use_dma = 0;
352*4882a593Smuzhiyun 		ep->fifoaddr = M66592_CFIFO;
353*4882a593Smuzhiyun 		ep->fifosel = M66592_CFIFOSEL;
354*4882a593Smuzhiyun 		ep->fifoctr = M66592_CFIFOCTR;
355*4882a593Smuzhiyun 		ep->fifotrn = 0;
356*4882a593Smuzhiyun 	}
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	ep->pipectr = get_pipectr_addr(pipenum);
359*4882a593Smuzhiyun 	ep->pipenum = pipenum;
360*4882a593Smuzhiyun 	ep->ep.maxpacket = usb_endpoint_maxp(desc);
361*4882a593Smuzhiyun 	m66592->pipenum2ep[pipenum] = ep;
362*4882a593Smuzhiyun 	m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
363*4882a593Smuzhiyun 	INIT_LIST_HEAD(&ep->queue);
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun 
m66592_ep_release(struct m66592_ep * ep)366*4882a593Smuzhiyun static void m66592_ep_release(struct m66592_ep *ep)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
369*4882a593Smuzhiyun 	u16 pipenum = ep->pipenum;
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	if (pipenum == 0)
372*4882a593Smuzhiyun 		return;
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	if (ep->use_dma)
375*4882a593Smuzhiyun 		m66592->num_dma--;
376*4882a593Smuzhiyun 	ep->pipenum = 0;
377*4882a593Smuzhiyun 	ep->busy = 0;
378*4882a593Smuzhiyun 	ep->use_dma = 0;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun 
alloc_pipe_config(struct m66592_ep * ep,const struct usb_endpoint_descriptor * desc)381*4882a593Smuzhiyun static int alloc_pipe_config(struct m66592_ep *ep,
382*4882a593Smuzhiyun 		const struct usb_endpoint_descriptor *desc)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
385*4882a593Smuzhiyun 	struct m66592_pipe_info info;
386*4882a593Smuzhiyun 	int dma = 0;
387*4882a593Smuzhiyun 	int *counter;
388*4882a593Smuzhiyun 	int ret;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	ep->ep.desc = desc;
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	BUG_ON(ep->pipenum);
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
395*4882a593Smuzhiyun 	case USB_ENDPOINT_XFER_BULK:
396*4882a593Smuzhiyun 		if (m66592->bulk >= M66592_MAX_NUM_BULK) {
397*4882a593Smuzhiyun 			if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
398*4882a593Smuzhiyun 				pr_err("bulk pipe is insufficient\n");
399*4882a593Smuzhiyun 				return -ENODEV;
400*4882a593Smuzhiyun 			} else {
401*4882a593Smuzhiyun 				info.pipe = M66592_BASE_PIPENUM_ISOC
402*4882a593Smuzhiyun 						+ m66592->isochronous;
403*4882a593Smuzhiyun 				counter = &m66592->isochronous;
404*4882a593Smuzhiyun 			}
405*4882a593Smuzhiyun 		} else {
406*4882a593Smuzhiyun 			info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
407*4882a593Smuzhiyun 			counter = &m66592->bulk;
408*4882a593Smuzhiyun 		}
409*4882a593Smuzhiyun 		info.type = M66592_BULK;
410*4882a593Smuzhiyun 		dma = 1;
411*4882a593Smuzhiyun 		break;
412*4882a593Smuzhiyun 	case USB_ENDPOINT_XFER_INT:
413*4882a593Smuzhiyun 		if (m66592->interrupt >= M66592_MAX_NUM_INT) {
414*4882a593Smuzhiyun 			pr_err("interrupt pipe is insufficient\n");
415*4882a593Smuzhiyun 			return -ENODEV;
416*4882a593Smuzhiyun 		}
417*4882a593Smuzhiyun 		info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
418*4882a593Smuzhiyun 		info.type = M66592_INT;
419*4882a593Smuzhiyun 		counter = &m66592->interrupt;
420*4882a593Smuzhiyun 		break;
421*4882a593Smuzhiyun 	case USB_ENDPOINT_XFER_ISOC:
422*4882a593Smuzhiyun 		if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
423*4882a593Smuzhiyun 			pr_err("isochronous pipe is insufficient\n");
424*4882a593Smuzhiyun 			return -ENODEV;
425*4882a593Smuzhiyun 		}
426*4882a593Smuzhiyun 		info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
427*4882a593Smuzhiyun 		info.type = M66592_ISO;
428*4882a593Smuzhiyun 		counter = &m66592->isochronous;
429*4882a593Smuzhiyun 		break;
430*4882a593Smuzhiyun 	default:
431*4882a593Smuzhiyun 		pr_err("unexpect xfer type\n");
432*4882a593Smuzhiyun 		return -EINVAL;
433*4882a593Smuzhiyun 	}
434*4882a593Smuzhiyun 	ep->type = info.type;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
437*4882a593Smuzhiyun 	info.maxpacket = usb_endpoint_maxp(desc);
438*4882a593Smuzhiyun 	info.interval = desc->bInterval;
439*4882a593Smuzhiyun 	if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
440*4882a593Smuzhiyun 		info.dir_in = 1;
441*4882a593Smuzhiyun 	else
442*4882a593Smuzhiyun 		info.dir_in = 0;
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	ret = pipe_buffer_setting(m66592, &info);
445*4882a593Smuzhiyun 	if (ret < 0) {
446*4882a593Smuzhiyun 		pr_err("pipe_buffer_setting fail\n");
447*4882a593Smuzhiyun 		return ret;
448*4882a593Smuzhiyun 	}
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	(*counter)++;
451*4882a593Smuzhiyun 	if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
452*4882a593Smuzhiyun 		m66592->bulk++;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
455*4882a593Smuzhiyun 	pipe_initialize(ep);
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	return 0;
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun 
free_pipe_config(struct m66592_ep * ep)460*4882a593Smuzhiyun static int free_pipe_config(struct m66592_ep *ep)
461*4882a593Smuzhiyun {
462*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
463*4882a593Smuzhiyun 	struct m66592_pipe_info info;
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	info.pipe = ep->pipenum;
466*4882a593Smuzhiyun 	info.type = ep->type;
467*4882a593Smuzhiyun 	pipe_buffer_release(m66592, &info);
468*4882a593Smuzhiyun 	m66592_ep_release(ep);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	return 0;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
pipe_irq_enable(struct m66592 * m66592,u16 pipenum)474*4882a593Smuzhiyun static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun 	enable_irq_ready(m66592, pipenum);
477*4882a593Smuzhiyun 	enable_irq_nrdy(m66592, pipenum);
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun 
pipe_irq_disable(struct m66592 * m66592,u16 pipenum)480*4882a593Smuzhiyun static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun 	disable_irq_ready(m66592, pipenum);
483*4882a593Smuzhiyun 	disable_irq_nrdy(m66592, pipenum);
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun /* if complete is true, gadget driver complete function is not call */
control_end(struct m66592 * m66592,unsigned ccpl)487*4882a593Smuzhiyun static void control_end(struct m66592 *m66592, unsigned ccpl)
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun 	m66592->ep[0].internal_ccpl = ccpl;
490*4882a593Smuzhiyun 	pipe_start(m66592, 0);
491*4882a593Smuzhiyun 	m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun 
start_ep0_write(struct m66592_ep * ep,struct m66592_request * req)494*4882a593Smuzhiyun static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	pipe_change(m66592, ep->pipenum);
499*4882a593Smuzhiyun 	m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
500*4882a593Smuzhiyun 			(M66592_ISEL | M66592_CURPIPE),
501*4882a593Smuzhiyun 			M66592_CFIFOSEL);
502*4882a593Smuzhiyun 	m66592_write(m66592, M66592_BCLR, ep->fifoctr);
503*4882a593Smuzhiyun 	if (req->req.length == 0) {
504*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
505*4882a593Smuzhiyun 		pipe_start(m66592, 0);
506*4882a593Smuzhiyun 		transfer_complete(ep, req, 0);
507*4882a593Smuzhiyun 	} else {
508*4882a593Smuzhiyun 		m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
509*4882a593Smuzhiyun 		irq_ep0_write(ep, req);
510*4882a593Smuzhiyun 	}
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun 
start_packet_write(struct m66592_ep * ep,struct m66592_request * req)513*4882a593Smuzhiyun static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
514*4882a593Smuzhiyun {
515*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
516*4882a593Smuzhiyun 	u16 tmp;
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	pipe_change(m66592, ep->pipenum);
519*4882a593Smuzhiyun 	disable_irq_empty(m66592, ep->pipenum);
520*4882a593Smuzhiyun 	pipe_start(m66592, ep->pipenum);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	tmp = m66592_read(m66592, ep->fifoctr);
523*4882a593Smuzhiyun 	if (unlikely((tmp & M66592_FRDY) == 0))
524*4882a593Smuzhiyun 		pipe_irq_enable(m66592, ep->pipenum);
525*4882a593Smuzhiyun 	else
526*4882a593Smuzhiyun 		irq_packet_write(ep, req);
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun 
start_packet_read(struct m66592_ep * ep,struct m66592_request * req)529*4882a593Smuzhiyun static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
532*4882a593Smuzhiyun 	u16 pipenum = ep->pipenum;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	if (ep->pipenum == 0) {
535*4882a593Smuzhiyun 		m66592_mdfy(m66592, M66592_PIPE0,
536*4882a593Smuzhiyun 				(M66592_ISEL | M66592_CURPIPE),
537*4882a593Smuzhiyun 				M66592_CFIFOSEL);
538*4882a593Smuzhiyun 		m66592_write(m66592, M66592_BCLR, ep->fifoctr);
539*4882a593Smuzhiyun 		pipe_start(m66592, pipenum);
540*4882a593Smuzhiyun 		pipe_irq_enable(m66592, pipenum);
541*4882a593Smuzhiyun 	} else {
542*4882a593Smuzhiyun 		if (ep->use_dma) {
543*4882a593Smuzhiyun 			m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
544*4882a593Smuzhiyun 			pipe_change(m66592, pipenum);
545*4882a593Smuzhiyun 			m66592_bset(m66592, M66592_TRENB, ep->fifosel);
546*4882a593Smuzhiyun 			m66592_write(m66592,
547*4882a593Smuzhiyun 				(req->req.length + ep->ep.maxpacket - 1)
548*4882a593Smuzhiyun 					/ ep->ep.maxpacket,
549*4882a593Smuzhiyun 				ep->fifotrn);
550*4882a593Smuzhiyun 		}
551*4882a593Smuzhiyun 		pipe_start(m66592, pipenum);	/* trigger once */
552*4882a593Smuzhiyun 		pipe_irq_enable(m66592, pipenum);
553*4882a593Smuzhiyun 	}
554*4882a593Smuzhiyun }
555*4882a593Smuzhiyun 
start_packet(struct m66592_ep * ep,struct m66592_request * req)556*4882a593Smuzhiyun static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
557*4882a593Smuzhiyun {
558*4882a593Smuzhiyun 	if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
559*4882a593Smuzhiyun 		start_packet_write(ep, req);
560*4882a593Smuzhiyun 	else
561*4882a593Smuzhiyun 		start_packet_read(ep, req);
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun 
start_ep0(struct m66592_ep * ep,struct m66592_request * req)564*4882a593Smuzhiyun static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun 	u16 ctsq;
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 	switch (ctsq) {
571*4882a593Smuzhiyun 	case M66592_CS_RDDS:
572*4882a593Smuzhiyun 		start_ep0_write(ep, req);
573*4882a593Smuzhiyun 		break;
574*4882a593Smuzhiyun 	case M66592_CS_WRDS:
575*4882a593Smuzhiyun 		start_packet_read(ep, req);
576*4882a593Smuzhiyun 		break;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	case M66592_CS_WRND:
579*4882a593Smuzhiyun 		control_end(ep->m66592, 0);
580*4882a593Smuzhiyun 		break;
581*4882a593Smuzhiyun 	default:
582*4882a593Smuzhiyun 		pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
583*4882a593Smuzhiyun 		break;
584*4882a593Smuzhiyun 	}
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun 
init_controller(struct m66592 * m66592)587*4882a593Smuzhiyun static void init_controller(struct m66592 *m66592)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun 	unsigned int endian;
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	if (m66592->pdata->on_chip) {
592*4882a593Smuzhiyun 		if (m66592->pdata->endian)
593*4882a593Smuzhiyun 			endian = 0; /* big endian */
594*4882a593Smuzhiyun 		else
595*4882a593Smuzhiyun 			endian = M66592_LITTLE; /* little endian */
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_HSE, M66592_SYSCFG);	/* High spd */
598*4882a593Smuzhiyun 		m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
599*4882a593Smuzhiyun 		m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
600*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 		/* This is a workaound for SH7722 2nd cut */
603*4882a593Smuzhiyun 		m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
604*4882a593Smuzhiyun 		m66592_bset(m66592, 0x1000, M66592_TESTMODE);
605*4882a593Smuzhiyun 		m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 		m66592_write(m66592, 0, M66592_CFBCFG);
610*4882a593Smuzhiyun 		m66592_write(m66592, 0, M66592_D0FBCFG);
611*4882a593Smuzhiyun 		m66592_bset(m66592, endian, M66592_CFBCFG);
612*4882a593Smuzhiyun 		m66592_bset(m66592, endian, M66592_D0FBCFG);
613*4882a593Smuzhiyun 	} else {
614*4882a593Smuzhiyun 		unsigned int clock, vif, irq_sense;
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 		if (m66592->pdata->endian)
617*4882a593Smuzhiyun 			endian = M66592_BIGEND; /* big endian */
618*4882a593Smuzhiyun 		else
619*4882a593Smuzhiyun 			endian = 0; /* little endian */
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 		if (m66592->pdata->vif)
622*4882a593Smuzhiyun 			vif = M66592_LDRV; /* 3.3v */
623*4882a593Smuzhiyun 		else
624*4882a593Smuzhiyun 			vif = 0; /* 1.5v */
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 		switch (m66592->pdata->xtal) {
627*4882a593Smuzhiyun 		case M66592_PLATDATA_XTAL_12MHZ:
628*4882a593Smuzhiyun 			clock = M66592_XTAL12;
629*4882a593Smuzhiyun 			break;
630*4882a593Smuzhiyun 		case M66592_PLATDATA_XTAL_24MHZ:
631*4882a593Smuzhiyun 			clock = M66592_XTAL24;
632*4882a593Smuzhiyun 			break;
633*4882a593Smuzhiyun 		case M66592_PLATDATA_XTAL_48MHZ:
634*4882a593Smuzhiyun 			clock = M66592_XTAL48;
635*4882a593Smuzhiyun 			break;
636*4882a593Smuzhiyun 		default:
637*4882a593Smuzhiyun 			pr_warn("m66592-udc: xtal configuration error\n");
638*4882a593Smuzhiyun 			clock = 0;
639*4882a593Smuzhiyun 		}
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 		switch (m66592->irq_trigger) {
642*4882a593Smuzhiyun 		case IRQF_TRIGGER_LOW:
643*4882a593Smuzhiyun 			irq_sense = M66592_INTL;
644*4882a593Smuzhiyun 			break;
645*4882a593Smuzhiyun 		case IRQF_TRIGGER_FALLING:
646*4882a593Smuzhiyun 			irq_sense = 0;
647*4882a593Smuzhiyun 			break;
648*4882a593Smuzhiyun 		default:
649*4882a593Smuzhiyun 			pr_warn("m66592-udc: irq trigger config error\n");
650*4882a593Smuzhiyun 			irq_sense = 0;
651*4882a593Smuzhiyun 		}
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 		m66592_bset(m66592,
654*4882a593Smuzhiyun 			    (vif & M66592_LDRV) | (endian & M66592_BIGEND),
655*4882a593Smuzhiyun 			    M66592_PINCFG);
656*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_HSE, M66592_SYSCFG);	/* High spd */
657*4882a593Smuzhiyun 		m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
658*4882a593Smuzhiyun 			    M66592_SYSCFG);
659*4882a593Smuzhiyun 		m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
660*4882a593Smuzhiyun 		m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
661*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 		msleep(3);
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun 		msleep(1);
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 		m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
674*4882a593Smuzhiyun 		m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
675*4882a593Smuzhiyun 			     M66592_DMA0CFG);
676*4882a593Smuzhiyun 	}
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun 
disable_controller(struct m66592 * m66592)679*4882a593Smuzhiyun static void disable_controller(struct m66592 *m66592)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun 	m66592_bclr(m66592, M66592_UTST, M66592_TESTMODE);
682*4882a593Smuzhiyun 	if (!m66592->pdata->on_chip) {
683*4882a593Smuzhiyun 		m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
684*4882a593Smuzhiyun 		udelay(1);
685*4882a593Smuzhiyun 		m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
686*4882a593Smuzhiyun 		udelay(1);
687*4882a593Smuzhiyun 		m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
688*4882a593Smuzhiyun 		udelay(1);
689*4882a593Smuzhiyun 		m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
690*4882a593Smuzhiyun 	}
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun 
m66592_start_xclock(struct m66592 * m66592)693*4882a593Smuzhiyun static void m66592_start_xclock(struct m66592 *m66592)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun 	u16 tmp;
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	if (!m66592->pdata->on_chip) {
698*4882a593Smuzhiyun 		tmp = m66592_read(m66592, M66592_SYSCFG);
699*4882a593Smuzhiyun 		if (!(tmp & M66592_XCKE))
700*4882a593Smuzhiyun 			m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
701*4882a593Smuzhiyun 	}
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun 
704*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
transfer_complete(struct m66592_ep * ep,struct m66592_request * req,int status)705*4882a593Smuzhiyun static void transfer_complete(struct m66592_ep *ep,
706*4882a593Smuzhiyun 		struct m66592_request *req, int status)
707*4882a593Smuzhiyun __releases(m66592->lock)
708*4882a593Smuzhiyun __acquires(m66592->lock)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun 	int restart = 0;
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun 	if (unlikely(ep->pipenum == 0)) {
713*4882a593Smuzhiyun 		if (ep->internal_ccpl) {
714*4882a593Smuzhiyun 			ep->internal_ccpl = 0;
715*4882a593Smuzhiyun 			return;
716*4882a593Smuzhiyun 		}
717*4882a593Smuzhiyun 	}
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 	list_del_init(&req->queue);
720*4882a593Smuzhiyun 	if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
721*4882a593Smuzhiyun 		req->req.status = -ESHUTDOWN;
722*4882a593Smuzhiyun 	else
723*4882a593Smuzhiyun 		req->req.status = status;
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	if (!list_empty(&ep->queue))
726*4882a593Smuzhiyun 		restart = 1;
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	spin_unlock(&ep->m66592->lock);
729*4882a593Smuzhiyun 	usb_gadget_giveback_request(&ep->ep, &req->req);
730*4882a593Smuzhiyun 	spin_lock(&ep->m66592->lock);
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun 	if (restart) {
733*4882a593Smuzhiyun 		req = list_entry(ep->queue.next, struct m66592_request, queue);
734*4882a593Smuzhiyun 		if (ep->ep.desc)
735*4882a593Smuzhiyun 			start_packet(ep, req);
736*4882a593Smuzhiyun 	}
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun 
irq_ep0_write(struct m66592_ep * ep,struct m66592_request * req)739*4882a593Smuzhiyun static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun 	int i;
742*4882a593Smuzhiyun 	u16 tmp;
743*4882a593Smuzhiyun 	unsigned bufsize;
744*4882a593Smuzhiyun 	size_t size;
745*4882a593Smuzhiyun 	void *buf;
746*4882a593Smuzhiyun 	u16 pipenum = ep->pipenum;
747*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun 	pipe_change(m66592, pipenum);
750*4882a593Smuzhiyun 	m66592_bset(m66592, M66592_ISEL, ep->fifosel);
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun 	i = 0;
753*4882a593Smuzhiyun 	do {
754*4882a593Smuzhiyun 		tmp = m66592_read(m66592, ep->fifoctr);
755*4882a593Smuzhiyun 		if (i++ > 100000) {
756*4882a593Smuzhiyun 			pr_err("pipe0 is busy. maybe cpu i/o bus "
757*4882a593Smuzhiyun 				"conflict. please power off this controller.");
758*4882a593Smuzhiyun 			return;
759*4882a593Smuzhiyun 		}
760*4882a593Smuzhiyun 		ndelay(1);
761*4882a593Smuzhiyun 	} while ((tmp & M66592_FRDY) == 0);
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun 	/* prepare parameters */
764*4882a593Smuzhiyun 	bufsize = get_buffer_size(m66592, pipenum);
765*4882a593Smuzhiyun 	buf = req->req.buf + req->req.actual;
766*4882a593Smuzhiyun 	size = min(bufsize, req->req.length - req->req.actual);
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun 	/* write fifo */
769*4882a593Smuzhiyun 	if (req->req.buf) {
770*4882a593Smuzhiyun 		if (size > 0)
771*4882a593Smuzhiyun 			m66592_write_fifo(m66592, ep, buf, size);
772*4882a593Smuzhiyun 		if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
773*4882a593Smuzhiyun 			m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
774*4882a593Smuzhiyun 	}
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun 	/* update parameters */
777*4882a593Smuzhiyun 	req->req.actual += size;
778*4882a593Smuzhiyun 
779*4882a593Smuzhiyun 	/* check transfer finish */
780*4882a593Smuzhiyun 	if ((!req->req.zero && (req->req.actual == req->req.length))
781*4882a593Smuzhiyun 			|| (size % ep->ep.maxpacket)
782*4882a593Smuzhiyun 			|| (size == 0)) {
783*4882a593Smuzhiyun 		disable_irq_ready(m66592, pipenum);
784*4882a593Smuzhiyun 		disable_irq_empty(m66592, pipenum);
785*4882a593Smuzhiyun 	} else {
786*4882a593Smuzhiyun 		disable_irq_ready(m66592, pipenum);
787*4882a593Smuzhiyun 		enable_irq_empty(m66592, pipenum);
788*4882a593Smuzhiyun 	}
789*4882a593Smuzhiyun 	pipe_start(m66592, pipenum);
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun 
irq_packet_write(struct m66592_ep * ep,struct m66592_request * req)792*4882a593Smuzhiyun static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
793*4882a593Smuzhiyun {
794*4882a593Smuzhiyun 	u16 tmp;
795*4882a593Smuzhiyun 	unsigned bufsize;
796*4882a593Smuzhiyun 	size_t size;
797*4882a593Smuzhiyun 	void *buf;
798*4882a593Smuzhiyun 	u16 pipenum = ep->pipenum;
799*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	pipe_change(m66592, pipenum);
802*4882a593Smuzhiyun 	tmp = m66592_read(m66592, ep->fifoctr);
803*4882a593Smuzhiyun 	if (unlikely((tmp & M66592_FRDY) == 0)) {
804*4882a593Smuzhiyun 		pipe_stop(m66592, pipenum);
805*4882a593Smuzhiyun 		pipe_irq_disable(m66592, pipenum);
806*4882a593Smuzhiyun 		pr_err("write fifo not ready. pipnum=%d\n", pipenum);
807*4882a593Smuzhiyun 		return;
808*4882a593Smuzhiyun 	}
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun 	/* prepare parameters */
811*4882a593Smuzhiyun 	bufsize = get_buffer_size(m66592, pipenum);
812*4882a593Smuzhiyun 	buf = req->req.buf + req->req.actual;
813*4882a593Smuzhiyun 	size = min(bufsize, req->req.length - req->req.actual);
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 	/* write fifo */
816*4882a593Smuzhiyun 	if (req->req.buf) {
817*4882a593Smuzhiyun 		m66592_write_fifo(m66592, ep, buf, size);
818*4882a593Smuzhiyun 		if ((size == 0)
819*4882a593Smuzhiyun 				|| ((size % ep->ep.maxpacket) != 0)
820*4882a593Smuzhiyun 				|| ((bufsize != ep->ep.maxpacket)
821*4882a593Smuzhiyun 					&& (bufsize > size)))
822*4882a593Smuzhiyun 			m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
823*4882a593Smuzhiyun 	}
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 	/* update parameters */
826*4882a593Smuzhiyun 	req->req.actual += size;
827*4882a593Smuzhiyun 	/* check transfer finish */
828*4882a593Smuzhiyun 	if ((!req->req.zero && (req->req.actual == req->req.length))
829*4882a593Smuzhiyun 			|| (size % ep->ep.maxpacket)
830*4882a593Smuzhiyun 			|| (size == 0)) {
831*4882a593Smuzhiyun 		disable_irq_ready(m66592, pipenum);
832*4882a593Smuzhiyun 		enable_irq_empty(m66592, pipenum);
833*4882a593Smuzhiyun 	} else {
834*4882a593Smuzhiyun 		disable_irq_empty(m66592, pipenum);
835*4882a593Smuzhiyun 		pipe_irq_enable(m66592, pipenum);
836*4882a593Smuzhiyun 	}
837*4882a593Smuzhiyun }
838*4882a593Smuzhiyun 
irq_packet_read(struct m66592_ep * ep,struct m66592_request * req)839*4882a593Smuzhiyun static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
840*4882a593Smuzhiyun {
841*4882a593Smuzhiyun 	u16 tmp;
842*4882a593Smuzhiyun 	int rcv_len, bufsize, req_len;
843*4882a593Smuzhiyun 	int size;
844*4882a593Smuzhiyun 	void *buf;
845*4882a593Smuzhiyun 	u16 pipenum = ep->pipenum;
846*4882a593Smuzhiyun 	struct m66592 *m66592 = ep->m66592;
847*4882a593Smuzhiyun 	int finish = 0;
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 	pipe_change(m66592, pipenum);
850*4882a593Smuzhiyun 	tmp = m66592_read(m66592, ep->fifoctr);
851*4882a593Smuzhiyun 	if (unlikely((tmp & M66592_FRDY) == 0)) {
852*4882a593Smuzhiyun 		req->req.status = -EPIPE;
853*4882a593Smuzhiyun 		pipe_stop(m66592, pipenum);
854*4882a593Smuzhiyun 		pipe_irq_disable(m66592, pipenum);
855*4882a593Smuzhiyun 		pr_err("read fifo not ready");
856*4882a593Smuzhiyun 		return;
857*4882a593Smuzhiyun 	}
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun 	/* prepare parameters */
860*4882a593Smuzhiyun 	rcv_len = tmp & M66592_DTLN;
861*4882a593Smuzhiyun 	bufsize = get_buffer_size(m66592, pipenum);
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 	buf = req->req.buf + req->req.actual;
864*4882a593Smuzhiyun 	req_len = req->req.length - req->req.actual;
865*4882a593Smuzhiyun 	if (rcv_len < bufsize)
866*4882a593Smuzhiyun 		size = min(rcv_len, req_len);
867*4882a593Smuzhiyun 	else
868*4882a593Smuzhiyun 		size = min(bufsize, req_len);
869*4882a593Smuzhiyun 
870*4882a593Smuzhiyun 	/* update parameters */
871*4882a593Smuzhiyun 	req->req.actual += size;
872*4882a593Smuzhiyun 
873*4882a593Smuzhiyun 	/* check transfer finish */
874*4882a593Smuzhiyun 	if ((!req->req.zero && (req->req.actual == req->req.length))
875*4882a593Smuzhiyun 			|| (size % ep->ep.maxpacket)
876*4882a593Smuzhiyun 			|| (size == 0)) {
877*4882a593Smuzhiyun 		pipe_stop(m66592, pipenum);
878*4882a593Smuzhiyun 		pipe_irq_disable(m66592, pipenum);
879*4882a593Smuzhiyun 		finish = 1;
880*4882a593Smuzhiyun 	}
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	/* read fifo */
883*4882a593Smuzhiyun 	if (req->req.buf) {
884*4882a593Smuzhiyun 		if (size == 0)
885*4882a593Smuzhiyun 			m66592_write(m66592, M66592_BCLR, ep->fifoctr);
886*4882a593Smuzhiyun 		else
887*4882a593Smuzhiyun 			m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
888*4882a593Smuzhiyun 	}
889*4882a593Smuzhiyun 
890*4882a593Smuzhiyun 	if ((ep->pipenum != 0) && finish)
891*4882a593Smuzhiyun 		transfer_complete(ep, req, 0);
892*4882a593Smuzhiyun }
893*4882a593Smuzhiyun 
irq_pipe_ready(struct m66592 * m66592,u16 status,u16 enb)894*4882a593Smuzhiyun static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
895*4882a593Smuzhiyun {
896*4882a593Smuzhiyun 	u16 check;
897*4882a593Smuzhiyun 	u16 pipenum;
898*4882a593Smuzhiyun 	struct m66592_ep *ep;
899*4882a593Smuzhiyun 	struct m66592_request *req;
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 	if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
902*4882a593Smuzhiyun 		m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
903*4882a593Smuzhiyun 		m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
904*4882a593Smuzhiyun 				M66592_CFIFOSEL);
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun 		ep = &m66592->ep[0];
907*4882a593Smuzhiyun 		req = list_entry(ep->queue.next, struct m66592_request, queue);
908*4882a593Smuzhiyun 		irq_packet_read(ep, req);
909*4882a593Smuzhiyun 	} else {
910*4882a593Smuzhiyun 		for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
911*4882a593Smuzhiyun 			check = 1 << pipenum;
912*4882a593Smuzhiyun 			if ((status & check) && (enb & check)) {
913*4882a593Smuzhiyun 				m66592_write(m66592, ~check, M66592_BRDYSTS);
914*4882a593Smuzhiyun 				ep = m66592->pipenum2ep[pipenum];
915*4882a593Smuzhiyun 				req = list_entry(ep->queue.next,
916*4882a593Smuzhiyun 						 struct m66592_request, queue);
917*4882a593Smuzhiyun 				if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
918*4882a593Smuzhiyun 					irq_packet_write(ep, req);
919*4882a593Smuzhiyun 				else
920*4882a593Smuzhiyun 					irq_packet_read(ep, req);
921*4882a593Smuzhiyun 			}
922*4882a593Smuzhiyun 		}
923*4882a593Smuzhiyun 	}
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun 
irq_pipe_empty(struct m66592 * m66592,u16 status,u16 enb)926*4882a593Smuzhiyun static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
927*4882a593Smuzhiyun {
928*4882a593Smuzhiyun 	u16 tmp;
929*4882a593Smuzhiyun 	u16 check;
930*4882a593Smuzhiyun 	u16 pipenum;
931*4882a593Smuzhiyun 	struct m66592_ep *ep;
932*4882a593Smuzhiyun 	struct m66592_request *req;
933*4882a593Smuzhiyun 
934*4882a593Smuzhiyun 	if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
935*4882a593Smuzhiyun 		m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
936*4882a593Smuzhiyun 
937*4882a593Smuzhiyun 		ep = &m66592->ep[0];
938*4882a593Smuzhiyun 		req = list_entry(ep->queue.next, struct m66592_request, queue);
939*4882a593Smuzhiyun 		irq_ep0_write(ep, req);
940*4882a593Smuzhiyun 	} else {
941*4882a593Smuzhiyun 		for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
942*4882a593Smuzhiyun 			check = 1 << pipenum;
943*4882a593Smuzhiyun 			if ((status & check) && (enb & check)) {
944*4882a593Smuzhiyun 				m66592_write(m66592, ~check, M66592_BEMPSTS);
945*4882a593Smuzhiyun 				tmp = control_reg_get(m66592, pipenum);
946*4882a593Smuzhiyun 				if ((tmp & M66592_INBUFM) == 0) {
947*4882a593Smuzhiyun 					disable_irq_empty(m66592, pipenum);
948*4882a593Smuzhiyun 					pipe_irq_disable(m66592, pipenum);
949*4882a593Smuzhiyun 					pipe_stop(m66592, pipenum);
950*4882a593Smuzhiyun 					ep = m66592->pipenum2ep[pipenum];
951*4882a593Smuzhiyun 					req = list_entry(ep->queue.next,
952*4882a593Smuzhiyun 							 struct m66592_request,
953*4882a593Smuzhiyun 							 queue);
954*4882a593Smuzhiyun 					if (!list_empty(&ep->queue))
955*4882a593Smuzhiyun 						transfer_complete(ep, req, 0);
956*4882a593Smuzhiyun 				}
957*4882a593Smuzhiyun 			}
958*4882a593Smuzhiyun 		}
959*4882a593Smuzhiyun 	}
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun 
get_status(struct m66592 * m66592,struct usb_ctrlrequest * ctrl)962*4882a593Smuzhiyun static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
963*4882a593Smuzhiyun __releases(m66592->lock)
964*4882a593Smuzhiyun __acquires(m66592->lock)
965*4882a593Smuzhiyun {
966*4882a593Smuzhiyun 	struct m66592_ep *ep;
967*4882a593Smuzhiyun 	u16 pid;
968*4882a593Smuzhiyun 	u16 status = 0;
969*4882a593Smuzhiyun 	u16 w_index = le16_to_cpu(ctrl->wIndex);
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 	switch (ctrl->bRequestType & USB_RECIP_MASK) {
972*4882a593Smuzhiyun 	case USB_RECIP_DEVICE:
973*4882a593Smuzhiyun 		status = 1 << USB_DEVICE_SELF_POWERED;
974*4882a593Smuzhiyun 		break;
975*4882a593Smuzhiyun 	case USB_RECIP_INTERFACE:
976*4882a593Smuzhiyun 		status = 0;
977*4882a593Smuzhiyun 		break;
978*4882a593Smuzhiyun 	case USB_RECIP_ENDPOINT:
979*4882a593Smuzhiyun 		ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
980*4882a593Smuzhiyun 		pid = control_reg_get_pid(m66592, ep->pipenum);
981*4882a593Smuzhiyun 		if (pid == M66592_PID_STALL)
982*4882a593Smuzhiyun 			status = 1 << USB_ENDPOINT_HALT;
983*4882a593Smuzhiyun 		else
984*4882a593Smuzhiyun 			status = 0;
985*4882a593Smuzhiyun 		break;
986*4882a593Smuzhiyun 	default:
987*4882a593Smuzhiyun 		pipe_stall(m66592, 0);
988*4882a593Smuzhiyun 		return;		/* exit */
989*4882a593Smuzhiyun 	}
990*4882a593Smuzhiyun 
991*4882a593Smuzhiyun 	m66592->ep0_data = cpu_to_le16(status);
992*4882a593Smuzhiyun 	m66592->ep0_req->buf = &m66592->ep0_data;
993*4882a593Smuzhiyun 	m66592->ep0_req->length = 2;
994*4882a593Smuzhiyun 	/* AV: what happens if we get called again before that gets through? */
995*4882a593Smuzhiyun 	spin_unlock(&m66592->lock);
996*4882a593Smuzhiyun 	m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
997*4882a593Smuzhiyun 	spin_lock(&m66592->lock);
998*4882a593Smuzhiyun }
999*4882a593Smuzhiyun 
clear_feature(struct m66592 * m66592,struct usb_ctrlrequest * ctrl)1000*4882a593Smuzhiyun static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1001*4882a593Smuzhiyun {
1002*4882a593Smuzhiyun 	switch (ctrl->bRequestType & USB_RECIP_MASK) {
1003*4882a593Smuzhiyun 	case USB_RECIP_DEVICE:
1004*4882a593Smuzhiyun 		control_end(m66592, 1);
1005*4882a593Smuzhiyun 		break;
1006*4882a593Smuzhiyun 	case USB_RECIP_INTERFACE:
1007*4882a593Smuzhiyun 		control_end(m66592, 1);
1008*4882a593Smuzhiyun 		break;
1009*4882a593Smuzhiyun 	case USB_RECIP_ENDPOINT: {
1010*4882a593Smuzhiyun 		struct m66592_ep *ep;
1011*4882a593Smuzhiyun 		struct m66592_request *req;
1012*4882a593Smuzhiyun 		u16 w_index = le16_to_cpu(ctrl->wIndex);
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun 		ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1015*4882a593Smuzhiyun 		pipe_stop(m66592, ep->pipenum);
1016*4882a593Smuzhiyun 		control_reg_sqclr(m66592, ep->pipenum);
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun 		control_end(m66592, 1);
1019*4882a593Smuzhiyun 
1020*4882a593Smuzhiyun 		req = list_entry(ep->queue.next,
1021*4882a593Smuzhiyun 		struct m66592_request, queue);
1022*4882a593Smuzhiyun 		if (ep->busy) {
1023*4882a593Smuzhiyun 			ep->busy = 0;
1024*4882a593Smuzhiyun 			if (list_empty(&ep->queue))
1025*4882a593Smuzhiyun 				break;
1026*4882a593Smuzhiyun 			start_packet(ep, req);
1027*4882a593Smuzhiyun 		} else if (!list_empty(&ep->queue))
1028*4882a593Smuzhiyun 			pipe_start(m66592, ep->pipenum);
1029*4882a593Smuzhiyun 		}
1030*4882a593Smuzhiyun 		break;
1031*4882a593Smuzhiyun 	default:
1032*4882a593Smuzhiyun 		pipe_stall(m66592, 0);
1033*4882a593Smuzhiyun 		break;
1034*4882a593Smuzhiyun 	}
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun 
set_feature(struct m66592 * m66592,struct usb_ctrlrequest * ctrl)1037*4882a593Smuzhiyun static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1038*4882a593Smuzhiyun {
1039*4882a593Smuzhiyun 	u16 tmp;
1040*4882a593Smuzhiyun 	int timeout = 3000;
1041*4882a593Smuzhiyun 
1042*4882a593Smuzhiyun 	switch (ctrl->bRequestType & USB_RECIP_MASK) {
1043*4882a593Smuzhiyun 	case USB_RECIP_DEVICE:
1044*4882a593Smuzhiyun 		switch (le16_to_cpu(ctrl->wValue)) {
1045*4882a593Smuzhiyun 		case USB_DEVICE_TEST_MODE:
1046*4882a593Smuzhiyun 			control_end(m66592, 1);
1047*4882a593Smuzhiyun 			/* Wait for the completion of status stage */
1048*4882a593Smuzhiyun 			do {
1049*4882a593Smuzhiyun 				tmp = m66592_read(m66592, M66592_INTSTS0) &
1050*4882a593Smuzhiyun 								M66592_CTSQ;
1051*4882a593Smuzhiyun 				udelay(1);
1052*4882a593Smuzhiyun 			} while (tmp != M66592_CS_IDST && timeout-- > 0);
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun 			if (tmp == M66592_CS_IDST)
1055*4882a593Smuzhiyun 				m66592_bset(m66592,
1056*4882a593Smuzhiyun 					    le16_to_cpu(ctrl->wIndex >> 8),
1057*4882a593Smuzhiyun 					    M66592_TESTMODE);
1058*4882a593Smuzhiyun 			break;
1059*4882a593Smuzhiyun 		default:
1060*4882a593Smuzhiyun 			pipe_stall(m66592, 0);
1061*4882a593Smuzhiyun 			break;
1062*4882a593Smuzhiyun 		}
1063*4882a593Smuzhiyun 		break;
1064*4882a593Smuzhiyun 	case USB_RECIP_INTERFACE:
1065*4882a593Smuzhiyun 		control_end(m66592, 1);
1066*4882a593Smuzhiyun 		break;
1067*4882a593Smuzhiyun 	case USB_RECIP_ENDPOINT: {
1068*4882a593Smuzhiyun 		struct m66592_ep *ep;
1069*4882a593Smuzhiyun 		u16 w_index = le16_to_cpu(ctrl->wIndex);
1070*4882a593Smuzhiyun 
1071*4882a593Smuzhiyun 		ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1072*4882a593Smuzhiyun 		pipe_stall(m66592, ep->pipenum);
1073*4882a593Smuzhiyun 
1074*4882a593Smuzhiyun 		control_end(m66592, 1);
1075*4882a593Smuzhiyun 		}
1076*4882a593Smuzhiyun 		break;
1077*4882a593Smuzhiyun 	default:
1078*4882a593Smuzhiyun 		pipe_stall(m66592, 0);
1079*4882a593Smuzhiyun 		break;
1080*4882a593Smuzhiyun 	}
1081*4882a593Smuzhiyun }
1082*4882a593Smuzhiyun 
1083*4882a593Smuzhiyun /* if return value is true, call class driver's setup() */
setup_packet(struct m66592 * m66592,struct usb_ctrlrequest * ctrl)1084*4882a593Smuzhiyun static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1085*4882a593Smuzhiyun {
1086*4882a593Smuzhiyun 	u16 *p = (u16 *)ctrl;
1087*4882a593Smuzhiyun 	unsigned long offset = M66592_USBREQ;
1088*4882a593Smuzhiyun 	int i, ret = 0;
1089*4882a593Smuzhiyun 
1090*4882a593Smuzhiyun 	/* read fifo */
1091*4882a593Smuzhiyun 	m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun 	for (i = 0; i < 4; i++)
1094*4882a593Smuzhiyun 		p[i] = m66592_read(m66592, offset + i*2);
1095*4882a593Smuzhiyun 
1096*4882a593Smuzhiyun 	/* check request */
1097*4882a593Smuzhiyun 	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1098*4882a593Smuzhiyun 		switch (ctrl->bRequest) {
1099*4882a593Smuzhiyun 		case USB_REQ_GET_STATUS:
1100*4882a593Smuzhiyun 			get_status(m66592, ctrl);
1101*4882a593Smuzhiyun 			break;
1102*4882a593Smuzhiyun 		case USB_REQ_CLEAR_FEATURE:
1103*4882a593Smuzhiyun 			clear_feature(m66592, ctrl);
1104*4882a593Smuzhiyun 			break;
1105*4882a593Smuzhiyun 		case USB_REQ_SET_FEATURE:
1106*4882a593Smuzhiyun 			set_feature(m66592, ctrl);
1107*4882a593Smuzhiyun 			break;
1108*4882a593Smuzhiyun 		default:
1109*4882a593Smuzhiyun 			ret = 1;
1110*4882a593Smuzhiyun 			break;
1111*4882a593Smuzhiyun 		}
1112*4882a593Smuzhiyun 	} else
1113*4882a593Smuzhiyun 		ret = 1;
1114*4882a593Smuzhiyun 	return ret;
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun 
m66592_update_usb_speed(struct m66592 * m66592)1117*4882a593Smuzhiyun static void m66592_update_usb_speed(struct m66592 *m66592)
1118*4882a593Smuzhiyun {
1119*4882a593Smuzhiyun 	u16 speed = get_usb_speed(m66592);
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 	switch (speed) {
1122*4882a593Smuzhiyun 	case M66592_HSMODE:
1123*4882a593Smuzhiyun 		m66592->gadget.speed = USB_SPEED_HIGH;
1124*4882a593Smuzhiyun 		break;
1125*4882a593Smuzhiyun 	case M66592_FSMODE:
1126*4882a593Smuzhiyun 		m66592->gadget.speed = USB_SPEED_FULL;
1127*4882a593Smuzhiyun 		break;
1128*4882a593Smuzhiyun 	default:
1129*4882a593Smuzhiyun 		m66592->gadget.speed = USB_SPEED_UNKNOWN;
1130*4882a593Smuzhiyun 		pr_err("USB speed unknown\n");
1131*4882a593Smuzhiyun 	}
1132*4882a593Smuzhiyun }
1133*4882a593Smuzhiyun 
irq_device_state(struct m66592 * m66592)1134*4882a593Smuzhiyun static void irq_device_state(struct m66592 *m66592)
1135*4882a593Smuzhiyun {
1136*4882a593Smuzhiyun 	u16 dvsq;
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
1139*4882a593Smuzhiyun 	m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	if (dvsq == M66592_DS_DFLT) {	/* bus reset */
1142*4882a593Smuzhiyun 		usb_gadget_udc_reset(&m66592->gadget, m66592->driver);
1143*4882a593Smuzhiyun 		m66592_update_usb_speed(m66592);
1144*4882a593Smuzhiyun 	}
1145*4882a593Smuzhiyun 	if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
1146*4882a593Smuzhiyun 		m66592_update_usb_speed(m66592);
1147*4882a593Smuzhiyun 	if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
1148*4882a593Smuzhiyun 			&& m66592->gadget.speed == USB_SPEED_UNKNOWN)
1149*4882a593Smuzhiyun 		m66592_update_usb_speed(m66592);
1150*4882a593Smuzhiyun 
1151*4882a593Smuzhiyun 	m66592->old_dvsq = dvsq;
1152*4882a593Smuzhiyun }
1153*4882a593Smuzhiyun 
irq_control_stage(struct m66592 * m66592)1154*4882a593Smuzhiyun static void irq_control_stage(struct m66592 *m66592)
1155*4882a593Smuzhiyun __releases(m66592->lock)
1156*4882a593Smuzhiyun __acquires(m66592->lock)
1157*4882a593Smuzhiyun {
1158*4882a593Smuzhiyun 	struct usb_ctrlrequest ctrl;
1159*4882a593Smuzhiyun 	u16 ctsq;
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 	ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
1162*4882a593Smuzhiyun 	m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
1163*4882a593Smuzhiyun 
1164*4882a593Smuzhiyun 	switch (ctsq) {
1165*4882a593Smuzhiyun 	case M66592_CS_IDST: {
1166*4882a593Smuzhiyun 		struct m66592_ep *ep;
1167*4882a593Smuzhiyun 		struct m66592_request *req;
1168*4882a593Smuzhiyun 		ep = &m66592->ep[0];
1169*4882a593Smuzhiyun 		req = list_entry(ep->queue.next, struct m66592_request, queue);
1170*4882a593Smuzhiyun 		transfer_complete(ep, req, 0);
1171*4882a593Smuzhiyun 		}
1172*4882a593Smuzhiyun 		break;
1173*4882a593Smuzhiyun 
1174*4882a593Smuzhiyun 	case M66592_CS_RDDS:
1175*4882a593Smuzhiyun 	case M66592_CS_WRDS:
1176*4882a593Smuzhiyun 	case M66592_CS_WRND:
1177*4882a593Smuzhiyun 		if (setup_packet(m66592, &ctrl)) {
1178*4882a593Smuzhiyun 			spin_unlock(&m66592->lock);
1179*4882a593Smuzhiyun 			if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
1180*4882a593Smuzhiyun 				pipe_stall(m66592, 0);
1181*4882a593Smuzhiyun 			spin_lock(&m66592->lock);
1182*4882a593Smuzhiyun 		}
1183*4882a593Smuzhiyun 		break;
1184*4882a593Smuzhiyun 	case M66592_CS_RDSS:
1185*4882a593Smuzhiyun 	case M66592_CS_WRSS:
1186*4882a593Smuzhiyun 		control_end(m66592, 0);
1187*4882a593Smuzhiyun 		break;
1188*4882a593Smuzhiyun 	default:
1189*4882a593Smuzhiyun 		pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
1190*4882a593Smuzhiyun 		break;
1191*4882a593Smuzhiyun 	}
1192*4882a593Smuzhiyun }
1193*4882a593Smuzhiyun 
m66592_irq(int irq,void * _m66592)1194*4882a593Smuzhiyun static irqreturn_t m66592_irq(int irq, void *_m66592)
1195*4882a593Smuzhiyun {
1196*4882a593Smuzhiyun 	struct m66592 *m66592 = _m66592;
1197*4882a593Smuzhiyun 	u16 intsts0;
1198*4882a593Smuzhiyun 	u16 intenb0;
1199*4882a593Smuzhiyun 	u16 savepipe;
1200*4882a593Smuzhiyun 	u16 mask0;
1201*4882a593Smuzhiyun 
1202*4882a593Smuzhiyun 	spin_lock(&m66592->lock);
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun 	intsts0 = m66592_read(m66592, M66592_INTSTS0);
1205*4882a593Smuzhiyun 	intenb0 = m66592_read(m66592, M66592_INTENB0);
1206*4882a593Smuzhiyun 
1207*4882a593Smuzhiyun 	if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
1208*4882a593Smuzhiyun 		/*
1209*4882a593Smuzhiyun 		 * When USB clock stops, it cannot read register. Even if a
1210*4882a593Smuzhiyun 		 * clock stops, the interrupt occurs. So this driver turn on
1211*4882a593Smuzhiyun 		 * a clock by this timing and do re-reading of register.
1212*4882a593Smuzhiyun 		 */
1213*4882a593Smuzhiyun 		m66592_start_xclock(m66592);
1214*4882a593Smuzhiyun 		intsts0 = m66592_read(m66592, M66592_INTSTS0);
1215*4882a593Smuzhiyun 		intenb0 = m66592_read(m66592, M66592_INTENB0);
1216*4882a593Smuzhiyun 	}
1217*4882a593Smuzhiyun 
1218*4882a593Smuzhiyun 	savepipe = m66592_read(m66592, M66592_CFIFOSEL);
1219*4882a593Smuzhiyun 
1220*4882a593Smuzhiyun 	mask0 = intsts0 & intenb0;
1221*4882a593Smuzhiyun 	if (mask0) {
1222*4882a593Smuzhiyun 		u16 brdysts = m66592_read(m66592, M66592_BRDYSTS);
1223*4882a593Smuzhiyun 		u16 bempsts = m66592_read(m66592, M66592_BEMPSTS);
1224*4882a593Smuzhiyun 		u16 brdyenb = m66592_read(m66592, M66592_BRDYENB);
1225*4882a593Smuzhiyun 		u16 bempenb = m66592_read(m66592, M66592_BEMPENB);
1226*4882a593Smuzhiyun 
1227*4882a593Smuzhiyun 		if (mask0 & M66592_VBINT) {
1228*4882a593Smuzhiyun 			m66592_write(m66592,  0xffff & ~M66592_VBINT,
1229*4882a593Smuzhiyun 					M66592_INTSTS0);
1230*4882a593Smuzhiyun 			m66592_start_xclock(m66592);
1231*4882a593Smuzhiyun 
1232*4882a593Smuzhiyun 			/* start vbus sampling */
1233*4882a593Smuzhiyun 			m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
1234*4882a593Smuzhiyun 					& M66592_VBSTS;
1235*4882a593Smuzhiyun 			m66592->scount = M66592_MAX_SAMPLING;
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 			mod_timer(&m66592->timer,
1238*4882a593Smuzhiyun 					jiffies + msecs_to_jiffies(50));
1239*4882a593Smuzhiyun 		}
1240*4882a593Smuzhiyun 		if (intsts0 & M66592_DVSQ)
1241*4882a593Smuzhiyun 			irq_device_state(m66592);
1242*4882a593Smuzhiyun 
1243*4882a593Smuzhiyun 		if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
1244*4882a593Smuzhiyun 				&& (brdysts & brdyenb)) {
1245*4882a593Smuzhiyun 			irq_pipe_ready(m66592, brdysts, brdyenb);
1246*4882a593Smuzhiyun 		}
1247*4882a593Smuzhiyun 		if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
1248*4882a593Smuzhiyun 				&& (bempsts & bempenb)) {
1249*4882a593Smuzhiyun 			irq_pipe_empty(m66592, bempsts, bempenb);
1250*4882a593Smuzhiyun 		}
1251*4882a593Smuzhiyun 
1252*4882a593Smuzhiyun 		if (intsts0 & M66592_CTRT)
1253*4882a593Smuzhiyun 			irq_control_stage(m66592);
1254*4882a593Smuzhiyun 	}
1255*4882a593Smuzhiyun 
1256*4882a593Smuzhiyun 	m66592_write(m66592, savepipe, M66592_CFIFOSEL);
1257*4882a593Smuzhiyun 
1258*4882a593Smuzhiyun 	spin_unlock(&m66592->lock);
1259*4882a593Smuzhiyun 	return IRQ_HANDLED;
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun 
m66592_timer(struct timer_list * t)1262*4882a593Smuzhiyun static void m66592_timer(struct timer_list *t)
1263*4882a593Smuzhiyun {
1264*4882a593Smuzhiyun 	struct m66592 *m66592 = from_timer(m66592, t, timer);
1265*4882a593Smuzhiyun 	unsigned long flags;
1266*4882a593Smuzhiyun 	u16 tmp;
1267*4882a593Smuzhiyun 
1268*4882a593Smuzhiyun 	spin_lock_irqsave(&m66592->lock, flags);
1269*4882a593Smuzhiyun 	tmp = m66592_read(m66592, M66592_SYSCFG);
1270*4882a593Smuzhiyun 	if (!(tmp & M66592_RCKE)) {
1271*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
1272*4882a593Smuzhiyun 		udelay(10);
1273*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
1274*4882a593Smuzhiyun 	}
1275*4882a593Smuzhiyun 	if (m66592->scount > 0) {
1276*4882a593Smuzhiyun 		tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
1277*4882a593Smuzhiyun 		if (tmp == m66592->old_vbus) {
1278*4882a593Smuzhiyun 			m66592->scount--;
1279*4882a593Smuzhiyun 			if (m66592->scount == 0) {
1280*4882a593Smuzhiyun 				if (tmp == M66592_VBSTS)
1281*4882a593Smuzhiyun 					m66592_usb_connect(m66592);
1282*4882a593Smuzhiyun 				else
1283*4882a593Smuzhiyun 					m66592_usb_disconnect(m66592);
1284*4882a593Smuzhiyun 			} else {
1285*4882a593Smuzhiyun 				mod_timer(&m66592->timer,
1286*4882a593Smuzhiyun 					jiffies + msecs_to_jiffies(50));
1287*4882a593Smuzhiyun 			}
1288*4882a593Smuzhiyun 		} else {
1289*4882a593Smuzhiyun 			m66592->scount = M66592_MAX_SAMPLING;
1290*4882a593Smuzhiyun 			m66592->old_vbus = tmp;
1291*4882a593Smuzhiyun 			mod_timer(&m66592->timer,
1292*4882a593Smuzhiyun 					jiffies + msecs_to_jiffies(50));
1293*4882a593Smuzhiyun 		}
1294*4882a593Smuzhiyun 	}
1295*4882a593Smuzhiyun 	spin_unlock_irqrestore(&m66592->lock, flags);
1296*4882a593Smuzhiyun }
1297*4882a593Smuzhiyun 
1298*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
m66592_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)1299*4882a593Smuzhiyun static int m66592_enable(struct usb_ep *_ep,
1300*4882a593Smuzhiyun 			 const struct usb_endpoint_descriptor *desc)
1301*4882a593Smuzhiyun {
1302*4882a593Smuzhiyun 	struct m66592_ep *ep;
1303*4882a593Smuzhiyun 
1304*4882a593Smuzhiyun 	ep = container_of(_ep, struct m66592_ep, ep);
1305*4882a593Smuzhiyun 	return alloc_pipe_config(ep, desc);
1306*4882a593Smuzhiyun }
1307*4882a593Smuzhiyun 
m66592_disable(struct usb_ep * _ep)1308*4882a593Smuzhiyun static int m66592_disable(struct usb_ep *_ep)
1309*4882a593Smuzhiyun {
1310*4882a593Smuzhiyun 	struct m66592_ep *ep;
1311*4882a593Smuzhiyun 	struct m66592_request *req;
1312*4882a593Smuzhiyun 	unsigned long flags;
1313*4882a593Smuzhiyun 
1314*4882a593Smuzhiyun 	ep = container_of(_ep, struct m66592_ep, ep);
1315*4882a593Smuzhiyun 	BUG_ON(!ep);
1316*4882a593Smuzhiyun 
1317*4882a593Smuzhiyun 	while (!list_empty(&ep->queue)) {
1318*4882a593Smuzhiyun 		req = list_entry(ep->queue.next, struct m66592_request, queue);
1319*4882a593Smuzhiyun 		spin_lock_irqsave(&ep->m66592->lock, flags);
1320*4882a593Smuzhiyun 		transfer_complete(ep, req, -ECONNRESET);
1321*4882a593Smuzhiyun 		spin_unlock_irqrestore(&ep->m66592->lock, flags);
1322*4882a593Smuzhiyun 	}
1323*4882a593Smuzhiyun 
1324*4882a593Smuzhiyun 	pipe_irq_disable(ep->m66592, ep->pipenum);
1325*4882a593Smuzhiyun 	return free_pipe_config(ep);
1326*4882a593Smuzhiyun }
1327*4882a593Smuzhiyun 
m66592_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)1328*4882a593Smuzhiyun static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
1329*4882a593Smuzhiyun 						gfp_t gfp_flags)
1330*4882a593Smuzhiyun {
1331*4882a593Smuzhiyun 	struct m66592_request *req;
1332*4882a593Smuzhiyun 
1333*4882a593Smuzhiyun 	req = kzalloc(sizeof(struct m66592_request), gfp_flags);
1334*4882a593Smuzhiyun 	if (!req)
1335*4882a593Smuzhiyun 		return NULL;
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 	INIT_LIST_HEAD(&req->queue);
1338*4882a593Smuzhiyun 
1339*4882a593Smuzhiyun 	return &req->req;
1340*4882a593Smuzhiyun }
1341*4882a593Smuzhiyun 
m66592_free_request(struct usb_ep * _ep,struct usb_request * _req)1342*4882a593Smuzhiyun static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
1343*4882a593Smuzhiyun {
1344*4882a593Smuzhiyun 	struct m66592_request *req;
1345*4882a593Smuzhiyun 
1346*4882a593Smuzhiyun 	req = container_of(_req, struct m66592_request, req);
1347*4882a593Smuzhiyun 	kfree(req);
1348*4882a593Smuzhiyun }
1349*4882a593Smuzhiyun 
m66592_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)1350*4882a593Smuzhiyun static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
1351*4882a593Smuzhiyun 			gfp_t gfp_flags)
1352*4882a593Smuzhiyun {
1353*4882a593Smuzhiyun 	struct m66592_ep *ep;
1354*4882a593Smuzhiyun 	struct m66592_request *req;
1355*4882a593Smuzhiyun 	unsigned long flags;
1356*4882a593Smuzhiyun 	int request = 0;
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 	ep = container_of(_ep, struct m66592_ep, ep);
1359*4882a593Smuzhiyun 	req = container_of(_req, struct m66592_request, req);
1360*4882a593Smuzhiyun 
1361*4882a593Smuzhiyun 	if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
1362*4882a593Smuzhiyun 		return -ESHUTDOWN;
1363*4882a593Smuzhiyun 
1364*4882a593Smuzhiyun 	spin_lock_irqsave(&ep->m66592->lock, flags);
1365*4882a593Smuzhiyun 
1366*4882a593Smuzhiyun 	if (list_empty(&ep->queue))
1367*4882a593Smuzhiyun 		request = 1;
1368*4882a593Smuzhiyun 
1369*4882a593Smuzhiyun 	list_add_tail(&req->queue, &ep->queue);
1370*4882a593Smuzhiyun 	req->req.actual = 0;
1371*4882a593Smuzhiyun 	req->req.status = -EINPROGRESS;
1372*4882a593Smuzhiyun 
1373*4882a593Smuzhiyun 	if (ep->ep.desc == NULL)	/* control */
1374*4882a593Smuzhiyun 		start_ep0(ep, req);
1375*4882a593Smuzhiyun 	else {
1376*4882a593Smuzhiyun 		if (request && !ep->busy)
1377*4882a593Smuzhiyun 			start_packet(ep, req);
1378*4882a593Smuzhiyun 	}
1379*4882a593Smuzhiyun 
1380*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ep->m66592->lock, flags);
1381*4882a593Smuzhiyun 
1382*4882a593Smuzhiyun 	return 0;
1383*4882a593Smuzhiyun }
1384*4882a593Smuzhiyun 
m66592_dequeue(struct usb_ep * _ep,struct usb_request * _req)1385*4882a593Smuzhiyun static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1386*4882a593Smuzhiyun {
1387*4882a593Smuzhiyun 	struct m66592_ep *ep;
1388*4882a593Smuzhiyun 	struct m66592_request *req;
1389*4882a593Smuzhiyun 	unsigned long flags;
1390*4882a593Smuzhiyun 
1391*4882a593Smuzhiyun 	ep = container_of(_ep, struct m66592_ep, ep);
1392*4882a593Smuzhiyun 	req = container_of(_req, struct m66592_request, req);
1393*4882a593Smuzhiyun 
1394*4882a593Smuzhiyun 	spin_lock_irqsave(&ep->m66592->lock, flags);
1395*4882a593Smuzhiyun 	if (!list_empty(&ep->queue))
1396*4882a593Smuzhiyun 		transfer_complete(ep, req, -ECONNRESET);
1397*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ep->m66592->lock, flags);
1398*4882a593Smuzhiyun 
1399*4882a593Smuzhiyun 	return 0;
1400*4882a593Smuzhiyun }
1401*4882a593Smuzhiyun 
m66592_set_halt(struct usb_ep * _ep,int value)1402*4882a593Smuzhiyun static int m66592_set_halt(struct usb_ep *_ep, int value)
1403*4882a593Smuzhiyun {
1404*4882a593Smuzhiyun 	struct m66592_ep *ep = container_of(_ep, struct m66592_ep, ep);
1405*4882a593Smuzhiyun 	unsigned long flags;
1406*4882a593Smuzhiyun 	int ret = 0;
1407*4882a593Smuzhiyun 
1408*4882a593Smuzhiyun 	spin_lock_irqsave(&ep->m66592->lock, flags);
1409*4882a593Smuzhiyun 	if (!list_empty(&ep->queue)) {
1410*4882a593Smuzhiyun 		ret = -EAGAIN;
1411*4882a593Smuzhiyun 	} else if (value) {
1412*4882a593Smuzhiyun 		ep->busy = 1;
1413*4882a593Smuzhiyun 		pipe_stall(ep->m66592, ep->pipenum);
1414*4882a593Smuzhiyun 	} else {
1415*4882a593Smuzhiyun 		ep->busy = 0;
1416*4882a593Smuzhiyun 		pipe_stop(ep->m66592, ep->pipenum);
1417*4882a593Smuzhiyun 	}
1418*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ep->m66592->lock, flags);
1419*4882a593Smuzhiyun 	return ret;
1420*4882a593Smuzhiyun }
1421*4882a593Smuzhiyun 
m66592_fifo_flush(struct usb_ep * _ep)1422*4882a593Smuzhiyun static void m66592_fifo_flush(struct usb_ep *_ep)
1423*4882a593Smuzhiyun {
1424*4882a593Smuzhiyun 	struct m66592_ep *ep;
1425*4882a593Smuzhiyun 	unsigned long flags;
1426*4882a593Smuzhiyun 
1427*4882a593Smuzhiyun 	ep = container_of(_ep, struct m66592_ep, ep);
1428*4882a593Smuzhiyun 	spin_lock_irqsave(&ep->m66592->lock, flags);
1429*4882a593Smuzhiyun 	if (list_empty(&ep->queue) && !ep->busy) {
1430*4882a593Smuzhiyun 		pipe_stop(ep->m66592, ep->pipenum);
1431*4882a593Smuzhiyun 		m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
1432*4882a593Smuzhiyun 	}
1433*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ep->m66592->lock, flags);
1434*4882a593Smuzhiyun }
1435*4882a593Smuzhiyun 
1436*4882a593Smuzhiyun static const struct usb_ep_ops m66592_ep_ops = {
1437*4882a593Smuzhiyun 	.enable		= m66592_enable,
1438*4882a593Smuzhiyun 	.disable	= m66592_disable,
1439*4882a593Smuzhiyun 
1440*4882a593Smuzhiyun 	.alloc_request	= m66592_alloc_request,
1441*4882a593Smuzhiyun 	.free_request	= m66592_free_request,
1442*4882a593Smuzhiyun 
1443*4882a593Smuzhiyun 	.queue		= m66592_queue,
1444*4882a593Smuzhiyun 	.dequeue	= m66592_dequeue,
1445*4882a593Smuzhiyun 
1446*4882a593Smuzhiyun 	.set_halt	= m66592_set_halt,
1447*4882a593Smuzhiyun 	.fifo_flush	= m66592_fifo_flush,
1448*4882a593Smuzhiyun };
1449*4882a593Smuzhiyun 
1450*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
m66592_udc_start(struct usb_gadget * g,struct usb_gadget_driver * driver)1451*4882a593Smuzhiyun static int m66592_udc_start(struct usb_gadget *g,
1452*4882a593Smuzhiyun 		struct usb_gadget_driver *driver)
1453*4882a593Smuzhiyun {
1454*4882a593Smuzhiyun 	struct m66592 *m66592 = to_m66592(g);
1455*4882a593Smuzhiyun 
1456*4882a593Smuzhiyun 	/* hook up the driver */
1457*4882a593Smuzhiyun 	driver->driver.bus = NULL;
1458*4882a593Smuzhiyun 	m66592->driver = driver;
1459*4882a593Smuzhiyun 
1460*4882a593Smuzhiyun 	m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1461*4882a593Smuzhiyun 	if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
1462*4882a593Smuzhiyun 		m66592_start_xclock(m66592);
1463*4882a593Smuzhiyun 		/* start vbus sampling */
1464*4882a593Smuzhiyun 		m66592->old_vbus = m66592_read(m66592,
1465*4882a593Smuzhiyun 					 M66592_INTSTS0) & M66592_VBSTS;
1466*4882a593Smuzhiyun 		m66592->scount = M66592_MAX_SAMPLING;
1467*4882a593Smuzhiyun 		mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
1468*4882a593Smuzhiyun 	}
1469*4882a593Smuzhiyun 
1470*4882a593Smuzhiyun 	return 0;
1471*4882a593Smuzhiyun }
1472*4882a593Smuzhiyun 
m66592_udc_stop(struct usb_gadget * g)1473*4882a593Smuzhiyun static int m66592_udc_stop(struct usb_gadget *g)
1474*4882a593Smuzhiyun {
1475*4882a593Smuzhiyun 	struct m66592 *m66592 = to_m66592(g);
1476*4882a593Smuzhiyun 
1477*4882a593Smuzhiyun 	m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1478*4882a593Smuzhiyun 
1479*4882a593Smuzhiyun 	init_controller(m66592);
1480*4882a593Smuzhiyun 	disable_controller(m66592);
1481*4882a593Smuzhiyun 
1482*4882a593Smuzhiyun 	m66592->driver = NULL;
1483*4882a593Smuzhiyun 
1484*4882a593Smuzhiyun 	return 0;
1485*4882a593Smuzhiyun }
1486*4882a593Smuzhiyun 
1487*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
m66592_get_frame(struct usb_gadget * _gadget)1488*4882a593Smuzhiyun static int m66592_get_frame(struct usb_gadget *_gadget)
1489*4882a593Smuzhiyun {
1490*4882a593Smuzhiyun 	struct m66592 *m66592 = gadget_to_m66592(_gadget);
1491*4882a593Smuzhiyun 	return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
1492*4882a593Smuzhiyun }
1493*4882a593Smuzhiyun 
m66592_pullup(struct usb_gadget * gadget,int is_on)1494*4882a593Smuzhiyun static int m66592_pullup(struct usb_gadget *gadget, int is_on)
1495*4882a593Smuzhiyun {
1496*4882a593Smuzhiyun 	struct m66592 *m66592 = gadget_to_m66592(gadget);
1497*4882a593Smuzhiyun 	unsigned long flags;
1498*4882a593Smuzhiyun 
1499*4882a593Smuzhiyun 	spin_lock_irqsave(&m66592->lock, flags);
1500*4882a593Smuzhiyun 	if (is_on)
1501*4882a593Smuzhiyun 		m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
1502*4882a593Smuzhiyun 	else
1503*4882a593Smuzhiyun 		m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
1504*4882a593Smuzhiyun 	spin_unlock_irqrestore(&m66592->lock, flags);
1505*4882a593Smuzhiyun 
1506*4882a593Smuzhiyun 	return 0;
1507*4882a593Smuzhiyun }
1508*4882a593Smuzhiyun 
1509*4882a593Smuzhiyun static const struct usb_gadget_ops m66592_gadget_ops = {
1510*4882a593Smuzhiyun 	.get_frame		= m66592_get_frame,
1511*4882a593Smuzhiyun 	.udc_start		= m66592_udc_start,
1512*4882a593Smuzhiyun 	.udc_stop		= m66592_udc_stop,
1513*4882a593Smuzhiyun 	.pullup			= m66592_pullup,
1514*4882a593Smuzhiyun };
1515*4882a593Smuzhiyun 
m66592_remove(struct platform_device * pdev)1516*4882a593Smuzhiyun static int m66592_remove(struct platform_device *pdev)
1517*4882a593Smuzhiyun {
1518*4882a593Smuzhiyun 	struct m66592		*m66592 = platform_get_drvdata(pdev);
1519*4882a593Smuzhiyun 
1520*4882a593Smuzhiyun 	usb_del_gadget_udc(&m66592->gadget);
1521*4882a593Smuzhiyun 
1522*4882a593Smuzhiyun 	del_timer_sync(&m66592->timer);
1523*4882a593Smuzhiyun 	iounmap(m66592->reg);
1524*4882a593Smuzhiyun 	free_irq(platform_get_irq(pdev, 0), m66592);
1525*4882a593Smuzhiyun 	m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1526*4882a593Smuzhiyun 	if (m66592->pdata->on_chip) {
1527*4882a593Smuzhiyun 		clk_disable(m66592->clk);
1528*4882a593Smuzhiyun 		clk_put(m66592->clk);
1529*4882a593Smuzhiyun 	}
1530*4882a593Smuzhiyun 	kfree(m66592);
1531*4882a593Smuzhiyun 	return 0;
1532*4882a593Smuzhiyun }
1533*4882a593Smuzhiyun 
nop_completion(struct usb_ep * ep,struct usb_request * r)1534*4882a593Smuzhiyun static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1535*4882a593Smuzhiyun {
1536*4882a593Smuzhiyun }
1537*4882a593Smuzhiyun 
m66592_probe(struct platform_device * pdev)1538*4882a593Smuzhiyun static int m66592_probe(struct platform_device *pdev)
1539*4882a593Smuzhiyun {
1540*4882a593Smuzhiyun 	struct resource *res, *ires;
1541*4882a593Smuzhiyun 	void __iomem *reg = NULL;
1542*4882a593Smuzhiyun 	struct m66592 *m66592 = NULL;
1543*4882a593Smuzhiyun 	char clk_name[8];
1544*4882a593Smuzhiyun 	int ret = 0;
1545*4882a593Smuzhiyun 	int i;
1546*4882a593Smuzhiyun 
1547*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1548*4882a593Smuzhiyun 	if (!res) {
1549*4882a593Smuzhiyun 		ret = -ENODEV;
1550*4882a593Smuzhiyun 		pr_err("platform_get_resource error.\n");
1551*4882a593Smuzhiyun 		goto clean_up;
1552*4882a593Smuzhiyun 	}
1553*4882a593Smuzhiyun 
1554*4882a593Smuzhiyun 	ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1555*4882a593Smuzhiyun 	if (!ires) {
1556*4882a593Smuzhiyun 		ret = -ENODEV;
1557*4882a593Smuzhiyun 		dev_err(&pdev->dev,
1558*4882a593Smuzhiyun 			"platform_get_resource IORESOURCE_IRQ error.\n");
1559*4882a593Smuzhiyun 		goto clean_up;
1560*4882a593Smuzhiyun 	}
1561*4882a593Smuzhiyun 
1562*4882a593Smuzhiyun 	reg = ioremap(res->start, resource_size(res));
1563*4882a593Smuzhiyun 	if (reg == NULL) {
1564*4882a593Smuzhiyun 		ret = -ENOMEM;
1565*4882a593Smuzhiyun 		pr_err("ioremap error.\n");
1566*4882a593Smuzhiyun 		goto clean_up;
1567*4882a593Smuzhiyun 	}
1568*4882a593Smuzhiyun 
1569*4882a593Smuzhiyun 	if (dev_get_platdata(&pdev->dev) == NULL) {
1570*4882a593Smuzhiyun 		dev_err(&pdev->dev, "no platform data\n");
1571*4882a593Smuzhiyun 		ret = -ENODEV;
1572*4882a593Smuzhiyun 		goto clean_up;
1573*4882a593Smuzhiyun 	}
1574*4882a593Smuzhiyun 
1575*4882a593Smuzhiyun 	/* initialize ucd */
1576*4882a593Smuzhiyun 	m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
1577*4882a593Smuzhiyun 	if (m66592 == NULL) {
1578*4882a593Smuzhiyun 		ret = -ENOMEM;
1579*4882a593Smuzhiyun 		goto clean_up;
1580*4882a593Smuzhiyun 	}
1581*4882a593Smuzhiyun 
1582*4882a593Smuzhiyun 	m66592->pdata = dev_get_platdata(&pdev->dev);
1583*4882a593Smuzhiyun 	m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
1584*4882a593Smuzhiyun 
1585*4882a593Smuzhiyun 	spin_lock_init(&m66592->lock);
1586*4882a593Smuzhiyun 	platform_set_drvdata(pdev, m66592);
1587*4882a593Smuzhiyun 
1588*4882a593Smuzhiyun 	m66592->gadget.ops = &m66592_gadget_ops;
1589*4882a593Smuzhiyun 	m66592->gadget.max_speed = USB_SPEED_HIGH;
1590*4882a593Smuzhiyun 	m66592->gadget.name = udc_name;
1591*4882a593Smuzhiyun 
1592*4882a593Smuzhiyun 	timer_setup(&m66592->timer, m66592_timer, 0);
1593*4882a593Smuzhiyun 	m66592->reg = reg;
1594*4882a593Smuzhiyun 
1595*4882a593Smuzhiyun 	ret = request_irq(ires->start, m66592_irq, IRQF_SHARED,
1596*4882a593Smuzhiyun 			udc_name, m66592);
1597*4882a593Smuzhiyun 	if (ret < 0) {
1598*4882a593Smuzhiyun 		pr_err("request_irq error (%d)\n", ret);
1599*4882a593Smuzhiyun 		goto clean_up;
1600*4882a593Smuzhiyun 	}
1601*4882a593Smuzhiyun 
1602*4882a593Smuzhiyun 	if (m66592->pdata->on_chip) {
1603*4882a593Smuzhiyun 		snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
1604*4882a593Smuzhiyun 		m66592->clk = clk_get(&pdev->dev, clk_name);
1605*4882a593Smuzhiyun 		if (IS_ERR(m66592->clk)) {
1606*4882a593Smuzhiyun 			dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
1607*4882a593Smuzhiyun 				clk_name);
1608*4882a593Smuzhiyun 			ret = PTR_ERR(m66592->clk);
1609*4882a593Smuzhiyun 			goto clean_up2;
1610*4882a593Smuzhiyun 		}
1611*4882a593Smuzhiyun 		clk_enable(m66592->clk);
1612*4882a593Smuzhiyun 	}
1613*4882a593Smuzhiyun 
1614*4882a593Smuzhiyun 	INIT_LIST_HEAD(&m66592->gadget.ep_list);
1615*4882a593Smuzhiyun 	m66592->gadget.ep0 = &m66592->ep[0].ep;
1616*4882a593Smuzhiyun 	INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
1617*4882a593Smuzhiyun 	for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
1618*4882a593Smuzhiyun 		struct m66592_ep *ep = &m66592->ep[i];
1619*4882a593Smuzhiyun 
1620*4882a593Smuzhiyun 		if (i != 0) {
1621*4882a593Smuzhiyun 			INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
1622*4882a593Smuzhiyun 			list_add_tail(&m66592->ep[i].ep.ep_list,
1623*4882a593Smuzhiyun 					&m66592->gadget.ep_list);
1624*4882a593Smuzhiyun 		}
1625*4882a593Smuzhiyun 		ep->m66592 = m66592;
1626*4882a593Smuzhiyun 		INIT_LIST_HEAD(&ep->queue);
1627*4882a593Smuzhiyun 		ep->ep.name = m66592_ep_name[i];
1628*4882a593Smuzhiyun 		ep->ep.ops = &m66592_ep_ops;
1629*4882a593Smuzhiyun 		usb_ep_set_maxpacket_limit(&ep->ep, 512);
1630*4882a593Smuzhiyun 
1631*4882a593Smuzhiyun 		if (i == 0) {
1632*4882a593Smuzhiyun 			ep->ep.caps.type_control = true;
1633*4882a593Smuzhiyun 		} else {
1634*4882a593Smuzhiyun 			ep->ep.caps.type_iso = true;
1635*4882a593Smuzhiyun 			ep->ep.caps.type_bulk = true;
1636*4882a593Smuzhiyun 			ep->ep.caps.type_int = true;
1637*4882a593Smuzhiyun 		}
1638*4882a593Smuzhiyun 
1639*4882a593Smuzhiyun 		ep->ep.caps.dir_in = true;
1640*4882a593Smuzhiyun 		ep->ep.caps.dir_out = true;
1641*4882a593Smuzhiyun 	}
1642*4882a593Smuzhiyun 	usb_ep_set_maxpacket_limit(&m66592->ep[0].ep, 64);
1643*4882a593Smuzhiyun 	m66592->ep[0].pipenum = 0;
1644*4882a593Smuzhiyun 	m66592->ep[0].fifoaddr = M66592_CFIFO;
1645*4882a593Smuzhiyun 	m66592->ep[0].fifosel = M66592_CFIFOSEL;
1646*4882a593Smuzhiyun 	m66592->ep[0].fifoctr = M66592_CFIFOCTR;
1647*4882a593Smuzhiyun 	m66592->ep[0].fifotrn = 0;
1648*4882a593Smuzhiyun 	m66592->ep[0].pipectr = get_pipectr_addr(0);
1649*4882a593Smuzhiyun 	m66592->pipenum2ep[0] = &m66592->ep[0];
1650*4882a593Smuzhiyun 	m66592->epaddr2ep[0] = &m66592->ep[0];
1651*4882a593Smuzhiyun 
1652*4882a593Smuzhiyun 	m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
1653*4882a593Smuzhiyun 	if (m66592->ep0_req == NULL) {
1654*4882a593Smuzhiyun 		ret = -ENOMEM;
1655*4882a593Smuzhiyun 		goto clean_up3;
1656*4882a593Smuzhiyun 	}
1657*4882a593Smuzhiyun 	m66592->ep0_req->complete = nop_completion;
1658*4882a593Smuzhiyun 
1659*4882a593Smuzhiyun 	init_controller(m66592);
1660*4882a593Smuzhiyun 
1661*4882a593Smuzhiyun 	ret = usb_add_gadget_udc(&pdev->dev, &m66592->gadget);
1662*4882a593Smuzhiyun 	if (ret)
1663*4882a593Smuzhiyun 		goto err_add_udc;
1664*4882a593Smuzhiyun 
1665*4882a593Smuzhiyun 	dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1666*4882a593Smuzhiyun 	return 0;
1667*4882a593Smuzhiyun 
1668*4882a593Smuzhiyun err_add_udc:
1669*4882a593Smuzhiyun 	m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1670*4882a593Smuzhiyun 	m66592->ep0_req = NULL;
1671*4882a593Smuzhiyun clean_up3:
1672*4882a593Smuzhiyun 	if (m66592->pdata->on_chip) {
1673*4882a593Smuzhiyun 		clk_disable(m66592->clk);
1674*4882a593Smuzhiyun 		clk_put(m66592->clk);
1675*4882a593Smuzhiyun 	}
1676*4882a593Smuzhiyun clean_up2:
1677*4882a593Smuzhiyun 	free_irq(ires->start, m66592);
1678*4882a593Smuzhiyun clean_up:
1679*4882a593Smuzhiyun 	if (m66592) {
1680*4882a593Smuzhiyun 		if (m66592->ep0_req)
1681*4882a593Smuzhiyun 			m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1682*4882a593Smuzhiyun 		kfree(m66592);
1683*4882a593Smuzhiyun 	}
1684*4882a593Smuzhiyun 	if (reg)
1685*4882a593Smuzhiyun 		iounmap(reg);
1686*4882a593Smuzhiyun 
1687*4882a593Smuzhiyun 	return ret;
1688*4882a593Smuzhiyun }
1689*4882a593Smuzhiyun 
1690*4882a593Smuzhiyun /*-------------------------------------------------------------------------*/
1691*4882a593Smuzhiyun static struct platform_driver m66592_driver = {
1692*4882a593Smuzhiyun 	.remove =	m66592_remove,
1693*4882a593Smuzhiyun 	.driver		= {
1694*4882a593Smuzhiyun 		.name =	udc_name,
1695*4882a593Smuzhiyun 	},
1696*4882a593Smuzhiyun };
1697*4882a593Smuzhiyun 
1698*4882a593Smuzhiyun module_platform_driver_probe(m66592_driver, m66592_probe);
1699