1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the Atmel USBA high speed USB device controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2005-2007 Atmel Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #ifndef __LINUX_USB_GADGET_USBA_UDC_H__
8*4882a593Smuzhiyun #define __LINUX_USB_GADGET_USBA_UDC_H__
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /* USB register offsets */
13*4882a593Smuzhiyun #define USBA_CTRL 0x0000
14*4882a593Smuzhiyun #define USBA_FNUM 0x0004
15*4882a593Smuzhiyun #define USBA_INT_ENB 0x0010
16*4882a593Smuzhiyun #define USBA_INT_STA 0x0014
17*4882a593Smuzhiyun #define USBA_INT_CLR 0x0018
18*4882a593Smuzhiyun #define USBA_EPT_RST 0x001c
19*4882a593Smuzhiyun #define USBA_TST 0x00e0
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* USB endpoint register offsets */
22*4882a593Smuzhiyun #define USBA_EPT_CFG 0x0000
23*4882a593Smuzhiyun #define USBA_EPT_CTL_ENB 0x0004
24*4882a593Smuzhiyun #define USBA_EPT_CTL_DIS 0x0008
25*4882a593Smuzhiyun #define USBA_EPT_CTL 0x000c
26*4882a593Smuzhiyun #define USBA_EPT_SET_STA 0x0014
27*4882a593Smuzhiyun #define USBA_EPT_CLR_STA 0x0018
28*4882a593Smuzhiyun #define USBA_EPT_STA 0x001c
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* USB DMA register offsets */
31*4882a593Smuzhiyun #define USBA_DMA_NXT_DSC 0x0000
32*4882a593Smuzhiyun #define USBA_DMA_ADDRESS 0x0004
33*4882a593Smuzhiyun #define USBA_DMA_CONTROL 0x0008
34*4882a593Smuzhiyun #define USBA_DMA_STATUS 0x000c
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* Bitfields in CTRL */
37*4882a593Smuzhiyun #define USBA_DEV_ADDR_OFFSET 0
38*4882a593Smuzhiyun #define USBA_DEV_ADDR_SIZE 7
39*4882a593Smuzhiyun #define USBA_FADDR_EN (1 << 7)
40*4882a593Smuzhiyun #define USBA_EN_USBA (1 << 8)
41*4882a593Smuzhiyun #define USBA_DETACH (1 << 9)
42*4882a593Smuzhiyun #define USBA_REMOTE_WAKE_UP (1 << 10)
43*4882a593Smuzhiyun #define USBA_PULLD_DIS (1 << 11)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS)
46*4882a593Smuzhiyun #define USBA_DISABLE_MASK USBA_DETACH
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Bitfields in FNUM */
49*4882a593Smuzhiyun #define USBA_MICRO_FRAME_NUM_OFFSET 0
50*4882a593Smuzhiyun #define USBA_MICRO_FRAME_NUM_SIZE 3
51*4882a593Smuzhiyun #define USBA_FRAME_NUMBER_OFFSET 3
52*4882a593Smuzhiyun #define USBA_FRAME_NUMBER_SIZE 11
53*4882a593Smuzhiyun #define USBA_FRAME_NUM_ERROR (1 << 31)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Bitfields in INT_ENB/INT_STA/INT_CLR */
56*4882a593Smuzhiyun #define USBA_HIGH_SPEED (1 << 0)
57*4882a593Smuzhiyun #define USBA_DET_SUSPEND (1 << 1)
58*4882a593Smuzhiyun #define USBA_MICRO_SOF (1 << 2)
59*4882a593Smuzhiyun #define USBA_SOF (1 << 3)
60*4882a593Smuzhiyun #define USBA_END_OF_RESET (1 << 4)
61*4882a593Smuzhiyun #define USBA_WAKE_UP (1 << 5)
62*4882a593Smuzhiyun #define USBA_END_OF_RESUME (1 << 6)
63*4882a593Smuzhiyun #define USBA_UPSTREAM_RESUME (1 << 7)
64*4882a593Smuzhiyun #define USBA_EPT_INT_OFFSET 8
65*4882a593Smuzhiyun #define USBA_EPT_INT_SIZE 16
66*4882a593Smuzhiyun #define USBA_DMA_INT_OFFSET 24
67*4882a593Smuzhiyun #define USBA_DMA_INT_SIZE 8
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Bitfields in EPT_RST */
70*4882a593Smuzhiyun #define USBA_RST_OFFSET 0
71*4882a593Smuzhiyun #define USBA_RST_SIZE 16
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* Bitfields in USBA_TST */
74*4882a593Smuzhiyun #define USBA_SPEED_CFG_OFFSET 0
75*4882a593Smuzhiyun #define USBA_SPEED_CFG_SIZE 2
76*4882a593Smuzhiyun #define USBA_TST_J_MODE (1 << 2)
77*4882a593Smuzhiyun #define USBA_TST_K_MODE (1 << 3)
78*4882a593Smuzhiyun #define USBA_TST_PKT_MODE (1 << 4)
79*4882a593Smuzhiyun #define USBA_OPMODE2 (1 << 5)
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Bitfields in EPT_CFG */
82*4882a593Smuzhiyun #define USBA_EPT_SIZE_OFFSET 0
83*4882a593Smuzhiyun #define USBA_EPT_SIZE_SIZE 3
84*4882a593Smuzhiyun #define USBA_EPT_DIR_IN (1 << 3)
85*4882a593Smuzhiyun #define USBA_EPT_TYPE_OFFSET 4
86*4882a593Smuzhiyun #define USBA_EPT_TYPE_SIZE 2
87*4882a593Smuzhiyun #define USBA_BK_NUMBER_OFFSET 6
88*4882a593Smuzhiyun #define USBA_BK_NUMBER_SIZE 2
89*4882a593Smuzhiyun #define USBA_NB_TRANS_OFFSET 8
90*4882a593Smuzhiyun #define USBA_NB_TRANS_SIZE 2
91*4882a593Smuzhiyun #define USBA_EPT_MAPPED (1 << 31)
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
94*4882a593Smuzhiyun #define USBA_EPT_ENABLE (1 << 0)
95*4882a593Smuzhiyun #define USBA_AUTO_VALID (1 << 1)
96*4882a593Smuzhiyun #define USBA_INTDIS_DMA (1 << 3)
97*4882a593Smuzhiyun #define USBA_NYET_DIS (1 << 4)
98*4882a593Smuzhiyun #define USBA_DATAX_RX (1 << 6)
99*4882a593Smuzhiyun #define USBA_MDATA_RX (1 << 7)
100*4882a593Smuzhiyun /* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
101*4882a593Smuzhiyun #define USBA_BUSY_BANK_IE (1 << 18)
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
104*4882a593Smuzhiyun #define USBA_FORCE_STALL (1 << 5)
105*4882a593Smuzhiyun #define USBA_TOGGLE_CLR (1 << 6)
106*4882a593Smuzhiyun #define USBA_TOGGLE_SEQ_OFFSET 6
107*4882a593Smuzhiyun #define USBA_TOGGLE_SEQ_SIZE 2
108*4882a593Smuzhiyun #define USBA_ERR_OVFLW (1 << 8)
109*4882a593Smuzhiyun #define USBA_RX_BK_RDY (1 << 9)
110*4882a593Smuzhiyun #define USBA_KILL_BANK (1 << 9)
111*4882a593Smuzhiyun #define USBA_TX_COMPLETE (1 << 10)
112*4882a593Smuzhiyun #define USBA_TX_PK_RDY (1 << 11)
113*4882a593Smuzhiyun #define USBA_ISO_ERR_TRANS (1 << 11)
114*4882a593Smuzhiyun #define USBA_RX_SETUP (1 << 12)
115*4882a593Smuzhiyun #define USBA_ISO_ERR_FLOW (1 << 12)
116*4882a593Smuzhiyun #define USBA_STALL_SENT (1 << 13)
117*4882a593Smuzhiyun #define USBA_ISO_ERR_CRC (1 << 13)
118*4882a593Smuzhiyun #define USBA_ISO_ERR_NBTRANS (1 << 13)
119*4882a593Smuzhiyun #define USBA_NAK_IN (1 << 14)
120*4882a593Smuzhiyun #define USBA_ISO_ERR_FLUSH (1 << 14)
121*4882a593Smuzhiyun #define USBA_NAK_OUT (1 << 15)
122*4882a593Smuzhiyun #define USBA_CURRENT_BANK_OFFSET 16
123*4882a593Smuzhiyun #define USBA_CURRENT_BANK_SIZE 2
124*4882a593Smuzhiyun #define USBA_BUSY_BANKS_OFFSET 18
125*4882a593Smuzhiyun #define USBA_BUSY_BANKS_SIZE 2
126*4882a593Smuzhiyun #define USBA_BYTE_COUNT_OFFSET 20
127*4882a593Smuzhiyun #define USBA_BYTE_COUNT_SIZE 11
128*4882a593Smuzhiyun #define USBA_SHORT_PACKET (1 << 31)
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* Bitfields in DMA_CONTROL */
131*4882a593Smuzhiyun #define USBA_DMA_CH_EN (1 << 0)
132*4882a593Smuzhiyun #define USBA_DMA_LINK (1 << 1)
133*4882a593Smuzhiyun #define USBA_DMA_END_TR_EN (1 << 2)
134*4882a593Smuzhiyun #define USBA_DMA_END_BUF_EN (1 << 3)
135*4882a593Smuzhiyun #define USBA_DMA_END_TR_IE (1 << 4)
136*4882a593Smuzhiyun #define USBA_DMA_END_BUF_IE (1 << 5)
137*4882a593Smuzhiyun #define USBA_DMA_DESC_LOAD_IE (1 << 6)
138*4882a593Smuzhiyun #define USBA_DMA_BURST_LOCK (1 << 7)
139*4882a593Smuzhiyun #define USBA_DMA_BUF_LEN_OFFSET 16
140*4882a593Smuzhiyun #define USBA_DMA_BUF_LEN_SIZE 16
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* Bitfields in DMA_STATUS */
143*4882a593Smuzhiyun #define USBA_DMA_CH_ACTIVE (1 << 1)
144*4882a593Smuzhiyun #define USBA_DMA_END_TR_ST (1 << 4)
145*4882a593Smuzhiyun #define USBA_DMA_END_BUF_ST (1 << 5)
146*4882a593Smuzhiyun #define USBA_DMA_DESC_LOAD_ST (1 << 6)
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* Constants for SPEED_CFG */
149*4882a593Smuzhiyun #define USBA_SPEED_CFG_NORMAL 0
150*4882a593Smuzhiyun #define USBA_SPEED_CFG_FORCE_HIGH 2
151*4882a593Smuzhiyun #define USBA_SPEED_CFG_FORCE_FULL 3
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* Constants for EPT_SIZE */
154*4882a593Smuzhiyun #define USBA_EPT_SIZE_8 0
155*4882a593Smuzhiyun #define USBA_EPT_SIZE_16 1
156*4882a593Smuzhiyun #define USBA_EPT_SIZE_32 2
157*4882a593Smuzhiyun #define USBA_EPT_SIZE_64 3
158*4882a593Smuzhiyun #define USBA_EPT_SIZE_128 4
159*4882a593Smuzhiyun #define USBA_EPT_SIZE_256 5
160*4882a593Smuzhiyun #define USBA_EPT_SIZE_512 6
161*4882a593Smuzhiyun #define USBA_EPT_SIZE_1024 7
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /* Constants for EPT_TYPE */
164*4882a593Smuzhiyun #define USBA_EPT_TYPE_CONTROL 0
165*4882a593Smuzhiyun #define USBA_EPT_TYPE_ISO 1
166*4882a593Smuzhiyun #define USBA_EPT_TYPE_BULK 2
167*4882a593Smuzhiyun #define USBA_EPT_TYPE_INT 3
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /* Constants for BK_NUMBER */
170*4882a593Smuzhiyun #define USBA_BK_NUMBER_ZERO 0
171*4882a593Smuzhiyun #define USBA_BK_NUMBER_ONE 1
172*4882a593Smuzhiyun #define USBA_BK_NUMBER_DOUBLE 2
173*4882a593Smuzhiyun #define USBA_BK_NUMBER_TRIPLE 3
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /* Bit manipulation macros */
176*4882a593Smuzhiyun #define USBA_BF(name, value) \
177*4882a593Smuzhiyun (((value) & ((1 << USBA_##name##_SIZE) - 1)) \
178*4882a593Smuzhiyun << USBA_##name##_OFFSET)
179*4882a593Smuzhiyun #define USBA_BFEXT(name, value) \
180*4882a593Smuzhiyun (((value) >> USBA_##name##_OFFSET) \
181*4882a593Smuzhiyun & ((1 << USBA_##name##_SIZE) - 1))
182*4882a593Smuzhiyun #define USBA_BFINS(name, value, old) \
183*4882a593Smuzhiyun (((old) & ~(((1 << USBA_##name##_SIZE) - 1) \
184*4882a593Smuzhiyun << USBA_##name##_OFFSET)) \
185*4882a593Smuzhiyun | USBA_BF(name, value))
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /* Register access macros */
188*4882a593Smuzhiyun #define usba_readl(udc, reg) \
189*4882a593Smuzhiyun readl_relaxed((udc)->regs + USBA_##reg)
190*4882a593Smuzhiyun #define usba_writel(udc, reg, value) \
191*4882a593Smuzhiyun writel_relaxed((value), (udc)->regs + USBA_##reg)
192*4882a593Smuzhiyun #define usba_ep_readl(ep, reg) \
193*4882a593Smuzhiyun readl_relaxed((ep)->ep_regs + USBA_EPT_##reg)
194*4882a593Smuzhiyun #define usba_ep_writel(ep, reg, value) \
195*4882a593Smuzhiyun writel_relaxed((value), (ep)->ep_regs + USBA_EPT_##reg)
196*4882a593Smuzhiyun #define usba_dma_readl(ep, reg) \
197*4882a593Smuzhiyun readl_relaxed((ep)->dma_regs + USBA_DMA_##reg)
198*4882a593Smuzhiyun #define usba_dma_writel(ep, reg, value) \
199*4882a593Smuzhiyun writel_relaxed((value), (ep)->dma_regs + USBA_DMA_##reg)
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun /* Calculate base address for a given endpoint or DMA controller */
202*4882a593Smuzhiyun #define USBA_EPT_BASE(x) (0x100 + (x) * 0x20)
203*4882a593Smuzhiyun #define USBA_DMA_BASE(x) (0x300 + (x) * 0x10)
204*4882a593Smuzhiyun #define USBA_FIFO_BASE(x) ((x) << 16)
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /* Synth parameters */
207*4882a593Smuzhiyun #define USBA_NR_DMAS 7
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun #define EP0_FIFO_SIZE 64
210*4882a593Smuzhiyun #define EP0_EPT_SIZE USBA_EPT_SIZE_64
211*4882a593Smuzhiyun #define EP0_NR_BANKS 1
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun #define FIFO_IOMEM_ID 0
214*4882a593Smuzhiyun #define CTRL_IOMEM_ID 1
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun #define DBG_ERR 0x0001 /* report all error returns */
217*4882a593Smuzhiyun #define DBG_HW 0x0002 /* debug hardware initialization */
218*4882a593Smuzhiyun #define DBG_GADGET 0x0004 /* calls to/from gadget driver */
219*4882a593Smuzhiyun #define DBG_INT 0x0008 /* interrupts */
220*4882a593Smuzhiyun #define DBG_BUS 0x0010 /* report changes in bus state */
221*4882a593Smuzhiyun #define DBG_QUEUE 0x0020 /* debug request queue processing */
222*4882a593Smuzhiyun #define DBG_FIFO 0x0040 /* debug FIFO contents */
223*4882a593Smuzhiyun #define DBG_DMA 0x0080 /* debug DMA handling */
224*4882a593Smuzhiyun #define DBG_REQ 0x0100 /* print out queued request length */
225*4882a593Smuzhiyun #define DBG_ALL 0xffff
226*4882a593Smuzhiyun #define DBG_NONE 0x0000
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun #define DEBUG_LEVEL (DBG_ERR)
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun #define DBG(level, fmt, ...) \
231*4882a593Smuzhiyun do { \
232*4882a593Smuzhiyun if ((level) & DEBUG_LEVEL) \
233*4882a593Smuzhiyun pr_debug("udc: " fmt, ## __VA_ARGS__); \
234*4882a593Smuzhiyun } while (0)
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun enum usba_ctrl_state {
237*4882a593Smuzhiyun WAIT_FOR_SETUP,
238*4882a593Smuzhiyun DATA_STAGE_IN,
239*4882a593Smuzhiyun DATA_STAGE_OUT,
240*4882a593Smuzhiyun STATUS_STAGE_IN,
241*4882a593Smuzhiyun STATUS_STAGE_OUT,
242*4882a593Smuzhiyun STATUS_STAGE_ADDR,
243*4882a593Smuzhiyun STATUS_STAGE_TEST,
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun /*
246*4882a593Smuzhiyun EP_STATE_IDLE,
247*4882a593Smuzhiyun EP_STATE_SETUP,
248*4882a593Smuzhiyun EP_STATE_IN_DATA,
249*4882a593Smuzhiyun EP_STATE_OUT_DATA,
250*4882a593Smuzhiyun EP_STATE_SET_ADDR_STATUS,
251*4882a593Smuzhiyun EP_STATE_RX_STATUS,
252*4882a593Smuzhiyun EP_STATE_TX_STATUS,
253*4882a593Smuzhiyun EP_STATE_HALT,
254*4882a593Smuzhiyun */
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun struct usba_dma_desc {
257*4882a593Smuzhiyun dma_addr_t next;
258*4882a593Smuzhiyun dma_addr_t addr;
259*4882a593Smuzhiyun u32 ctrl;
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun struct usba_fifo_cfg {
263*4882a593Smuzhiyun u8 hw_ep_num;
264*4882a593Smuzhiyun u16 fifo_size;
265*4882a593Smuzhiyun u8 nr_banks;
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun struct usba_ep {
269*4882a593Smuzhiyun int state;
270*4882a593Smuzhiyun void __iomem *ep_regs;
271*4882a593Smuzhiyun void __iomem *dma_regs;
272*4882a593Smuzhiyun void __iomem *fifo;
273*4882a593Smuzhiyun char name[8];
274*4882a593Smuzhiyun struct usb_ep ep;
275*4882a593Smuzhiyun struct usba_udc *udc;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun struct list_head queue;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun u16 fifo_size;
280*4882a593Smuzhiyun u8 nr_banks;
281*4882a593Smuzhiyun u8 index;
282*4882a593Smuzhiyun unsigned int can_dma:1;
283*4882a593Smuzhiyun unsigned int can_isoc:1;
284*4882a593Smuzhiyun unsigned int is_isoc:1;
285*4882a593Smuzhiyun unsigned int is_in:1;
286*4882a593Smuzhiyun unsigned long ept_cfg;
287*4882a593Smuzhiyun #ifdef CONFIG_USB_GADGET_DEBUG_FS
288*4882a593Smuzhiyun u32 last_dma_status;
289*4882a593Smuzhiyun struct dentry *debugfs_dir;
290*4882a593Smuzhiyun #endif
291*4882a593Smuzhiyun };
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun struct usba_ep_config {
294*4882a593Smuzhiyun u8 nr_banks;
295*4882a593Smuzhiyun unsigned int can_dma:1;
296*4882a593Smuzhiyun unsigned int can_isoc:1;
297*4882a593Smuzhiyun };
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun struct usba_request {
300*4882a593Smuzhiyun struct usb_request req;
301*4882a593Smuzhiyun struct list_head queue;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun u32 ctrl;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun unsigned int submitted:1;
306*4882a593Smuzhiyun unsigned int last_transaction:1;
307*4882a593Smuzhiyun unsigned int using_dma:1;
308*4882a593Smuzhiyun unsigned int mapped:1;
309*4882a593Smuzhiyun };
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun struct usba_udc_errata {
312*4882a593Smuzhiyun void (*toggle_bias)(struct usba_udc *udc, int is_on);
313*4882a593Smuzhiyun void (*pulse_bias)(struct usba_udc *udc);
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun struct usba_udc_config {
317*4882a593Smuzhiyun const struct usba_udc_errata *errata;
318*4882a593Smuzhiyun const struct usba_ep_config *config;
319*4882a593Smuzhiyun const int num_ep;
320*4882a593Smuzhiyun const bool ep_prealloc;
321*4882a593Smuzhiyun };
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun struct usba_udc {
324*4882a593Smuzhiyun /* Protect hw registers from concurrent modifications */
325*4882a593Smuzhiyun spinlock_t lock;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /* Mutex to prevent concurrent start or stop */
328*4882a593Smuzhiyun struct mutex vbus_mutex;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun void __iomem *regs;
331*4882a593Smuzhiyun void __iomem *fifo;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun struct usb_gadget gadget;
334*4882a593Smuzhiyun struct usb_gadget_driver *driver;
335*4882a593Smuzhiyun struct platform_device *pdev;
336*4882a593Smuzhiyun const struct usba_udc_errata *errata;
337*4882a593Smuzhiyun int irq;
338*4882a593Smuzhiyun struct gpio_desc *vbus_pin;
339*4882a593Smuzhiyun int num_ep;
340*4882a593Smuzhiyun struct usba_fifo_cfg *fifo_cfg;
341*4882a593Smuzhiyun struct clk *pclk;
342*4882a593Smuzhiyun struct clk *hclk;
343*4882a593Smuzhiyun struct usba_ep *usba_ep;
344*4882a593Smuzhiyun bool bias_pulse_needed;
345*4882a593Smuzhiyun bool clocked;
346*4882a593Smuzhiyun bool suspended;
347*4882a593Smuzhiyun bool ep_prealloc;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun u16 devstatus;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun u16 test_mode;
352*4882a593Smuzhiyun int vbus_prev;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun u32 int_enb_cache;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun #ifdef CONFIG_USB_GADGET_DEBUG_FS
357*4882a593Smuzhiyun struct dentry *debugfs_root;
358*4882a593Smuzhiyun #endif
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun struct regmap *pmc;
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun
to_usba_ep(struct usb_ep * ep)363*4882a593Smuzhiyun static inline struct usba_ep *to_usba_ep(struct usb_ep *ep)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun return container_of(ep, struct usba_ep, ep);
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun
to_usba_req(struct usb_request * req)368*4882a593Smuzhiyun static inline struct usba_request *to_usba_req(struct usb_request *req)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun return container_of(req, struct usba_request, req);
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
to_usba_udc(struct usb_gadget * gadget)373*4882a593Smuzhiyun static inline struct usba_udc *to_usba_udc(struct usb_gadget *gadget)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun return container_of(gadget, struct usba_udc, gadget);
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun #define ep_is_control(ep) ((ep)->index == 0)
379*4882a593Smuzhiyun #define ep_is_idle(ep) ((ep)->state == EP_STATE_IDLE)
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun #endif /* __LINUX_USB_GADGET_USBA_UDC_H */
382