1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun * dwc3-exynos.c - Samsung Exynos DWC3 Specific Glue layer
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6*4882a593Smuzhiyun * http://www.samsung.com
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Anton Tikhomirov <av.tikhomirov@samsung.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/clk.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_platform.h>
18*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define DWC3_EXYNOS_MAX_CLOCKS 4
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct dwc3_exynos_driverdata {
23*4882a593Smuzhiyun const char *clk_names[DWC3_EXYNOS_MAX_CLOCKS];
24*4882a593Smuzhiyun int num_clks;
25*4882a593Smuzhiyun int suspend_clk_idx;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun struct dwc3_exynos {
29*4882a593Smuzhiyun struct device *dev;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun const char **clk_names;
32*4882a593Smuzhiyun struct clk *clks[DWC3_EXYNOS_MAX_CLOCKS];
33*4882a593Smuzhiyun int num_clks;
34*4882a593Smuzhiyun int suspend_clk_idx;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct regulator *vdd33;
37*4882a593Smuzhiyun struct regulator *vdd10;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
dwc3_exynos_probe(struct platform_device * pdev)40*4882a593Smuzhiyun static int dwc3_exynos_probe(struct platform_device *pdev)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct dwc3_exynos *exynos;
43*4882a593Smuzhiyun struct device *dev = &pdev->dev;
44*4882a593Smuzhiyun struct device_node *node = dev->of_node;
45*4882a593Smuzhiyun const struct dwc3_exynos_driverdata *driver_data;
46*4882a593Smuzhiyun int i, ret;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun exynos = devm_kzalloc(dev, sizeof(*exynos), GFP_KERNEL);
49*4882a593Smuzhiyun if (!exynos)
50*4882a593Smuzhiyun return -ENOMEM;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun driver_data = of_device_get_match_data(dev);
53*4882a593Smuzhiyun exynos->dev = dev;
54*4882a593Smuzhiyun exynos->num_clks = driver_data->num_clks;
55*4882a593Smuzhiyun exynos->clk_names = (const char **)driver_data->clk_names;
56*4882a593Smuzhiyun exynos->suspend_clk_idx = driver_data->suspend_clk_idx;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun platform_set_drvdata(pdev, exynos);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun for (i = 0; i < exynos->num_clks; i++) {
61*4882a593Smuzhiyun exynos->clks[i] = devm_clk_get(dev, exynos->clk_names[i]);
62*4882a593Smuzhiyun if (IS_ERR(exynos->clks[i])) {
63*4882a593Smuzhiyun dev_err(dev, "failed to get clock: %s\n",
64*4882a593Smuzhiyun exynos->clk_names[i]);
65*4882a593Smuzhiyun return PTR_ERR(exynos->clks[i]);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun for (i = 0; i < exynos->num_clks; i++) {
70*4882a593Smuzhiyun ret = clk_prepare_enable(exynos->clks[i]);
71*4882a593Smuzhiyun if (ret) {
72*4882a593Smuzhiyun while (i-- > 0)
73*4882a593Smuzhiyun clk_disable_unprepare(exynos->clks[i]);
74*4882a593Smuzhiyun return ret;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun if (exynos->suspend_clk_idx >= 0)
79*4882a593Smuzhiyun clk_prepare_enable(exynos->clks[exynos->suspend_clk_idx]);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun exynos->vdd33 = devm_regulator_get(dev, "vdd33");
82*4882a593Smuzhiyun if (IS_ERR(exynos->vdd33)) {
83*4882a593Smuzhiyun ret = PTR_ERR(exynos->vdd33);
84*4882a593Smuzhiyun goto vdd33_err;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun ret = regulator_enable(exynos->vdd33);
87*4882a593Smuzhiyun if (ret) {
88*4882a593Smuzhiyun dev_err(dev, "Failed to enable VDD33 supply\n");
89*4882a593Smuzhiyun goto vdd33_err;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun exynos->vdd10 = devm_regulator_get(dev, "vdd10");
93*4882a593Smuzhiyun if (IS_ERR(exynos->vdd10)) {
94*4882a593Smuzhiyun ret = PTR_ERR(exynos->vdd10);
95*4882a593Smuzhiyun goto vdd10_err;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun ret = regulator_enable(exynos->vdd10);
98*4882a593Smuzhiyun if (ret) {
99*4882a593Smuzhiyun dev_err(dev, "Failed to enable VDD10 supply\n");
100*4882a593Smuzhiyun goto vdd10_err;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (node) {
104*4882a593Smuzhiyun ret = of_platform_populate(node, NULL, NULL, dev);
105*4882a593Smuzhiyun if (ret) {
106*4882a593Smuzhiyun dev_err(dev, "failed to add dwc3 core\n");
107*4882a593Smuzhiyun goto populate_err;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun } else {
110*4882a593Smuzhiyun dev_err(dev, "no device node, failed to add dwc3 core\n");
111*4882a593Smuzhiyun ret = -ENODEV;
112*4882a593Smuzhiyun goto populate_err;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return 0;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun populate_err:
118*4882a593Smuzhiyun regulator_disable(exynos->vdd10);
119*4882a593Smuzhiyun vdd10_err:
120*4882a593Smuzhiyun regulator_disable(exynos->vdd33);
121*4882a593Smuzhiyun vdd33_err:
122*4882a593Smuzhiyun for (i = exynos->num_clks - 1; i >= 0; i--)
123*4882a593Smuzhiyun clk_disable_unprepare(exynos->clks[i]);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun if (exynos->suspend_clk_idx >= 0)
126*4882a593Smuzhiyun clk_disable_unprepare(exynos->clks[exynos->suspend_clk_idx]);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return ret;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
dwc3_exynos_remove(struct platform_device * pdev)131*4882a593Smuzhiyun static int dwc3_exynos_remove(struct platform_device *pdev)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun struct dwc3_exynos *exynos = platform_get_drvdata(pdev);
134*4882a593Smuzhiyun int i;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun of_platform_depopulate(&pdev->dev);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun for (i = exynos->num_clks - 1; i >= 0; i--)
139*4882a593Smuzhiyun clk_disable_unprepare(exynos->clks[i]);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun if (exynos->suspend_clk_idx >= 0)
142*4882a593Smuzhiyun clk_disable_unprepare(exynos->clks[exynos->suspend_clk_idx]);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun regulator_disable(exynos->vdd33);
145*4882a593Smuzhiyun regulator_disable(exynos->vdd10);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun return 0;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun static const struct dwc3_exynos_driverdata exynos5250_drvdata = {
151*4882a593Smuzhiyun .clk_names = { "usbdrd30" },
152*4882a593Smuzhiyun .num_clks = 1,
153*4882a593Smuzhiyun .suspend_clk_idx = -1,
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun static const struct dwc3_exynos_driverdata exynos5433_drvdata = {
157*4882a593Smuzhiyun .clk_names = { "aclk", "susp_clk", "pipe_pclk", "phyclk" },
158*4882a593Smuzhiyun .num_clks = 4,
159*4882a593Smuzhiyun .suspend_clk_idx = 1,
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun static const struct dwc3_exynos_driverdata exynos7_drvdata = {
163*4882a593Smuzhiyun .clk_names = { "usbdrd30", "usbdrd30_susp_clk", "usbdrd30_axius_clk" },
164*4882a593Smuzhiyun .num_clks = 3,
165*4882a593Smuzhiyun .suspend_clk_idx = 1,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun static const struct of_device_id exynos_dwc3_match[] = {
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun .compatible = "samsung,exynos5250-dwusb3",
171*4882a593Smuzhiyun .data = &exynos5250_drvdata,
172*4882a593Smuzhiyun }, {
173*4882a593Smuzhiyun .compatible = "samsung,exynos5433-dwusb3",
174*4882a593Smuzhiyun .data = &exynos5433_drvdata,
175*4882a593Smuzhiyun }, {
176*4882a593Smuzhiyun .compatible = "samsung,exynos7-dwusb3",
177*4882a593Smuzhiyun .data = &exynos7_drvdata,
178*4882a593Smuzhiyun }, {
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, exynos_dwc3_match);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
dwc3_exynos_suspend(struct device * dev)184*4882a593Smuzhiyun static int dwc3_exynos_suspend(struct device *dev)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun struct dwc3_exynos *exynos = dev_get_drvdata(dev);
187*4882a593Smuzhiyun int i;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun for (i = exynos->num_clks - 1; i >= 0; i--)
190*4882a593Smuzhiyun clk_disable_unprepare(exynos->clks[i]);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun regulator_disable(exynos->vdd33);
193*4882a593Smuzhiyun regulator_disable(exynos->vdd10);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return 0;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
dwc3_exynos_resume(struct device * dev)198*4882a593Smuzhiyun static int dwc3_exynos_resume(struct device *dev)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun struct dwc3_exynos *exynos = dev_get_drvdata(dev);
201*4882a593Smuzhiyun int i, ret;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun ret = regulator_enable(exynos->vdd33);
204*4882a593Smuzhiyun if (ret) {
205*4882a593Smuzhiyun dev_err(dev, "Failed to enable VDD33 supply\n");
206*4882a593Smuzhiyun return ret;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun ret = regulator_enable(exynos->vdd10);
209*4882a593Smuzhiyun if (ret) {
210*4882a593Smuzhiyun dev_err(dev, "Failed to enable VDD10 supply\n");
211*4882a593Smuzhiyun return ret;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun for (i = 0; i < exynos->num_clks; i++) {
215*4882a593Smuzhiyun ret = clk_prepare_enable(exynos->clks[i]);
216*4882a593Smuzhiyun if (ret) {
217*4882a593Smuzhiyun while (i-- > 0)
218*4882a593Smuzhiyun clk_disable_unprepare(exynos->clks[i]);
219*4882a593Smuzhiyun return ret;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun return 0;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun static const struct dev_pm_ops dwc3_exynos_dev_pm_ops = {
227*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(dwc3_exynos_suspend, dwc3_exynos_resume)
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun #define DEV_PM_OPS (&dwc3_exynos_dev_pm_ops)
231*4882a593Smuzhiyun #else
232*4882a593Smuzhiyun #define DEV_PM_OPS NULL
233*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun static struct platform_driver dwc3_exynos_driver = {
236*4882a593Smuzhiyun .probe = dwc3_exynos_probe,
237*4882a593Smuzhiyun .remove = dwc3_exynos_remove,
238*4882a593Smuzhiyun .driver = {
239*4882a593Smuzhiyun .name = "exynos-dwc3",
240*4882a593Smuzhiyun .of_match_table = exynos_dwc3_match,
241*4882a593Smuzhiyun .pm = DEV_PM_OPS,
242*4882a593Smuzhiyun },
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun module_platform_driver(dwc3_exynos_driver);
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun MODULE_AUTHOR("Anton Tikhomirov <av.tikhomirov@samsung.com>");
248*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
249*4882a593Smuzhiyun MODULE_DESCRIPTION("DesignWare USB3 Exynos Glue Layer");
250