1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
29
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
34
35 #include "core.h"
36 #include "gadget.h"
37 #include "io.h"
38
39 #include "debug.h"
40
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
42
43 /**
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
46 */
dwc3_get_dr_mode(struct dwc3 * dwc)47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
48 {
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82 /*
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
86 */
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
92 }
93
94 if (mode != dwc->dr_mode) {
95 dev_warn(dev,
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
98
99 dwc->dr_mode = mode;
100 }
101
102 return 0;
103 }
104
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
106 {
107 u32 reg;
108
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
113
114 dwc->current_dr_role = mode;
115 }
116
__dwc3_set_mode(struct work_struct * work)117 static void __dwc3_set_mode(struct work_struct *work)
118 {
119 struct dwc3 *dwc = work_to_dwc(work);
120 unsigned long flags;
121 int ret;
122 int retries = 1000;
123 u32 reg;
124
125 mutex_lock(&dwc->mutex);
126
127 pm_runtime_get_sync(dwc->dev);
128
129 #if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_NO_GKI)
130 if (dwc->desired_role_sw_mode == USB_DR_MODE_PERIPHERAL &&
131 dwc->desired_role_sw_mode != dwc->current_role_sw_mode)
132 pm_runtime_get(dwc->dev);
133 else if ((dwc->desired_role_sw_mode == USB_DR_MODE_UNKNOWN ||
134 dwc->desired_role_sw_mode == USB_DR_MODE_HOST) &&
135 dwc->current_role_sw_mode == USB_DR_MODE_PERIPHERAL)
136 pm_runtime_put(dwc->dev);
137
138 dwc->current_role_sw_mode = dwc->desired_role_sw_mode;
139 #endif
140
141 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
142 dwc3_otg_update(dwc, 0);
143
144 if (!dwc->desired_dr_role)
145 goto out;
146
147 if (dwc->desired_dr_role == dwc->current_dr_role)
148 goto out;
149
150 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
151 goto out;
152
153 switch (dwc->current_dr_role) {
154 case DWC3_GCTL_PRTCAP_HOST:
155 dwc3_host_exit(dwc);
156 break;
157 case DWC3_GCTL_PRTCAP_DEVICE:
158 dwc3_gadget_exit(dwc);
159 dwc3_event_buffers_cleanup(dwc);
160 break;
161 case DWC3_GCTL_PRTCAP_OTG:
162 dwc3_otg_exit(dwc);
163 spin_lock_irqsave(&dwc->lock, flags);
164 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
165 spin_unlock_irqrestore(&dwc->lock, flags);
166 dwc3_otg_update(dwc, 1);
167 break;
168 default:
169 break;
170 }
171
172 /*
173 * When current_dr_role is not set, there's no role switching.
174 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
175 */
176 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
177 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
178 dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
179 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
180 reg |= DWC3_GCTL_CORESOFTRESET;
181 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
182
183 /*
184 * Wait for internal clocks to synchronized. DWC_usb31 and
185 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
186 * keep it consistent across different IPs, let's wait up to
187 * 100ms before clearing GCTL.CORESOFTRESET.
188 */
189 msleep(100);
190
191 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
192 reg &= ~DWC3_GCTL_CORESOFTRESET;
193 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
194 }
195
196 spin_lock_irqsave(&dwc->lock, flags);
197
198 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
199
200 spin_unlock_irqrestore(&dwc->lock, flags);
201
202 switch (dwc->desired_dr_role) {
203 case DWC3_GCTL_PRTCAP_HOST:
204 ret = dwc3_host_init(dwc);
205 if (ret) {
206 dev_err(dwc->dev, "failed to initialize host\n");
207 } else {
208 if (dwc->usb2_phy)
209 otg_set_vbus(dwc->usb2_phy->otg, true);
210 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
211 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
212 if (dwc->dis_split_quirk) {
213 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
214 reg |= DWC3_GUCTL3_SPLITDISABLE;
215 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
216 }
217 }
218 break;
219 case DWC3_GCTL_PRTCAP_DEVICE:
220 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
221 reg |= DWC3_DCTL_CSFTRST;
222 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
223
224 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
225 retries = 10;
226
227 do {
228 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
229 if (!(reg & DWC3_DCTL_CSFTRST))
230 goto done;
231
232 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
233 msleep(20);
234 else
235 udelay(1);
236 } while (--retries);
237 done:
238 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
239 msleep(50);
240
241 dwc3_event_buffers_setup(dwc);
242
243 if (dwc->usb2_phy)
244 otg_set_vbus(dwc->usb2_phy->otg, false);
245 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
246 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
247
248 ret = dwc3_gadget_init(dwc);
249 if (ret)
250 dev_err(dwc->dev, "failed to initialize peripheral\n");
251 break;
252 case DWC3_GCTL_PRTCAP_OTG:
253 dwc3_otg_init(dwc);
254 dwc3_otg_update(dwc, 0);
255 break;
256 default:
257 break;
258 }
259
260 out:
261 pm_runtime_mark_last_busy(dwc->dev);
262 pm_runtime_put_autosuspend(dwc->dev);
263 mutex_unlock(&dwc->mutex);
264 }
265
dwc3_set_mode(struct dwc3 * dwc,u32 mode)266 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
267 {
268 unsigned long flags;
269
270 if (dwc->dr_mode != USB_DR_MODE_OTG)
271 return;
272
273 spin_lock_irqsave(&dwc->lock, flags);
274 dwc->desired_dr_role = mode;
275 spin_unlock_irqrestore(&dwc->lock, flags);
276
277 queue_work(system_freezable_wq, &dwc->drd_work);
278 }
279
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)280 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
281 {
282 struct dwc3 *dwc = dep->dwc;
283 u32 reg;
284
285 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
286 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
287 DWC3_GDBGFIFOSPACE_TYPE(type));
288
289 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
290
291 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
292 }
293
294 /**
295 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
296 * @dwc: pointer to our context structure
297 */
dwc3_core_soft_reset(struct dwc3 * dwc)298 int dwc3_core_soft_reset(struct dwc3 *dwc)
299 {
300 u32 reg;
301 int retries = 1000;
302
303 /*
304 * We're resetting only the device side because, if we're in host mode,
305 * XHCI driver will reset the host block. If dwc3 was configured for
306 * host-only mode, then we can return early.
307 */
308 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
309 return 0;
310
311 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
312 reg |= DWC3_DCTL_CSFTRST;
313 reg &= ~DWC3_DCTL_RUN_STOP;
314 dwc3_gadget_dctl_write_safe(dwc, reg);
315
316 /*
317 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
318 * is cleared only after all the clocks are synchronized. This can
319 * take a little more than 50ms. Set the polling rate at 20ms
320 * for 10 times instead.
321 */
322 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
323 retries = 10;
324
325 do {
326 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
327 if (!(reg & DWC3_DCTL_CSFTRST))
328 goto done;
329
330 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
331 msleep(20);
332 else
333 udelay(1);
334 } while (--retries);
335
336 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
337 return -ETIMEDOUT;
338
339 done:
340 /*
341 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
342 * is cleared, we must wait at least 50ms before accessing the PHY
343 * domain (synchronization delay).
344 */
345 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
346 msleep(50);
347
348 return 0;
349 }
350
351 /*
352 * dwc3_frame_length_adjustment - Adjusts frame length if required
353 * @dwc3: Pointer to our controller context structure
354 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)355 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
356 {
357 u32 reg;
358 u32 dft;
359
360 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
361 return;
362
363 if (dwc->fladj == 0)
364 return;
365
366 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
367 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
368 if (dft != dwc->fladj) {
369 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
370 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
371 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
372 }
373 }
374
375 /**
376 * dwc3_free_one_event_buffer - Frees one event buffer
377 * @dwc: Pointer to our controller context structure
378 * @evt: Pointer to event buffer to be freed
379 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)380 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
381 struct dwc3_event_buffer *evt)
382 {
383 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
384 }
385
386 /**
387 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
388 * @dwc: Pointer to our controller context structure
389 * @length: size of the event buffer
390 *
391 * Returns a pointer to the allocated event buffer structure on success
392 * otherwise ERR_PTR(errno).
393 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned int length)394 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
395 unsigned int length)
396 {
397 struct dwc3_event_buffer *evt;
398
399 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
400 if (!evt)
401 return ERR_PTR(-ENOMEM);
402
403 evt->dwc = dwc;
404 evt->length = length;
405 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
406 if (!evt->cache)
407 return ERR_PTR(-ENOMEM);
408
409 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
410 &evt->dma, GFP_KERNEL);
411 if (!evt->buf)
412 return ERR_PTR(-ENOMEM);
413
414 return evt;
415 }
416
417 /**
418 * dwc3_free_event_buffers - frees all allocated event buffers
419 * @dwc: Pointer to our controller context structure
420 */
dwc3_free_event_buffers(struct dwc3 * dwc)421 static void dwc3_free_event_buffers(struct dwc3 *dwc)
422 {
423 struct dwc3_event_buffer *evt;
424
425 evt = dwc->ev_buf;
426 if (evt)
427 dwc3_free_one_event_buffer(dwc, evt);
428 }
429
430 /**
431 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
432 * @dwc: pointer to our controller context structure
433 * @length: size of event buffer
434 *
435 * Returns 0 on success otherwise negative errno. In the error case, dwc
436 * may contain some buffers allocated but not all which were requested.
437 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned int length)438 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
439 {
440 struct dwc3_event_buffer *evt;
441
442 evt = dwc3_alloc_one_event_buffer(dwc, length);
443 if (IS_ERR(evt)) {
444 dev_err(dwc->dev, "can't allocate event buffer\n");
445 return PTR_ERR(evt);
446 }
447 dwc->ev_buf = evt;
448
449 return 0;
450 }
451
452 /**
453 * dwc3_event_buffers_setup - setup our allocated event buffers
454 * @dwc: pointer to our controller context structure
455 *
456 * Returns 0 on success otherwise negative errno.
457 */
dwc3_event_buffers_setup(struct dwc3 * dwc)458 int dwc3_event_buffers_setup(struct dwc3 *dwc)
459 {
460 struct dwc3_event_buffer *evt;
461
462 evt = dwc->ev_buf;
463 evt->lpos = 0;
464 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
465 lower_32_bits(evt->dma));
466 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
467 upper_32_bits(evt->dma));
468 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
469 DWC3_GEVNTSIZ_SIZE(evt->length));
470 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
471
472 return 0;
473 }
474
dwc3_event_buffers_cleanup(struct dwc3 * dwc)475 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
476 {
477 struct dwc3_event_buffer *evt;
478
479 evt = dwc->ev_buf;
480
481 evt->lpos = 0;
482
483 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
484 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
485 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
486 | DWC3_GEVNTSIZ_SIZE(0));
487 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
488 }
489
dwc3_alloc_scratch_buffers(struct dwc3 * dwc)490 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
491 {
492 if (!dwc->has_hibernation)
493 return 0;
494
495 if (!dwc->nr_scratch)
496 return 0;
497
498 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
499 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
500 if (!dwc->scratchbuf)
501 return -ENOMEM;
502
503 return 0;
504 }
505
dwc3_setup_scratch_buffers(struct dwc3 * dwc)506 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
507 {
508 dma_addr_t scratch_addr;
509 u32 param;
510 int ret;
511
512 if (!dwc->has_hibernation)
513 return 0;
514
515 if (!dwc->nr_scratch)
516 return 0;
517
518 /* should never fall here */
519 if (!WARN_ON(dwc->scratchbuf))
520 return 0;
521
522 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
523 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
524 DMA_BIDIRECTIONAL);
525 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
526 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
527 ret = -EFAULT;
528 goto err0;
529 }
530
531 dwc->scratch_addr = scratch_addr;
532
533 param = lower_32_bits(scratch_addr);
534
535 ret = dwc3_send_gadget_generic_command(dwc,
536 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
537 if (ret < 0)
538 goto err1;
539
540 param = upper_32_bits(scratch_addr);
541
542 ret = dwc3_send_gadget_generic_command(dwc,
543 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
544 if (ret < 0)
545 goto err1;
546
547 return 0;
548
549 err1:
550 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
551 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
552
553 err0:
554 return ret;
555 }
556
dwc3_free_scratch_buffers(struct dwc3 * dwc)557 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
558 {
559 if (!dwc->has_hibernation)
560 return;
561
562 if (!dwc->nr_scratch)
563 return;
564
565 /* should never fall here */
566 if (!WARN_ON(dwc->scratchbuf))
567 return;
568
569 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
570 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
571 kfree(dwc->scratchbuf);
572 }
573
dwc3_core_num_eps(struct dwc3 * dwc)574 static void dwc3_core_num_eps(struct dwc3 *dwc)
575 {
576 struct dwc3_hwparams *parms = &dwc->hwparams;
577
578 dwc->num_eps = DWC3_NUM_EPS(parms);
579 }
580
dwc3_cache_hwparams(struct dwc3 * dwc)581 static void dwc3_cache_hwparams(struct dwc3 *dwc)
582 {
583 struct dwc3_hwparams *parms = &dwc->hwparams;
584
585 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
586 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
587 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
588 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
589 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
590 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
591 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
592 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
593 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
594
595 if (DWC3_IP_IS(DWC32))
596 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
597 }
598
dwc3_core_ulpi_init(struct dwc3 * dwc)599 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
600 {
601 int intf;
602 int ret = 0;
603
604 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
605
606 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
607 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
608 dwc->hsphy_interface &&
609 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
610 ret = dwc3_ulpi_init(dwc);
611
612 return ret;
613 }
614
615 /**
616 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
617 * @dwc: Pointer to our controller context structure
618 *
619 * Returns 0 on success. The USB PHY interfaces are configured but not
620 * initialized. The PHY interfaces and the PHYs get initialized together with
621 * the core in dwc3_core_init.
622 */
dwc3_phy_setup(struct dwc3 * dwc)623 static int dwc3_phy_setup(struct dwc3 *dwc)
624 {
625 unsigned int hw_mode;
626 u32 reg;
627
628 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
629
630 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
631
632 /*
633 * Make sure UX_EXIT_PX is cleared as that causes issues with some
634 * PHYs. Also, this bit is not supposed to be used in normal operation.
635 */
636 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
637
638 /*
639 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
640 * to '0' during coreConsultant configuration. So default value
641 * will be '0' when the core is reset. Application needs to set it
642 * to '1' after the core initialization is completed.
643 */
644 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
645 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
646
647 /*
648 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
649 * power-on reset, and it can be set after core initialization, which is
650 * after device soft-reset during initialization.
651 */
652 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
653 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
654
655 if (dwc->u2ss_inp3_quirk)
656 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
657
658 if (dwc->dis_rxdet_inp3_quirk)
659 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
660
661 if (dwc->req_p1p2p3_quirk)
662 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
663
664 if (dwc->del_p1p2p3_quirk)
665 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
666
667 if (dwc->del_phy_power_chg_quirk)
668 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
669
670 if (dwc->lfps_filter_quirk)
671 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
672
673 if (dwc->rx_detect_poll_quirk)
674 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
675
676 if (dwc->tx_de_emphasis_quirk)
677 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
678
679 if (dwc->dis_u3_susphy_quirk)
680 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
681
682 if (dwc->dis_del_phy_power_chg_quirk)
683 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
684
685 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
686
687 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
688
689 /* Select the HS PHY interface */
690 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
691 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
692 if (dwc->hsphy_interface &&
693 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
694 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
695 break;
696 } else if (dwc->hsphy_interface &&
697 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
698 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
699 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
700 } else {
701 /* Relying on default value. */
702 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
703 break;
704 }
705 fallthrough;
706 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
707 default:
708 break;
709 }
710
711 switch (dwc->hsphy_mode) {
712 case USBPHY_INTERFACE_MODE_UTMI:
713 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
714 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
715 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
716 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
717 break;
718 case USBPHY_INTERFACE_MODE_UTMIW:
719 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
720 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
721 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
722 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
723 break;
724 default:
725 break;
726 }
727
728 /*
729 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
730 * '0' during coreConsultant configuration. So default value will
731 * be '0' when the core is reset. Application needs to set it to
732 * '1' after the core initialization is completed.
733 */
734 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
735 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
736
737 /*
738 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
739 * power-on reset, and it can be set after core initialization, which is
740 * after device soft-reset during initialization.
741 */
742 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
743 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
744
745 if (dwc->dis_u2_susphy_quirk)
746 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
747
748 if (dwc->dis_enblslpm_quirk)
749 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
750 else
751 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
752
753 if (dwc->dis_u2_freeclk_exists_quirk)
754 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
755
756 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
757
758 return 0;
759 }
760
dwc3_core_exit(struct dwc3 * dwc)761 static void dwc3_core_exit(struct dwc3 *dwc)
762 {
763 dwc3_event_buffers_cleanup(dwc);
764
765 usb_phy_set_suspend(dwc->usb2_phy, 1);
766 usb_phy_set_suspend(dwc->usb3_phy, 1);
767 phy_power_off(dwc->usb2_generic_phy);
768 phy_power_off(dwc->usb3_generic_phy);
769
770 usb_phy_shutdown(dwc->usb2_phy);
771 usb_phy_shutdown(dwc->usb3_phy);
772 phy_exit(dwc->usb2_generic_phy);
773 phy_exit(dwc->usb3_generic_phy);
774
775 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
776 reset_control_assert(dwc->reset);
777 }
778
dwc3_core_is_valid(struct dwc3 * dwc)779 static bool dwc3_core_is_valid(struct dwc3 *dwc)
780 {
781 u32 reg;
782
783 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
784 dwc->ip = DWC3_GSNPS_ID(reg);
785
786 /* This should read as U3 followed by revision number */
787 if (DWC3_IP_IS(DWC3)) {
788 dwc->revision = reg;
789 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
790 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
791 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
792 } else {
793 return false;
794 }
795
796 return true;
797 }
798
dwc3_core_setup_global_control(struct dwc3 * dwc)799 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
800 {
801 u32 hwparams4 = dwc->hwparams.hwparams4;
802 u32 reg;
803
804 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
805 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
806
807 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
808 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
809 /**
810 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
811 * issue which would cause xHCI compliance tests to fail.
812 *
813 * Because of that we cannot enable clock gating on such
814 * configurations.
815 *
816 * Refers to:
817 *
818 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
819 * SOF/ITP Mode Used
820 */
821 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
822 dwc->dr_mode == USB_DR_MODE_OTG) &&
823 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
824 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
825 else
826 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
827 break;
828 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
829 /* enable hibernation here */
830 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
831
832 /*
833 * REVISIT Enabling this bit so that host-mode hibernation
834 * will work. Device-mode hibernation is not yet implemented.
835 */
836 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
837 break;
838 default:
839 /* nothing */
840 break;
841 }
842
843 /* check if current dwc3 is on simulation board */
844 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
845 dev_info(dwc->dev, "Running with FPGA optimizations\n");
846 dwc->is_fpga = true;
847 }
848
849 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
850 "disable_scramble cannot be used on non-FPGA builds\n");
851
852 if (dwc->disable_scramble_quirk && dwc->is_fpga)
853 reg |= DWC3_GCTL_DISSCRAMBLE;
854 else
855 reg &= ~DWC3_GCTL_DISSCRAMBLE;
856
857 if (dwc->u2exit_lfps_quirk)
858 reg |= DWC3_GCTL_U2EXIT_LFPS;
859
860 /*
861 * WORKAROUND: DWC3 revisions <1.90a have a bug
862 * where the device can fail to connect at SuperSpeed
863 * and falls back to high-speed mode which causes
864 * the device to enter a Connect/Disconnect loop
865 */
866 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
867 reg |= DWC3_GCTL_U2RSTECN;
868
869 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
870 }
871
872 static int dwc3_core_get_phy(struct dwc3 *dwc);
873 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
874
875 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)876 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
877 {
878 struct device *dev = dwc->dev;
879 /* incrx_mode : for INCR burst type. */
880 bool incrx_mode;
881 /* incrx_size : for size of INCRX burst. */
882 u32 incrx_size;
883 u32 *vals;
884 u32 cfg;
885 int ntype;
886 int ret;
887 int i;
888
889 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
890
891 /*
892 * Handle property "snps,incr-burst-type-adjustment".
893 * Get the number of value from this property:
894 * result <= 0, means this property is not supported.
895 * result = 1, means INCRx burst mode supported.
896 * result > 1, means undefined length burst mode supported.
897 */
898 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
899 if (ntype <= 0)
900 return;
901
902 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
903 if (!vals) {
904 dev_err(dev, "Error to get memory\n");
905 return;
906 }
907
908 /* Get INCR burst type, and parse it */
909 ret = device_property_read_u32_array(dev,
910 "snps,incr-burst-type-adjustment", vals, ntype);
911 if (ret) {
912 kfree(vals);
913 dev_err(dev, "Error to get property\n");
914 return;
915 }
916
917 incrx_size = *vals;
918
919 if (ntype > 1) {
920 /* INCRX (undefined length) burst mode */
921 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
922 for (i = 1; i < ntype; i++) {
923 if (vals[i] > incrx_size)
924 incrx_size = vals[i];
925 }
926 } else {
927 /* INCRX burst mode */
928 incrx_mode = INCRX_BURST_MODE;
929 }
930
931 kfree(vals);
932
933 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
934 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
935 if (incrx_mode)
936 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
937 switch (incrx_size) {
938 case 256:
939 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
940 break;
941 case 128:
942 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
943 break;
944 case 64:
945 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
946 break;
947 case 32:
948 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
949 break;
950 case 16:
951 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
952 break;
953 case 8:
954 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
955 break;
956 case 4:
957 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
958 break;
959 case 1:
960 break;
961 default:
962 dev_err(dev, "Invalid property\n");
963 break;
964 }
965
966 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
967 }
968
969 /**
970 * dwc3_core_init - Low-level initialization of DWC3 Core
971 * @dwc: Pointer to our controller context structure
972 *
973 * Returns 0 on success otherwise negative errno.
974 */
dwc3_core_init(struct dwc3 * dwc)975 static int dwc3_core_init(struct dwc3 *dwc)
976 {
977 unsigned int hw_mode;
978 u32 reg;
979 int ret;
980
981 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
982
983 /*
984 * Write Linux Version Code to our GUID register so it's easy to figure
985 * out which kernel version a bug was found.
986 */
987 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
988
989 ret = dwc3_phy_setup(dwc);
990 if (ret)
991 goto err0;
992
993 if (!dwc->ulpi_ready) {
994 ret = dwc3_core_ulpi_init(dwc);
995 if (ret)
996 goto err0;
997 dwc->ulpi_ready = true;
998 }
999
1000 if (!dwc->phys_ready) {
1001 ret = dwc3_core_get_phy(dwc);
1002 if (ret)
1003 goto err0a;
1004 dwc->phys_ready = true;
1005 }
1006
1007 usb_phy_init(dwc->usb2_phy);
1008 usb_phy_init(dwc->usb3_phy);
1009 ret = phy_init(dwc->usb2_generic_phy);
1010 if (ret < 0)
1011 goto err0a;
1012
1013 ret = phy_init(dwc->usb3_generic_phy);
1014 if (ret < 0) {
1015 phy_exit(dwc->usb2_generic_phy);
1016 goto err0a;
1017 }
1018
1019 ret = dwc3_core_soft_reset(dwc);
1020 if (ret)
1021 goto err1;
1022
1023 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1024 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1025 if (!dwc->dis_u3_susphy_quirk) {
1026 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1027 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1028 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1029 }
1030
1031 if (!dwc->dis_u2_susphy_quirk) {
1032 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1033 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1034 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1035 }
1036 }
1037
1038 dwc3_core_setup_global_control(dwc);
1039 dwc3_core_num_eps(dwc);
1040
1041 ret = dwc3_setup_scratch_buffers(dwc);
1042 if (ret)
1043 goto err1;
1044
1045 /* Adjust Frame Length */
1046 dwc3_frame_length_adjustment(dwc);
1047
1048 dwc3_set_incr_burst_type(dwc);
1049
1050 usb_phy_set_suspend(dwc->usb2_phy, 0);
1051 usb_phy_set_suspend(dwc->usb3_phy, 0);
1052 ret = phy_power_on(dwc->usb2_generic_phy);
1053 if (ret < 0)
1054 goto err2;
1055
1056 ret = phy_power_on(dwc->usb3_generic_phy);
1057 if (ret < 0)
1058 goto err3;
1059
1060 ret = dwc3_event_buffers_setup(dwc);
1061 if (ret) {
1062 dev_err(dwc->dev, "failed to setup event buffers\n");
1063 goto err4;
1064 }
1065
1066 /*
1067 * ENDXFER polling is available on version 3.10a and later of
1068 * the DWC_usb3 controller. It is NOT available in the
1069 * DWC_usb31 controller.
1070 */
1071 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1072 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1073 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1074 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1075 }
1076
1077 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1078 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1079
1080 /*
1081 * Enable hardware control of sending remote wakeup
1082 * in HS when the device is in the L1 state.
1083 */
1084 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1085 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1086
1087 /*
1088 * Decouple USB 2.0 L1 & L2 events which will allow for
1089 * gadget driver to only receive U3/L2 suspend & wakeup
1090 * events and prevent the more frequent L1 LPM transitions
1091 * from interrupting the driver.
1092 */
1093 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1094 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1095
1096 if (dwc->dis_tx_ipgap_linecheck_quirk)
1097 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1098
1099 if (dwc->parkmode_disable_ss_quirk)
1100 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1101
1102 if (dwc->maximum_speed == USB_SPEED_HIGH ||
1103 dwc->maximum_speed == USB_SPEED_FULL)
1104 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1105
1106 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1107 }
1108
1109 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1110 dwc->dr_mode == USB_DR_MODE_OTG) {
1111 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1112
1113 /*
1114 * Enable Auto retry Feature to make the controller operating in
1115 * Host mode on seeing transaction errors(CRC errors or internal
1116 * overrun scenerios) on IN transfers to reply to the device
1117 * with a non-terminating retry ACK (i.e, an ACK transcation
1118 * packet with Retry=1 & Nump != 0)
1119 */
1120 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1121
1122 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1123 }
1124
1125 /*
1126 * Must config both number of packets and max burst settings to enable
1127 * RX and/or TX threshold.
1128 */
1129 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1130 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1131 u8 rx_maxburst = dwc->rx_max_burst_prd;
1132 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1133 u8 tx_maxburst = dwc->tx_max_burst_prd;
1134
1135 if (rx_thr_num && rx_maxburst) {
1136 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1137 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1138
1139 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1140 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1141
1142 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1143 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1144
1145 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1146 }
1147
1148 if (tx_thr_num && tx_maxburst) {
1149 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1150 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1151
1152 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1153 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1154
1155 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1156 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1157
1158 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1159 }
1160 }
1161
1162 return 0;
1163
1164 err4:
1165 phy_power_off(dwc->usb3_generic_phy);
1166
1167 err3:
1168 phy_power_off(dwc->usb2_generic_phy);
1169
1170 err2:
1171 usb_phy_set_suspend(dwc->usb2_phy, 1);
1172 usb_phy_set_suspend(dwc->usb3_phy, 1);
1173
1174 err1:
1175 usb_phy_shutdown(dwc->usb2_phy);
1176 usb_phy_shutdown(dwc->usb3_phy);
1177 phy_exit(dwc->usb2_generic_phy);
1178 phy_exit(dwc->usb3_generic_phy);
1179
1180 err0a:
1181 dwc3_ulpi_exit(dwc);
1182
1183 err0:
1184 return ret;
1185 }
1186
dwc3_core_get_phy(struct dwc3 * dwc)1187 static int dwc3_core_get_phy(struct dwc3 *dwc)
1188 {
1189 struct device *dev = dwc->dev;
1190 struct device_node *node = dev->of_node;
1191 int ret;
1192
1193 if (node) {
1194 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1195 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1196 } else {
1197 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1198 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1199 }
1200
1201 if (IS_ERR(dwc->usb2_phy)) {
1202 ret = PTR_ERR(dwc->usb2_phy);
1203 if (ret == -ENXIO || ret == -ENODEV)
1204 dwc->usb2_phy = NULL;
1205 else
1206 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1207 }
1208
1209 if (IS_ERR(dwc->usb3_phy)) {
1210 ret = PTR_ERR(dwc->usb3_phy);
1211 if (ret == -ENXIO || ret == -ENODEV)
1212 dwc->usb3_phy = NULL;
1213 else
1214 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1215 }
1216
1217 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1218 if (IS_ERR(dwc->usb2_generic_phy)) {
1219 ret = PTR_ERR(dwc->usb2_generic_phy);
1220 if (ret == -ENOSYS || ret == -ENODEV)
1221 dwc->usb2_generic_phy = NULL;
1222 else
1223 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1224 }
1225
1226 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1227 if (IS_ERR(dwc->usb3_generic_phy)) {
1228 ret = PTR_ERR(dwc->usb3_generic_phy);
1229 if (ret == -ENOSYS || ret == -ENODEV)
1230 dwc->usb3_generic_phy = NULL;
1231 else
1232 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1233 }
1234
1235 return 0;
1236 }
1237
dwc3_core_init_mode(struct dwc3 * dwc)1238 static int dwc3_core_init_mode(struct dwc3 *dwc)
1239 {
1240 struct device *dev = dwc->dev;
1241 int ret;
1242
1243 switch (dwc->dr_mode) {
1244 case USB_DR_MODE_PERIPHERAL:
1245 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1246
1247 if (dwc->usb2_phy)
1248 otg_set_vbus(dwc->usb2_phy->otg, false);
1249 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1250 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1251
1252 ret = dwc3_gadget_init(dwc);
1253 if (ret)
1254 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1255 break;
1256 case USB_DR_MODE_HOST:
1257 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1258
1259 if (dwc->usb2_phy)
1260 otg_set_vbus(dwc->usb2_phy->otg, true);
1261 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1262 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1263
1264 ret = dwc3_host_init(dwc);
1265 if (ret)
1266 return dev_err_probe(dev, ret, "failed to initialize host\n");
1267 break;
1268 case USB_DR_MODE_OTG:
1269 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1270 ret = dwc3_drd_init(dwc);
1271 if (ret)
1272 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1273 break;
1274 default:
1275 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1276 return -EINVAL;
1277 }
1278
1279 return 0;
1280 }
1281
dwc3_core_exit_mode(struct dwc3 * dwc)1282 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1283 {
1284 switch (dwc->dr_mode) {
1285 case USB_DR_MODE_PERIPHERAL:
1286 dwc3_gadget_exit(dwc);
1287 break;
1288 case USB_DR_MODE_HOST:
1289 dwc3_host_exit(dwc);
1290 break;
1291 case USB_DR_MODE_OTG:
1292 dwc3_drd_exit(dwc);
1293 break;
1294 default:
1295 /* do nothing */
1296 break;
1297 }
1298
1299 /* de-assert DRVVBUS for HOST and OTG mode */
1300 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1301 }
1302
dwc3_get_properties(struct dwc3 * dwc)1303 static void dwc3_get_properties(struct dwc3 *dwc)
1304 {
1305 struct device *dev = dwc->dev;
1306 u8 lpm_nyet_threshold;
1307 u8 tx_de_emphasis;
1308 u8 hird_threshold;
1309 u8 rx_thr_num_pkt_prd = 0;
1310 u8 rx_max_burst_prd = 0;
1311 u8 tx_thr_num_pkt_prd = 0;
1312 u8 tx_max_burst_prd = 0;
1313 u8 tx_fifo_resize_max_num;
1314 const char *usb_psy_name;
1315 int ret;
1316
1317 /* default to highest possible threshold */
1318 lpm_nyet_threshold = 0xf;
1319
1320 /* default to -3.5dB de-emphasis */
1321 tx_de_emphasis = 1;
1322
1323 /*
1324 * default to assert utmi_sleep_n and use maximum allowed HIRD
1325 * threshold value of 0b1100
1326 */
1327 hird_threshold = 12;
1328
1329 /*
1330 * default to a TXFIFO size large enough to fit 6 max packets. This
1331 * allows for systems with larger bus latencies to have some headroom
1332 * for endpoints that have a large bMaxBurst value.
1333 */
1334 tx_fifo_resize_max_num = 6;
1335
1336 dwc->maximum_speed = usb_get_maximum_speed(dev);
1337 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1338 dwc->dr_mode = usb_get_dr_mode(dev);
1339 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1340
1341 dwc->sysdev_is_parent = device_property_read_bool(dev,
1342 "linux,sysdev_is_parent");
1343 if (dwc->sysdev_is_parent)
1344 dwc->sysdev = dwc->dev->parent;
1345 else
1346 dwc->sysdev = dwc->dev;
1347
1348 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1349 if (ret >= 0) {
1350 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1351 if (!dwc->usb_psy)
1352 dev_err(dev, "couldn't get usb power supply\n");
1353 }
1354
1355 dwc->has_lpm_erratum = device_property_read_bool(dev,
1356 "snps,has-lpm-erratum");
1357 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1358 &lpm_nyet_threshold);
1359 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1360 "snps,is-utmi-l1-suspend");
1361 device_property_read_u8(dev, "snps,hird-threshold",
1362 &hird_threshold);
1363 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1364 "snps,dis-start-transfer-quirk");
1365 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1366 "snps,usb3_lpm_capable");
1367 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1368 "snps,usb2-lpm-disable");
1369 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1370 "snps,usb2-gadget-lpm-disable");
1371 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1372 &rx_thr_num_pkt_prd);
1373 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1374 &rx_max_burst_prd);
1375 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1376 &tx_thr_num_pkt_prd);
1377 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1378 &tx_max_burst_prd);
1379 dwc->do_fifo_resize = device_property_read_bool(dev,
1380 "tx-fifo-resize");
1381 if (dwc->do_fifo_resize)
1382 device_property_read_u8(dev, "tx-fifo-max-num",
1383 &tx_fifo_resize_max_num);
1384
1385 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1386 "snps,disable_scramble_quirk");
1387 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1388 "snps,u2exit_lfps_quirk");
1389 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1390 "snps,u2ss_inp3_quirk");
1391 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1392 "snps,req_p1p2p3_quirk");
1393 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1394 "snps,del_p1p2p3_quirk");
1395 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1396 "snps,del_phy_power_chg_quirk");
1397 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1398 "snps,lfps_filter_quirk");
1399 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1400 "snps,rx_detect_poll_quirk");
1401 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1402 "snps,dis_u3_susphy_quirk");
1403 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1404 "snps,dis_u2_susphy_quirk");
1405 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1406 "snps,dis_enblslpm_quirk");
1407 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1408 "snps,dis-u1-entry-quirk");
1409 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1410 "snps,dis-u2-entry-quirk");
1411 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1412 "snps,dis_rxdet_inp3_quirk");
1413 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1414 "snps,dis-u2-freeclk-exists-quirk");
1415 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1416 "snps,dis-del-phy-power-chg-quirk");
1417 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1418 "snps,dis-tx-ipgap-linecheck-quirk");
1419 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1420 "snps,parkmode-disable-ss-quirk");
1421
1422 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1423 "snps,tx_de_emphasis_quirk");
1424 device_property_read_u8(dev, "snps,tx_de_emphasis",
1425 &tx_de_emphasis);
1426 device_property_read_string(dev, "snps,hsphy_interface",
1427 &dwc->hsphy_interface);
1428 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1429 &dwc->fladj);
1430
1431 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1432 "snps,dis_metastability_quirk");
1433
1434 dwc->dis_split_quirk = device_property_read_bool(dev,
1435 "snps,dis-split-quirk");
1436
1437 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1438 dwc->tx_de_emphasis = tx_de_emphasis;
1439
1440 dwc->hird_threshold = hird_threshold;
1441
1442 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1443 dwc->rx_max_burst_prd = rx_max_burst_prd;
1444
1445 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1446 dwc->tx_max_burst_prd = tx_max_burst_prd;
1447
1448 dwc->imod_interval = 0;
1449
1450 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1451 }
1452
1453 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1454 bool dwc3_has_imod(struct dwc3 *dwc)
1455 {
1456 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1457 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1458 DWC3_IP_IS(DWC32);
1459 }
1460
dwc3_check_params(struct dwc3 * dwc)1461 static void dwc3_check_params(struct dwc3 *dwc)
1462 {
1463 struct device *dev = dwc->dev;
1464 unsigned int hwparam_gen =
1465 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1466
1467 /* Check for proper value of imod_interval */
1468 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1469 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1470 dwc->imod_interval = 0;
1471 }
1472
1473 /*
1474 * Workaround for STAR 9000961433 which affects only version
1475 * 3.00a of the DWC_usb3 core. This prevents the controller
1476 * interrupt from being masked while handling events. IMOD
1477 * allows us to work around this issue. Enable it for the
1478 * affected version.
1479 */
1480 if (!dwc->imod_interval &&
1481 DWC3_VER_IS(DWC3, 300A))
1482 dwc->imod_interval = 1;
1483
1484 /* Check the maximum_speed parameter */
1485 switch (dwc->maximum_speed) {
1486 case USB_SPEED_LOW:
1487 case USB_SPEED_FULL:
1488 case USB_SPEED_HIGH:
1489 break;
1490 case USB_SPEED_SUPER:
1491 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1492 dev_warn(dev, "UDC doesn't support Gen 1\n");
1493 break;
1494 case USB_SPEED_SUPER_PLUS:
1495 if ((DWC3_IP_IS(DWC32) &&
1496 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1497 (!DWC3_IP_IS(DWC32) &&
1498 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1499 dev_warn(dev, "UDC doesn't support SSP\n");
1500 break;
1501 default:
1502 dev_err(dev, "invalid maximum_speed parameter %d\n",
1503 dwc->maximum_speed);
1504 fallthrough;
1505 case USB_SPEED_UNKNOWN:
1506 switch (hwparam_gen) {
1507 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1508 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1509 break;
1510 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1511 if (DWC3_IP_IS(DWC32))
1512 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1513 else
1514 dwc->maximum_speed = USB_SPEED_SUPER;
1515 break;
1516 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1517 dwc->maximum_speed = USB_SPEED_HIGH;
1518 break;
1519 default:
1520 dwc->maximum_speed = USB_SPEED_SUPER;
1521 break;
1522 }
1523 break;
1524 }
1525
1526 /*
1527 * Currently the controller does not have visibility into the HW
1528 * parameter to determine the maximum number of lanes the HW supports.
1529 * If the number of lanes is not specified in the device property, then
1530 * set the default to support dual-lane for DWC_usb32 and single-lane
1531 * for DWC_usb31 for super-speed-plus.
1532 */
1533 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1534 switch (dwc->max_ssp_rate) {
1535 case USB_SSP_GEN_2x1:
1536 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1537 dev_warn(dev, "UDC only supports Gen 1\n");
1538 break;
1539 case USB_SSP_GEN_1x2:
1540 case USB_SSP_GEN_2x2:
1541 if (DWC3_IP_IS(DWC31))
1542 dev_warn(dev, "UDC only supports single lane\n");
1543 break;
1544 case USB_SSP_GEN_UNKNOWN:
1545 default:
1546 switch (hwparam_gen) {
1547 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1548 if (DWC3_IP_IS(DWC32))
1549 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1550 else
1551 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1552 break;
1553 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1554 if (DWC3_IP_IS(DWC32))
1555 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1556 break;
1557 }
1558 break;
1559 }
1560 }
1561 }
1562
dwc3_probe(struct platform_device * pdev)1563 static int dwc3_probe(struct platform_device *pdev)
1564 {
1565 struct device *dev = &pdev->dev;
1566 struct resource *res, dwc_res;
1567 struct dwc3_vendor *vdwc;
1568 struct dwc3 *dwc;
1569
1570 int ret;
1571
1572 void __iomem *regs;
1573
1574 vdwc = devm_kzalloc(dev, sizeof(*vdwc), GFP_KERNEL);
1575 if (!vdwc)
1576 return -ENOMEM;
1577 dwc = &vdwc->dwc;
1578
1579 dwc->dev = dev;
1580
1581 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1582 if (!res) {
1583 dev_err(dev, "missing memory resource\n");
1584 return -ENODEV;
1585 }
1586
1587 dwc->xhci_resources[0].start = res->start;
1588 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1589 DWC3_XHCI_REGS_END;
1590 dwc->xhci_resources[0].flags = res->flags;
1591 dwc->xhci_resources[0].name = res->name;
1592
1593 /*
1594 * Request memory region but exclude xHCI regs,
1595 * since it will be requested by the xhci-plat driver.
1596 */
1597 dwc_res = *res;
1598 dwc_res.start += DWC3_GLOBALS_REGS_START;
1599
1600 regs = devm_ioremap_resource(dev, &dwc_res);
1601 if (IS_ERR(regs))
1602 return PTR_ERR(regs);
1603
1604 dwc->regs = regs;
1605 dwc->regs_size = resource_size(&dwc_res);
1606
1607 dwc3_get_properties(dwc);
1608
1609 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1610 if (IS_ERR(dwc->reset))
1611 return PTR_ERR(dwc->reset);
1612
1613 if (dev->of_node) {
1614 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1615 if (ret == -EPROBE_DEFER)
1616 return ret;
1617 /*
1618 * Clocks are optional, but new DT platforms should support all
1619 * clocks as required by the DT-binding.
1620 */
1621 if (ret < 0)
1622 dwc->num_clks = 0;
1623 else
1624 dwc->num_clks = ret;
1625
1626 }
1627
1628 ret = reset_control_deassert(dwc->reset);
1629 if (ret)
1630 return ret;
1631
1632 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1633 if (ret)
1634 goto assert_reset;
1635
1636 if (!dwc3_core_is_valid(dwc)) {
1637 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1638 ret = -ENODEV;
1639 goto disable_clks;
1640 }
1641
1642 platform_set_drvdata(pdev, dwc);
1643 dwc3_cache_hwparams(dwc);
1644
1645 spin_lock_init(&dwc->lock);
1646 mutex_init(&dwc->mutex);
1647
1648 pm_runtime_set_active(dev);
1649 pm_runtime_use_autosuspend(dev);
1650 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1651 pm_runtime_enable(dev);
1652 ret = pm_runtime_get_sync(dev);
1653 if (ret < 0)
1654 goto err1;
1655
1656 pm_runtime_forbid(dev);
1657
1658 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1659 if (ret) {
1660 dev_err(dwc->dev, "failed to allocate event buffers\n");
1661 ret = -ENOMEM;
1662 goto err2;
1663 }
1664
1665 ret = dwc3_get_dr_mode(dwc);
1666 if (ret)
1667 goto err3;
1668
1669 ret = dwc3_alloc_scratch_buffers(dwc);
1670 if (ret)
1671 goto err3;
1672
1673 ret = dwc3_core_init(dwc);
1674 if (ret) {
1675 dev_err_probe(dev, ret, "failed to initialize core\n");
1676 goto err4;
1677 }
1678
1679 dwc3_check_params(dwc);
1680 dwc3_debugfs_init(dwc);
1681
1682 ret = dwc3_core_init_mode(dwc);
1683 if (ret)
1684 goto err5;
1685
1686 if (dwc->dr_mode == USB_DR_MODE_OTG &&
1687 of_device_is_compatible(dev->parent->of_node,
1688 "rockchip,rk3399-dwc3")) {
1689 #if defined(CONFIG_ARCH_ROCKCHIP) && defined(CONFIG_NO_GKI)
1690 pm_runtime_set_autosuspend_delay(dev, 100);
1691 #endif
1692 pm_runtime_allow(dev);
1693 pm_runtime_put_sync_suspend(dev);
1694 } else {
1695 pm_runtime_put(dev);
1696 }
1697
1698 return 0;
1699
1700 err5:
1701 dwc3_debugfs_exit(dwc);
1702 dwc3_event_buffers_cleanup(dwc);
1703
1704 usb_phy_set_suspend(dwc->usb2_phy, 1);
1705 usb_phy_set_suspend(dwc->usb3_phy, 1);
1706 phy_power_off(dwc->usb2_generic_phy);
1707 phy_power_off(dwc->usb3_generic_phy);
1708
1709 usb_phy_shutdown(dwc->usb2_phy);
1710 usb_phy_shutdown(dwc->usb3_phy);
1711 phy_exit(dwc->usb2_generic_phy);
1712 phy_exit(dwc->usb3_generic_phy);
1713
1714 dwc3_ulpi_exit(dwc);
1715
1716 err4:
1717 dwc3_free_scratch_buffers(dwc);
1718
1719 err3:
1720 dwc3_free_event_buffers(dwc);
1721
1722 err2:
1723 pm_runtime_allow(&pdev->dev);
1724
1725 err1:
1726 pm_runtime_put_sync(&pdev->dev);
1727 pm_runtime_disable(&pdev->dev);
1728
1729 disable_clks:
1730 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1731 assert_reset:
1732 reset_control_assert(dwc->reset);
1733
1734 if (dwc->usb_psy)
1735 power_supply_put(dwc->usb_psy);
1736
1737 return ret;
1738 }
1739
dwc3_remove(struct platform_device * pdev)1740 static int dwc3_remove(struct platform_device *pdev)
1741 {
1742 struct dwc3 *dwc = platform_get_drvdata(pdev);
1743
1744 pm_runtime_get_sync(&pdev->dev);
1745
1746 dwc3_core_exit_mode(dwc);
1747 dwc3_debugfs_exit(dwc);
1748
1749 dwc3_core_exit(dwc);
1750 dwc3_ulpi_exit(dwc);
1751
1752 pm_runtime_disable(&pdev->dev);
1753 pm_runtime_put_noidle(&pdev->dev);
1754 pm_runtime_set_suspended(&pdev->dev);
1755
1756 dwc3_free_event_buffers(dwc);
1757 dwc3_free_scratch_buffers(dwc);
1758
1759 if (dwc->usb_psy)
1760 power_supply_put(dwc->usb_psy);
1761
1762 return 0;
1763 }
1764
1765 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)1766 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1767 {
1768 int ret;
1769
1770 ret = reset_control_deassert(dwc->reset);
1771 if (ret)
1772 return ret;
1773
1774 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1775 if (ret)
1776 goto assert_reset;
1777
1778 ret = dwc3_core_init(dwc);
1779 if (ret)
1780 goto disable_clks;
1781
1782 return 0;
1783
1784 disable_clks:
1785 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1786 assert_reset:
1787 reset_control_assert(dwc->reset);
1788
1789 return ret;
1790 }
1791
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)1792 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1793 {
1794 unsigned long flags;
1795 u32 reg;
1796
1797 switch (dwc->current_dr_role) {
1798 case DWC3_GCTL_PRTCAP_DEVICE:
1799 if (pm_runtime_suspended(dwc->dev))
1800 break;
1801 dwc3_gadget_suspend(dwc);
1802 synchronize_irq(dwc->irq_gadget);
1803 dwc3_core_exit(dwc);
1804 break;
1805 case DWC3_GCTL_PRTCAP_HOST:
1806 if (!PMSG_IS_AUTO(msg)) {
1807 dwc3_core_exit(dwc);
1808 break;
1809 }
1810
1811 /* Let controller to suspend HSPHY before PHY driver suspends */
1812 if (dwc->dis_u2_susphy_quirk ||
1813 dwc->dis_enblslpm_quirk) {
1814 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1815 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1816 DWC3_GUSB2PHYCFG_SUSPHY;
1817 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1818
1819 /* Give some time for USB2 PHY to suspend */
1820 usleep_range(5000, 6000);
1821 }
1822
1823 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1824 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1825 break;
1826 case DWC3_GCTL_PRTCAP_OTG:
1827 /* do nothing during runtime_suspend */
1828 if (PMSG_IS_AUTO(msg))
1829 break;
1830
1831 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1832 spin_lock_irqsave(&dwc->lock, flags);
1833 dwc3_gadget_suspend(dwc);
1834 spin_unlock_irqrestore(&dwc->lock, flags);
1835 synchronize_irq(dwc->irq_gadget);
1836 }
1837
1838 dwc3_otg_exit(dwc);
1839 dwc3_core_exit(dwc);
1840 break;
1841 default:
1842 if (!pm_runtime_suspended(dwc->dev))
1843 dwc3_core_exit(dwc);
1844 break;
1845 }
1846
1847 return 0;
1848 }
1849
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)1850 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1851 {
1852 unsigned long flags;
1853 int ret;
1854 u32 reg;
1855
1856 switch (dwc->current_dr_role) {
1857 case DWC3_GCTL_PRTCAP_DEVICE:
1858 ret = dwc3_core_init_for_resume(dwc);
1859 if (ret)
1860 return ret;
1861
1862 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1863 dwc3_gadget_resume(dwc);
1864 break;
1865 case DWC3_GCTL_PRTCAP_HOST:
1866 if (!PMSG_IS_AUTO(msg)) {
1867 ret = dwc3_core_init_for_resume(dwc);
1868 if (ret)
1869 return ret;
1870 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1871 break;
1872 }
1873 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1874 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1875 if (dwc->dis_u2_susphy_quirk)
1876 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1877
1878 if (dwc->dis_enblslpm_quirk)
1879 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1880
1881 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1882
1883 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1884 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1885 break;
1886 case DWC3_GCTL_PRTCAP_OTG:
1887 /* nothing to do on runtime_resume */
1888 if (PMSG_IS_AUTO(msg))
1889 break;
1890
1891 ret = dwc3_core_init_for_resume(dwc);
1892 if (ret)
1893 return ret;
1894
1895 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1896
1897 dwc3_otg_init(dwc);
1898 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1899 dwc3_otg_host_init(dwc);
1900 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1901 spin_lock_irqsave(&dwc->lock, flags);
1902 dwc3_gadget_resume(dwc);
1903 spin_unlock_irqrestore(&dwc->lock, flags);
1904 }
1905
1906 break;
1907 default:
1908 ret = dwc3_core_init_for_resume(dwc);
1909 if (ret)
1910 return ret;
1911 break;
1912 }
1913
1914 return 0;
1915 }
1916
dwc3_runtime_checks(struct dwc3 * dwc)1917 static int dwc3_runtime_checks(struct dwc3 *dwc)
1918 {
1919 switch (dwc->current_dr_role) {
1920 case DWC3_GCTL_PRTCAP_DEVICE:
1921 if (dwc->connected)
1922 return -EBUSY;
1923 break;
1924 case DWC3_GCTL_PRTCAP_HOST:
1925 default:
1926 /* do nothing */
1927 break;
1928 }
1929
1930 return 0;
1931 }
1932
dwc3_runtime_suspend(struct device * dev)1933 static int dwc3_runtime_suspend(struct device *dev)
1934 {
1935 struct dwc3 *dwc = dev_get_drvdata(dev);
1936 int ret;
1937
1938 if (dwc3_runtime_checks(dwc))
1939 return -EBUSY;
1940
1941 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1942 if (ret)
1943 return ret;
1944
1945 device_init_wakeup(dev, false);
1946
1947 return 0;
1948 }
1949
dwc3_runtime_resume(struct device * dev)1950 static int dwc3_runtime_resume(struct device *dev)
1951 {
1952 struct dwc3 *dwc = dev_get_drvdata(dev);
1953 int ret;
1954
1955 device_init_wakeup(dev, true);
1956
1957 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1958 if (ret)
1959 return ret;
1960
1961 switch (dwc->current_dr_role) {
1962 case DWC3_GCTL_PRTCAP_DEVICE:
1963 dwc3_gadget_process_pending_events(dwc);
1964 break;
1965 case DWC3_GCTL_PRTCAP_HOST:
1966 default:
1967 /* do nothing */
1968 break;
1969 }
1970
1971 pm_runtime_mark_last_busy(dev);
1972
1973 return 0;
1974 }
1975
dwc3_runtime_idle(struct device * dev)1976 static int dwc3_runtime_idle(struct device *dev)
1977 {
1978 struct dwc3 *dwc = dev_get_drvdata(dev);
1979
1980 switch (dwc->current_dr_role) {
1981 case DWC3_GCTL_PRTCAP_DEVICE:
1982 if (dwc3_runtime_checks(dwc))
1983 return -EBUSY;
1984 break;
1985 case DWC3_GCTL_PRTCAP_HOST:
1986 default:
1987 /* do nothing */
1988 break;
1989 }
1990
1991 pm_runtime_mark_last_busy(dev);
1992 pm_runtime_autosuspend(dev);
1993
1994 return 0;
1995 }
1996 #endif /* CONFIG_PM */
1997
1998 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)1999 static int dwc3_suspend(struct device *dev)
2000 {
2001 struct dwc3 *dwc = dev_get_drvdata(dev);
2002 int ret;
2003
2004 if (pm_runtime_suspended(dwc->dev))
2005 return 0;
2006
2007 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2008 if (ret)
2009 return ret;
2010
2011 pinctrl_pm_select_sleep_state(dev);
2012
2013 return 0;
2014 }
2015
dwc3_resume(struct device * dev)2016 static int dwc3_resume(struct device *dev)
2017 {
2018 struct dwc3 *dwc = dev_get_drvdata(dev);
2019 int ret;
2020
2021 if (pm_runtime_suspended(dwc->dev))
2022 return 0;
2023
2024 pinctrl_pm_select_default_state(dev);
2025
2026 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2027 if (ret)
2028 return ret;
2029
2030 pm_runtime_disable(dev);
2031 pm_runtime_set_active(dev);
2032 pm_runtime_enable(dev);
2033
2034 return 0;
2035 }
2036
dwc3_complete(struct device * dev)2037 static void dwc3_complete(struct device *dev)
2038 {
2039 struct dwc3 *dwc = dev_get_drvdata(dev);
2040 u32 reg;
2041
2042 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2043 dwc->dis_split_quirk) {
2044 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2045 reg |= DWC3_GUCTL3_SPLITDISABLE;
2046 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2047 }
2048 }
2049 #else
2050 #define dwc3_complete NULL
2051 #endif /* CONFIG_PM_SLEEP */
2052
2053 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2054 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2055 .complete = dwc3_complete,
2056 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2057 dwc3_runtime_idle)
2058 };
2059
2060 #ifdef CONFIG_OF
2061 static const struct of_device_id of_dwc3_match[] = {
2062 {
2063 .compatible = "snps,dwc3"
2064 },
2065 {
2066 .compatible = "synopsys,dwc3"
2067 },
2068 { },
2069 };
2070 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2071 #endif
2072
2073 #ifdef CONFIG_ACPI
2074
2075 #define ACPI_ID_INTEL_BSW "808622B7"
2076
2077 static const struct acpi_device_id dwc3_acpi_match[] = {
2078 { ACPI_ID_INTEL_BSW, 0 },
2079 { },
2080 };
2081 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2082 #endif
2083
2084 static struct platform_driver dwc3_driver = {
2085 .probe = dwc3_probe,
2086 .remove = dwc3_remove,
2087 .driver = {
2088 .name = "dwc3",
2089 .of_match_table = of_match_ptr(of_dwc3_match),
2090 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2091 .pm = &dwc3_dev_pm_ops,
2092 },
2093 };
2094
2095 module_platform_driver(dwc3_driver);
2096
2097 MODULE_ALIAS("platform:dwc3");
2098 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2099 MODULE_LICENSE("GPL v2");
2100 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2101