1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * core.c - DesignWare HS OTG Controller common routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * The Core code provides basic services for accessing and managing the
40 * DWC_otg hardware. These services are used by both the Host Controller
41 * Driver and the Peripheral Controller Driver.
42 */
43 #include <linux/kernel.h>
44 #include <linux/module.h>
45 #include <linux/moduleparam.h>
46 #include <linux/spinlock.h>
47 #include <linux/interrupt.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/delay.h>
50 #include <linux/io.h>
51 #include <linux/slab.h>
52 #include <linux/usb.h>
53
54 #include <linux/usb/hcd.h>
55 #include <linux/usb/ch11.h>
56
57 #include "core.h"
58 #include "hcd.h"
59
60 /**
61 * dwc2_backup_global_registers() - Backup global controller registers.
62 * When suspending usb bus, registers needs to be backuped
63 * if controller power is disabled once suspended.
64 *
65 * @hsotg: Programming view of the DWC_otg controller
66 */
dwc2_backup_global_registers(struct dwc2_hsotg * hsotg)67 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
68 {
69 struct dwc2_gregs_backup *gr;
70
71 dev_dbg(hsotg->dev, "%s\n", __func__);
72
73 /* Backup global regs */
74 gr = &hsotg->gr_backup;
75
76 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
77 gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
78 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
79 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
80 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
81 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
82 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
83 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
84 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
85 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
86 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
87
88 gr->valid = true;
89 return 0;
90 }
91
92 /**
93 * dwc2_restore_global_registers() - Restore controller global registers.
94 * When resuming usb bus, device registers needs to be restored
95 * if controller power were disabled.
96 *
97 * @hsotg: Programming view of the DWC_otg controller
98 */
dwc2_restore_global_registers(struct dwc2_hsotg * hsotg)99 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
100 {
101 struct dwc2_gregs_backup *gr;
102
103 dev_dbg(hsotg->dev, "%s\n", __func__);
104
105 /* Restore global regs */
106 gr = &hsotg->gr_backup;
107 if (!gr->valid) {
108 dev_err(hsotg->dev, "%s: no global registers to restore\n",
109 __func__);
110 return -EINVAL;
111 }
112 gr->valid = false;
113
114 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
115 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
116 dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
117 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
118 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
119 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
120 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
121 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
122 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
123 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
124 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
125 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
126
127 return 0;
128 }
129
130 /**
131 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
132 *
133 * @hsotg: Programming view of the DWC_otg controller
134 * @restore: Controller registers need to be restored
135 */
dwc2_exit_partial_power_down(struct dwc2_hsotg * hsotg,bool restore)136 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore)
137 {
138 u32 pcgcctl;
139 int ret = 0;
140
141 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
142 return -ENOTSUPP;
143
144 pcgcctl = dwc2_readl(hsotg, PCGCTL);
145 pcgcctl &= ~PCGCTL_STOPPCLK;
146 dwc2_writel(hsotg, pcgcctl, PCGCTL);
147
148 pcgcctl = dwc2_readl(hsotg, PCGCTL);
149 pcgcctl &= ~PCGCTL_PWRCLMP;
150 dwc2_writel(hsotg, pcgcctl, PCGCTL);
151
152 pcgcctl = dwc2_readl(hsotg, PCGCTL);
153 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
154 dwc2_writel(hsotg, pcgcctl, PCGCTL);
155
156 udelay(100);
157 if (restore) {
158 ret = dwc2_restore_global_registers(hsotg);
159 if (ret) {
160 dev_err(hsotg->dev, "%s: failed to restore registers\n",
161 __func__);
162 return ret;
163 }
164 if (dwc2_is_host_mode(hsotg)) {
165 ret = dwc2_restore_host_registers(hsotg);
166 if (ret) {
167 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
168 __func__);
169 return ret;
170 }
171 } else {
172 ret = dwc2_restore_device_registers(hsotg, 0);
173 if (ret) {
174 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
175 __func__);
176 return ret;
177 }
178 }
179 }
180
181 return ret;
182 }
183
184 /**
185 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
186 *
187 * @hsotg: Programming view of the DWC_otg controller
188 */
dwc2_enter_partial_power_down(struct dwc2_hsotg * hsotg)189 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
190 {
191 u32 pcgcctl;
192 int ret = 0;
193
194 if (!hsotg->params.power_down)
195 return -ENOTSUPP;
196
197 /* Backup all registers */
198 ret = dwc2_backup_global_registers(hsotg);
199 if (ret) {
200 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
201 __func__);
202 return ret;
203 }
204
205 if (dwc2_is_host_mode(hsotg)) {
206 ret = dwc2_backup_host_registers(hsotg);
207 if (ret) {
208 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
209 __func__);
210 return ret;
211 }
212 } else {
213 ret = dwc2_backup_device_registers(hsotg);
214 if (ret) {
215 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
216 __func__);
217 return ret;
218 }
219 }
220
221 /*
222 * Clear any pending interrupts since dwc2 will not be able to
223 * clear them after entering partial_power_down.
224 */
225 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
226
227 /* Put the controller in low power state */
228 pcgcctl = dwc2_readl(hsotg, PCGCTL);
229
230 pcgcctl |= PCGCTL_PWRCLMP;
231 dwc2_writel(hsotg, pcgcctl, PCGCTL);
232 ndelay(20);
233
234 pcgcctl |= PCGCTL_RSTPDWNMODULE;
235 dwc2_writel(hsotg, pcgcctl, PCGCTL);
236 ndelay(20);
237
238 pcgcctl |= PCGCTL_STOPPCLK;
239 dwc2_writel(hsotg, pcgcctl, PCGCTL);
240
241 return ret;
242 }
243
244 /**
245 * dwc2_restore_essential_regs() - Restore essiential regs of core.
246 *
247 * @hsotg: Programming view of the DWC_otg controller
248 * @rmode: Restore mode, enabled in case of remote-wakeup.
249 * @is_host: Host or device mode.
250 */
dwc2_restore_essential_regs(struct dwc2_hsotg * hsotg,int rmode,int is_host)251 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
252 int is_host)
253 {
254 u32 pcgcctl;
255 struct dwc2_gregs_backup *gr;
256 struct dwc2_dregs_backup *dr;
257 struct dwc2_hregs_backup *hr;
258
259 gr = &hsotg->gr_backup;
260 dr = &hsotg->dr_backup;
261 hr = &hsotg->hr_backup;
262
263 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
264
265 /* Load restore values for [31:14] bits */
266 pcgcctl = (gr->pcgcctl & 0xffffc000);
267 /* If High Speed */
268 if (is_host) {
269 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
270 pcgcctl |= BIT(17);
271 } else {
272 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
273 pcgcctl |= BIT(17);
274 }
275 dwc2_writel(hsotg, pcgcctl, PCGCTL);
276
277 /* Umnask global Interrupt in GAHBCFG and restore it */
278 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
279
280 /* Clear all pending interupts */
281 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
282
283 /* Unmask restore done interrupt */
284 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
285
286 /* Restore GUSBCFG and HCFG/DCFG */
287 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
288
289 if (is_host) {
290 dwc2_writel(hsotg, hr->hcfg, HCFG);
291 if (rmode)
292 pcgcctl |= PCGCTL_RESTOREMODE;
293 dwc2_writel(hsotg, pcgcctl, PCGCTL);
294 udelay(10);
295
296 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
297 dwc2_writel(hsotg, pcgcctl, PCGCTL);
298 udelay(10);
299 } else {
300 dwc2_writel(hsotg, dr->dcfg, DCFG);
301 if (!rmode)
302 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
303 dwc2_writel(hsotg, pcgcctl, PCGCTL);
304 udelay(10);
305
306 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
307 dwc2_writel(hsotg, pcgcctl, PCGCTL);
308 udelay(10);
309 }
310 }
311
312 /**
313 * dwc2_hib_restore_common() - Common part of restore routine.
314 *
315 * @hsotg: Programming view of the DWC_otg controller
316 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
317 * @is_host: Host or device mode.
318 */
dwc2_hib_restore_common(struct dwc2_hsotg * hsotg,int rem_wakeup,int is_host)319 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
320 int is_host)
321 {
322 u32 gpwrdn;
323
324 /* Switch-on voltage to the core */
325 gpwrdn = dwc2_readl(hsotg, GPWRDN);
326 gpwrdn &= ~GPWRDN_PWRDNSWTCH;
327 dwc2_writel(hsotg, gpwrdn, GPWRDN);
328 udelay(10);
329
330 /* Reset core */
331 gpwrdn = dwc2_readl(hsotg, GPWRDN);
332 gpwrdn &= ~GPWRDN_PWRDNRSTN;
333 dwc2_writel(hsotg, gpwrdn, GPWRDN);
334 udelay(10);
335
336 /* Enable restore from PMU */
337 gpwrdn = dwc2_readl(hsotg, GPWRDN);
338 gpwrdn |= GPWRDN_RESTORE;
339 dwc2_writel(hsotg, gpwrdn, GPWRDN);
340 udelay(10);
341
342 /* Disable Power Down Clamp */
343 gpwrdn = dwc2_readl(hsotg, GPWRDN);
344 gpwrdn &= ~GPWRDN_PWRDNCLMP;
345 dwc2_writel(hsotg, gpwrdn, GPWRDN);
346 udelay(50);
347
348 if (!is_host && rem_wakeup)
349 udelay(70);
350
351 /* Deassert reset core */
352 gpwrdn = dwc2_readl(hsotg, GPWRDN);
353 gpwrdn |= GPWRDN_PWRDNRSTN;
354 dwc2_writel(hsotg, gpwrdn, GPWRDN);
355 udelay(10);
356
357 /* Disable PMU interrupt */
358 gpwrdn = dwc2_readl(hsotg, GPWRDN);
359 gpwrdn &= ~GPWRDN_PMUINTSEL;
360 dwc2_writel(hsotg, gpwrdn, GPWRDN);
361 udelay(10);
362
363 /* Set Restore Essential Regs bit in PCGCCTL register */
364 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
365
366 /*
367 * Wait For Restore_done Interrupt. This mechanism of polling the
368 * interrupt is introduced to avoid any possible race conditions
369 */
370 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
371 20000)) {
372 dev_dbg(hsotg->dev,
373 "%s: Restore Done wan't generated here\n",
374 __func__);
375 } else {
376 dev_dbg(hsotg->dev, "restore done generated here\n");
377 }
378 }
379
380 /**
381 * dwc2_wait_for_mode() - Waits for the controller mode.
382 * @hsotg: Programming view of the DWC_otg controller.
383 * @host_mode: If true, waits for host mode, otherwise device mode.
384 */
dwc2_wait_for_mode(struct dwc2_hsotg * hsotg,bool host_mode)385 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
386 bool host_mode)
387 {
388 ktime_t start;
389 ktime_t end;
390 unsigned int timeout = 110;
391
392 dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
393 host_mode ? "host" : "device");
394
395 start = ktime_get();
396
397 while (1) {
398 s64 ms;
399
400 if (dwc2_is_host_mode(hsotg) == host_mode) {
401 dev_vdbg(hsotg->dev, "%s mode set\n",
402 host_mode ? "Host" : "Device");
403 break;
404 }
405
406 end = ktime_get();
407 ms = ktime_to_ms(ktime_sub(end, start));
408
409 if (ms >= (s64)timeout) {
410 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
411 __func__, host_mode ? "host" : "device");
412 break;
413 }
414
415 usleep_range(1000, 2000);
416 }
417 }
418
419 /**
420 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
421 * filter is enabled.
422 *
423 * @hsotg: Programming view of DWC_otg controller
424 */
dwc2_iddig_filter_enabled(struct dwc2_hsotg * hsotg)425 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
426 {
427 u32 gsnpsid;
428 u32 ghwcfg4;
429
430 if (!dwc2_hw_is_otg(hsotg))
431 return false;
432
433 /* Check if core configuration includes the IDDIG filter. */
434 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
435 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
436 return false;
437
438 /*
439 * Check if the IDDIG debounce filter is bypassed. Available
440 * in core version >= 3.10a.
441 */
442 gsnpsid = dwc2_readl(hsotg, GSNPSID);
443 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
444 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
445
446 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
447 return false;
448 }
449
450 return true;
451 }
452
453 /*
454 * dwc2_enter_hibernation() - Common function to enter hibernation.
455 *
456 * @hsotg: Programming view of the DWC_otg controller
457 * @is_host: True if core is in host mode.
458 *
459 * Return: 0 if successful, negative error code otherwise
460 */
dwc2_enter_hibernation(struct dwc2_hsotg * hsotg,int is_host)461 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
462 {
463 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_HIBERNATION)
464 return -ENOTSUPP;
465
466 if (is_host)
467 return dwc2_host_enter_hibernation(hsotg);
468 else
469 return dwc2_gadget_enter_hibernation(hsotg);
470 }
471
472 /*
473 * dwc2_exit_hibernation() - Common function to exit from hibernation.
474 *
475 * @hsotg: Programming view of the DWC_otg controller
476 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
477 * @reset: Enabled in case of restore with reset.
478 * @is_host: True if core is in host mode.
479 *
480 * Return: 0 if successful, negative error code otherwise
481 */
dwc2_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset,int is_host)482 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
483 int reset, int is_host)
484 {
485 if (is_host)
486 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
487 else
488 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
489 }
490
491 /*
492 * Do core a soft reset of the core. Be careful with this because it
493 * resets all the internal state machines of the core.
494 */
dwc2_core_reset(struct dwc2_hsotg * hsotg,bool skip_wait)495 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
496 {
497 u32 greset;
498 bool wait_for_host_mode = false;
499
500 dev_vdbg(hsotg->dev, "%s()\n", __func__);
501
502 /*
503 * If the current mode is host, either due to the force mode
504 * bit being set (which persists after core reset) or the
505 * connector id pin, a core soft reset will temporarily reset
506 * the mode to device. A delay from the IDDIG debounce filter
507 * will occur before going back to host mode.
508 *
509 * Determine whether we will go back into host mode after a
510 * reset and account for this delay after the reset.
511 */
512 if (dwc2_iddig_filter_enabled(hsotg)) {
513 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
514 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
515
516 if (!(gotgctl & GOTGCTL_CONID_B) ||
517 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
518 wait_for_host_mode = true;
519 }
520 }
521
522 /* Core Soft Reset */
523 greset = dwc2_readl(hsotg, GRSTCTL);
524 greset |= GRSTCTL_CSFTRST;
525 dwc2_writel(hsotg, greset, GRSTCTL);
526
527 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
528 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
529 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
530 GRSTCTL_CSFTRST, 10000)) {
531 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
532 __func__);
533 return -EBUSY;
534 }
535 } else {
536 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
537 GRSTCTL_CSFTRST_DONE, 10000)) {
538 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
539 __func__);
540 return -EBUSY;
541 }
542 greset = dwc2_readl(hsotg, GRSTCTL);
543 greset &= ~GRSTCTL_CSFTRST;
544 greset |= GRSTCTL_CSFTRST_DONE;
545 dwc2_writel(hsotg, greset, GRSTCTL);
546 }
547
548 /* Wait for AHB master IDLE state */
549 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
550 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
551 __func__);
552 return -EBUSY;
553 }
554
555 if (wait_for_host_mode && !skip_wait)
556 dwc2_wait_for_mode(hsotg, true);
557
558 return 0;
559 }
560
561 /**
562 * dwc2_force_mode() - Force the mode of the controller.
563 *
564 * Forcing the mode is needed for two cases:
565 *
566 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
567 * controller to stay in a particular mode regardless of ID pin
568 * changes. We do this once during probe.
569 *
570 * 2) During probe we want to read reset values of the hw
571 * configuration registers that are only available in either host or
572 * device mode. We may need to force the mode if the current mode does
573 * not allow us to access the register in the mode that we want.
574 *
575 * In either case it only makes sense to force the mode if the
576 * controller hardware is OTG capable.
577 *
578 * Checks are done in this function to determine whether doing a force
579 * would be valid or not.
580 *
581 * If a force is done, it requires a IDDIG debounce filter delay if
582 * the filter is configured and enabled. We poll the current mode of
583 * the controller to account for this delay.
584 *
585 * @hsotg: Programming view of DWC_otg controller
586 * @host: Host mode flag
587 */
dwc2_force_mode(struct dwc2_hsotg * hsotg,bool host)588 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
589 {
590 u32 gusbcfg;
591 u32 set;
592 u32 clear;
593
594 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
595
596 /*
597 * Force mode has no effect if the hardware is not OTG.
598 */
599 if (!dwc2_hw_is_otg(hsotg))
600 return;
601
602 /*
603 * If dr_mode is either peripheral or host only, there is no
604 * need to ever force the mode to the opposite mode.
605 */
606 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
607 return;
608
609 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
610 return;
611
612 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
613
614 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
615 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
616
617 gusbcfg &= ~clear;
618 gusbcfg |= set;
619 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
620
621 dwc2_wait_for_mode(hsotg, host);
622 return;
623 }
624
625 /**
626 * dwc2_clear_force_mode() - Clears the force mode bits.
627 *
628 * After clearing the bits, wait up to 100 ms to account for any
629 * potential IDDIG filter delay. We can't know if we expect this delay
630 * or not because the value of the connector ID status is affected by
631 * the force mode. We only need to call this once during probe if
632 * dr_mode == OTG.
633 *
634 * @hsotg: Programming view of DWC_otg controller
635 */
dwc2_clear_force_mode(struct dwc2_hsotg * hsotg)636 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
637 {
638 u32 gusbcfg;
639
640 if (!dwc2_hw_is_otg(hsotg))
641 return;
642
643 dev_dbg(hsotg->dev, "Clearing force mode bits\n");
644
645 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
646 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
647 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
648 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
649
650 if (dwc2_iddig_filter_enabled(hsotg))
651 msleep(100);
652 }
653
654 /*
655 * Sets or clears force mode based on the dr_mode parameter.
656 */
dwc2_force_dr_mode(struct dwc2_hsotg * hsotg)657 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
658 {
659 u32 count = 0;
660
661 switch (hsotg->dr_mode) {
662 case USB_DR_MODE_HOST:
663 /*
664 * NOTE: This is required for some rockchip soc based
665 * platforms on their host-only dwc2.
666 */
667 if (!dwc2_hw_is_otg(hsotg)) {
668 while (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_CONID_B) {
669 msleep(20);
670 if (++count > 10)
671 break;
672 }
673 if (count > 10)
674 dev_err(hsotg->dev,
675 "Waiting for Host Mode timed out");
676 }
677
678 break;
679 case USB_DR_MODE_PERIPHERAL:
680 dwc2_force_mode(hsotg, false);
681 break;
682 case USB_DR_MODE_OTG:
683 dwc2_clear_force_mode(hsotg);
684 break;
685 default:
686 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
687 __func__, hsotg->dr_mode);
688 break;
689 }
690 }
691
692 /*
693 * dwc2_enable_acg - enable active clock gating feature
694 */
dwc2_enable_acg(struct dwc2_hsotg * hsotg)695 void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
696 {
697 if (hsotg->params.acg_enable) {
698 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
699
700 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
701 pcgcctl1 |= PCGCCTL1_GATEEN;
702 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
703 }
704 }
705
706 /**
707 * dwc2_dump_host_registers() - Prints the host registers
708 *
709 * @hsotg: Programming view of DWC_otg controller
710 *
711 * NOTE: This function will be removed once the peripheral controller code
712 * is integrated and the driver is stable
713 */
dwc2_dump_host_registers(struct dwc2_hsotg * hsotg)714 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
715 {
716 #ifdef DEBUG
717 u32 __iomem *addr;
718 int i;
719
720 dev_dbg(hsotg->dev, "Host Global Registers\n");
721 addr = hsotg->regs + HCFG;
722 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
723 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
724 addr = hsotg->regs + HFIR;
725 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
726 (unsigned long)addr, dwc2_readl(hsotg, HFIR));
727 addr = hsotg->regs + HFNUM;
728 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
729 (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
730 addr = hsotg->regs + HPTXSTS;
731 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
732 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
733 addr = hsotg->regs + HAINT;
734 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
735 (unsigned long)addr, dwc2_readl(hsotg, HAINT));
736 addr = hsotg->regs + HAINTMSK;
737 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
738 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
739 if (hsotg->params.dma_desc_enable) {
740 addr = hsotg->regs + HFLBADDR;
741 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
742 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
743 }
744
745 addr = hsotg->regs + HPRT0;
746 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
747 (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
748
749 for (i = 0; i < hsotg->params.host_channels; i++) {
750 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
751 addr = hsotg->regs + HCCHAR(i);
752 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
753 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
754 addr = hsotg->regs + HCSPLT(i);
755 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
756 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
757 addr = hsotg->regs + HCINT(i);
758 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
759 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
760 addr = hsotg->regs + HCINTMSK(i);
761 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
762 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
763 addr = hsotg->regs + HCTSIZ(i);
764 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
765 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
766 addr = hsotg->regs + HCDMA(i);
767 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
768 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
769 if (hsotg->params.dma_desc_enable) {
770 addr = hsotg->regs + HCDMAB(i);
771 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
772 (unsigned long)addr, dwc2_readl(hsotg,
773 HCDMAB(i)));
774 }
775 }
776 #endif
777 }
778
779 /**
780 * dwc2_dump_global_registers() - Prints the core global registers
781 *
782 * @hsotg: Programming view of DWC_otg controller
783 *
784 * NOTE: This function will be removed once the peripheral controller code
785 * is integrated and the driver is stable
786 */
dwc2_dump_global_registers(struct dwc2_hsotg * hsotg)787 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
788 {
789 #ifdef DEBUG
790 u32 __iomem *addr;
791
792 dev_dbg(hsotg->dev, "Core Global Registers\n");
793 addr = hsotg->regs + GOTGCTL;
794 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
795 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
796 addr = hsotg->regs + GOTGINT;
797 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
798 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
799 addr = hsotg->regs + GAHBCFG;
800 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
801 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
802 addr = hsotg->regs + GUSBCFG;
803 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
804 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
805 addr = hsotg->regs + GRSTCTL;
806 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
807 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
808 addr = hsotg->regs + GINTSTS;
809 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
810 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
811 addr = hsotg->regs + GINTMSK;
812 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
813 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
814 addr = hsotg->regs + GRXSTSR;
815 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
816 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
817 addr = hsotg->regs + GRXFSIZ;
818 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
819 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
820 addr = hsotg->regs + GNPTXFSIZ;
821 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
822 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
823 addr = hsotg->regs + GNPTXSTS;
824 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
825 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
826 addr = hsotg->regs + GI2CCTL;
827 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
828 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
829 addr = hsotg->regs + GPVNDCTL;
830 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
831 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
832 addr = hsotg->regs + GGPIO;
833 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
834 (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
835 addr = hsotg->regs + GUID;
836 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
837 (unsigned long)addr, dwc2_readl(hsotg, GUID));
838 addr = hsotg->regs + GSNPSID;
839 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
840 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
841 addr = hsotg->regs + GHWCFG1;
842 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
843 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
844 addr = hsotg->regs + GHWCFG2;
845 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
846 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
847 addr = hsotg->regs + GHWCFG3;
848 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
849 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
850 addr = hsotg->regs + GHWCFG4;
851 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
852 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
853 addr = hsotg->regs + GLPMCFG;
854 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
855 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
856 addr = hsotg->regs + GPWRDN;
857 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
858 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
859 addr = hsotg->regs + GDFIFOCFG;
860 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
861 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
862 addr = hsotg->regs + HPTXFSIZ;
863 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
864 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
865
866 addr = hsotg->regs + PCGCTL;
867 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
868 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
869 #endif
870 }
871
872 /**
873 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
874 *
875 * @hsotg: Programming view of DWC_otg controller
876 * @num: Tx FIFO to flush
877 */
dwc2_flush_tx_fifo(struct dwc2_hsotg * hsotg,const int num)878 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
879 {
880 u32 greset;
881
882 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
883
884 /* Wait for AHB master IDLE state */
885 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
886 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
887 __func__);
888
889 greset = GRSTCTL_TXFFLSH;
890 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
891 dwc2_writel(hsotg, greset, GRSTCTL);
892
893 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
894 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
895 __func__);
896
897 /* Wait for at least 3 PHY Clocks */
898 udelay(1);
899 }
900
901 /**
902 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
903 *
904 * @hsotg: Programming view of DWC_otg controller
905 */
dwc2_flush_rx_fifo(struct dwc2_hsotg * hsotg)906 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
907 {
908 u32 greset;
909
910 dev_vdbg(hsotg->dev, "%s()\n", __func__);
911
912 /* Wait for AHB master IDLE state */
913 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
914 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
915 __func__);
916
917 greset = GRSTCTL_RXFFLSH;
918 dwc2_writel(hsotg, greset, GRSTCTL);
919
920 /* Wait for RxFIFO flush done */
921 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
922 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
923 __func__);
924
925 /* Wait for at least 3 PHY Clocks */
926 udelay(1);
927 }
928
dwc2_is_controller_alive(struct dwc2_hsotg * hsotg)929 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
930 {
931 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
932 return false;
933 else
934 return true;
935 }
936
937 /**
938 * dwc2_enable_global_interrupts() - Enables the controller's Global
939 * Interrupt in the AHB Config register
940 *
941 * @hsotg: Programming view of DWC_otg controller
942 */
dwc2_enable_global_interrupts(struct dwc2_hsotg * hsotg)943 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
944 {
945 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
946
947 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
948 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
949 }
950
951 /**
952 * dwc2_disable_global_interrupts() - Disables the controller's Global
953 * Interrupt in the AHB Config register
954 *
955 * @hsotg: Programming view of DWC_otg controller
956 */
dwc2_disable_global_interrupts(struct dwc2_hsotg * hsotg)957 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
958 {
959 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
960
961 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
962 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
963 }
964
965 /* Returns the controller's GHWCFG2.OTG_MODE. */
dwc2_op_mode(struct dwc2_hsotg * hsotg)966 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
967 {
968 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
969
970 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
971 GHWCFG2_OP_MODE_SHIFT;
972 }
973
974 /* Returns true if the controller is capable of DRD. */
dwc2_hw_is_otg(struct dwc2_hsotg * hsotg)975 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
976 {
977 unsigned int op_mode = dwc2_op_mode(hsotg);
978
979 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
980 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
981 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
982 }
983
984 /* Returns true if the controller is host-only. */
dwc2_hw_is_host(struct dwc2_hsotg * hsotg)985 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
986 {
987 unsigned int op_mode = dwc2_op_mode(hsotg);
988
989 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
990 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
991 }
992
993 /* Returns true if the controller is device-only. */
dwc2_hw_is_device(struct dwc2_hsotg * hsotg)994 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
995 {
996 unsigned int op_mode = dwc2_op_mode(hsotg);
997
998 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
999 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
1000 }
1001
1002 /**
1003 * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
1004 * @hsotg: Programming view of DWC_otg controller.
1005 * @offset: Register's offset where bit/bits must be set.
1006 * @mask: Mask of the bit/bits which must be set.
1007 * @timeout: Timeout to wait.
1008 *
1009 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
1010 */
dwc2_hsotg_wait_bit_set(struct dwc2_hsotg * hsotg,u32 offset,u32 mask,u32 timeout)1011 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
1012 u32 timeout)
1013 {
1014 u32 i;
1015
1016 for (i = 0; i < timeout; i++) {
1017 if (dwc2_readl(hsotg, offset) & mask)
1018 return 0;
1019 udelay(1);
1020 }
1021
1022 return -ETIMEDOUT;
1023 }
1024
1025 /**
1026 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
1027 * @hsotg: Programming view of DWC_otg controller.
1028 * @offset: Register's offset where bit/bits must be set.
1029 * @mask: Mask of the bit/bits which must be set.
1030 * @timeout: Timeout to wait.
1031 *
1032 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
1033 */
dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg * hsotg,u32 offset,u32 mask,u32 timeout)1034 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
1035 u32 timeout)
1036 {
1037 u32 i;
1038
1039 for (i = 0; i < timeout; i++) {
1040 if (!(dwc2_readl(hsotg, offset) & mask))
1041 return 0;
1042 udelay(1);
1043 }
1044
1045 return -ETIMEDOUT;
1046 }
1047
1048 /*
1049 * Initializes the FSLSPClkSel field of the HCFG register depending on the
1050 * PHY type
1051 */
dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg * hsotg)1052 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
1053 {
1054 u32 hcfg, val;
1055
1056 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1057 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1058 hsotg->params.ulpi_fs_ls) ||
1059 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1060 /* Full speed PHY */
1061 val = HCFG_FSLSPCLKSEL_48_MHZ;
1062 } else {
1063 /* High speed PHY running at full speed or high speed */
1064 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
1065 }
1066
1067 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
1068 hcfg = dwc2_readl(hsotg, HCFG);
1069 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
1070 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
1071 dwc2_writel(hsotg, hcfg, HCFG);
1072 }
1073
dwc2_fs_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1074 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1075 {
1076 u32 usbcfg, ggpio, i2cctl;
1077 int retval = 0;
1078
1079 /*
1080 * core_init() is now called on every switch so only call the
1081 * following for the first time through
1082 */
1083 if (select_phy) {
1084 dev_dbg(hsotg->dev, "FS PHY selected\n");
1085
1086 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1087 if (!(usbcfg & GUSBCFG_PHYSEL)) {
1088 usbcfg |= GUSBCFG_PHYSEL;
1089 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1090
1091 /* Reset after a PHY select */
1092 retval = dwc2_core_reset(hsotg, false);
1093
1094 if (retval) {
1095 dev_err(hsotg->dev,
1096 "%s: Reset failed, aborting", __func__);
1097 return retval;
1098 }
1099 }
1100
1101 if (hsotg->params.activate_stm_fs_transceiver) {
1102 ggpio = dwc2_readl(hsotg, GGPIO);
1103 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1104 dev_dbg(hsotg->dev, "Activating transceiver\n");
1105 /*
1106 * STM32F4x9 uses the GGPIO register as general
1107 * core configuration register.
1108 */
1109 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1110 dwc2_writel(hsotg, ggpio, GGPIO);
1111 }
1112 }
1113 }
1114
1115 /*
1116 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1117 * do this on HNP Dev/Host mode switches (done in dev_init and
1118 * host_init).
1119 */
1120 if (dwc2_is_host_mode(hsotg))
1121 dwc2_init_fs_ls_pclk_sel(hsotg);
1122
1123 if (hsotg->params.i2c_enable) {
1124 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1125
1126 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
1127 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1128 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1129 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1130
1131 /* Program GI2CCTL.I2CEn */
1132 i2cctl = dwc2_readl(hsotg, GI2CCTL);
1133 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1134 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1135 i2cctl &= ~GI2CCTL_I2CEN;
1136 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1137 i2cctl |= GI2CCTL_I2CEN;
1138 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1139 }
1140
1141 return retval;
1142 }
1143
dwc2_hs_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1144 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1145 {
1146 u32 usbcfg, usbcfg_old;
1147 int retval = 0;
1148
1149 if (!select_phy)
1150 return 0;
1151
1152 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1153 usbcfg_old = usbcfg;
1154
1155 /*
1156 * HS PHY parameters. These parameters are preserved during soft reset
1157 * so only program the first time. Do a soft reset immediately after
1158 * setting phyif.
1159 */
1160 switch (hsotg->params.phy_type) {
1161 case DWC2_PHY_TYPE_PARAM_ULPI:
1162 /* ULPI interface */
1163 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1164 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1165 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1166 if (hsotg->params.phy_ulpi_ddr)
1167 usbcfg |= GUSBCFG_DDRSEL;
1168
1169 /* Set external VBUS indicator as needed. */
1170 if (hsotg->params.oc_disable)
1171 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1172 GUSBCFG_INDICATORPASSTHROUGH);
1173 break;
1174 case DWC2_PHY_TYPE_PARAM_UTMI:
1175 /* UTMI+ interface */
1176 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1177 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1178 if (hsotg->params.phy_utmi_width == 16)
1179 usbcfg |= GUSBCFG_PHYIF16;
1180 break;
1181 default:
1182 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1183 break;
1184 }
1185
1186 if (usbcfg != usbcfg_old) {
1187 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1188
1189 /* Reset after setting the PHY parameters */
1190 retval = dwc2_core_reset(hsotg, false);
1191 if (retval) {
1192 dev_err(hsotg->dev,
1193 "%s: Reset failed, aborting", __func__);
1194 return retval;
1195 }
1196 }
1197
1198 return retval;
1199 }
1200
dwc2_set_turnaround_time(struct dwc2_hsotg * hsotg)1201 static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1202 {
1203 u32 usbcfg;
1204
1205 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1206 return;
1207
1208 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1209
1210 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1211 if (hsotg->params.phy_utmi_width == 16)
1212 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1213 else
1214 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1215
1216 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1217 }
1218
dwc2_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1219 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1220 {
1221 u32 usbcfg;
1222 int retval = 0;
1223
1224 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1225 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1226 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1227 /* If FS/LS mode with FS/LS PHY */
1228 retval = dwc2_fs_phy_init(hsotg, select_phy);
1229 if (retval)
1230 return retval;
1231 } else {
1232 /* High speed PHY */
1233 retval = dwc2_hs_phy_init(hsotg, select_phy);
1234 if (retval)
1235 return retval;
1236
1237 if (dwc2_is_device_mode(hsotg))
1238 dwc2_set_turnaround_time(hsotg);
1239 }
1240
1241 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1242 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1243 hsotg->params.ulpi_fs_ls) {
1244 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1245 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1246 usbcfg |= GUSBCFG_ULPI_FS_LS;
1247 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1248 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1249 } else {
1250 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1251 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1252 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1253 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1254 }
1255
1256 return retval;
1257 }
1258
1259 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1260 MODULE_AUTHOR("Synopsys, Inc.");
1261 MODULE_LICENSE("Dual BSD/GPL");
1262