1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Cadence USB3 and USBSSP DRD header file. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2018-2020 Cadence. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Pawel Laszczak <pawell@cadence.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __LINUX_CDNS3_DRD 10*4882a593Smuzhiyun #define __LINUX_CDNS3_DRD 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/usb/otg.h> 13*4882a593Smuzhiyun #include <linux/phy/phy.h> 14*4882a593Smuzhiyun #include "core.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* DRD register interface for version v1 of cdns3 driver. */ 17*4882a593Smuzhiyun struct cdns3_otg_regs { 18*4882a593Smuzhiyun __le32 did; 19*4882a593Smuzhiyun __le32 rid; 20*4882a593Smuzhiyun __le32 capabilities; 21*4882a593Smuzhiyun __le32 reserved1; 22*4882a593Smuzhiyun __le32 cmd; 23*4882a593Smuzhiyun __le32 sts; 24*4882a593Smuzhiyun __le32 state; 25*4882a593Smuzhiyun __le32 reserved2; 26*4882a593Smuzhiyun __le32 ien; 27*4882a593Smuzhiyun __le32 ivect; 28*4882a593Smuzhiyun __le32 refclk; 29*4882a593Smuzhiyun __le32 tmr; 30*4882a593Smuzhiyun __le32 reserved3[4]; 31*4882a593Smuzhiyun __le32 simulate; 32*4882a593Smuzhiyun __le32 override; 33*4882a593Smuzhiyun __le32 susp_ctrl; 34*4882a593Smuzhiyun __le32 phyrst_cfg; 35*4882a593Smuzhiyun __le32 anasts; 36*4882a593Smuzhiyun __le32 adp_ramp_time; 37*4882a593Smuzhiyun __le32 ctrl1; 38*4882a593Smuzhiyun __le32 ctrl2; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* DRD register interface for version v0 of cdns3 driver. */ 42*4882a593Smuzhiyun struct cdns3_otg_legacy_regs { 43*4882a593Smuzhiyun __le32 cmd; 44*4882a593Smuzhiyun __le32 sts; 45*4882a593Smuzhiyun __le32 state; 46*4882a593Smuzhiyun __le32 refclk; 47*4882a593Smuzhiyun __le32 ien; 48*4882a593Smuzhiyun __le32 ivect; 49*4882a593Smuzhiyun __le32 reserved1[3]; 50*4882a593Smuzhiyun __le32 tmr; 51*4882a593Smuzhiyun __le32 reserved2[2]; 52*4882a593Smuzhiyun __le32 version; 53*4882a593Smuzhiyun __le32 capabilities; 54*4882a593Smuzhiyun __le32 reserved3[2]; 55*4882a593Smuzhiyun __le32 simulate; 56*4882a593Smuzhiyun __le32 reserved4[5]; 57*4882a593Smuzhiyun __le32 ctrl1; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* DRD register interface for cdnsp driver */ 61*4882a593Smuzhiyun struct cdnsp_otg_regs { 62*4882a593Smuzhiyun __le32 did; 63*4882a593Smuzhiyun __le32 rid; 64*4882a593Smuzhiyun __le32 cfgs1; 65*4882a593Smuzhiyun __le32 cfgs2; 66*4882a593Smuzhiyun __le32 cmd; 67*4882a593Smuzhiyun __le32 sts; 68*4882a593Smuzhiyun __le32 state; 69*4882a593Smuzhiyun __le32 ien; 70*4882a593Smuzhiyun __le32 ivect; 71*4882a593Smuzhiyun __le32 tmr; 72*4882a593Smuzhiyun __le32 simulate; 73*4882a593Smuzhiyun __le32 adpbc_sts; 74*4882a593Smuzhiyun __le32 adp_ramp_time; 75*4882a593Smuzhiyun __le32 adpbc_ctrl1; 76*4882a593Smuzhiyun __le32 adpbc_ctrl2; 77*4882a593Smuzhiyun __le32 override; 78*4882a593Smuzhiyun __le32 vbusvalid_dbnc_cfg; 79*4882a593Smuzhiyun __le32 sessvalid_dbnc_cfg; 80*4882a593Smuzhiyun __le32 susp_timing_ctrl; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define OTG_CDNSP_DID 0x0004034E 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 86*4882a593Smuzhiyun * Common registers interface for both CDNS3 and CDNSP version of DRD. 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun struct cdns3_otg_common_regs { 89*4882a593Smuzhiyun __le32 cmd; 90*4882a593Smuzhiyun __le32 sts; 91*4882a593Smuzhiyun __le32 state; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* 95*4882a593Smuzhiyun * Interrupt related registers. This registers are mapped in different 96*4882a593Smuzhiyun * location for CDNSP controller. 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun struct cdns3_otg_irq_regs { 99*4882a593Smuzhiyun __le32 ien; 100*4882a593Smuzhiyun __le32 ivect; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* CDNS_RID - bitmasks */ 104*4882a593Smuzhiyun #define CDNS_RID(p) ((p) & GENMASK(15, 0)) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* CDNS_VID - bitmasks */ 107*4882a593Smuzhiyun #define CDNS_DID(p) ((p) & GENMASK(31, 0)) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* OTGCMD - bitmasks */ 110*4882a593Smuzhiyun /* "Request the bus for Device mode. */ 111*4882a593Smuzhiyun #define OTGCMD_DEV_BUS_REQ BIT(0) 112*4882a593Smuzhiyun /* Request the bus for Host mode */ 113*4882a593Smuzhiyun #define OTGCMD_HOST_BUS_REQ BIT(1) 114*4882a593Smuzhiyun /* Enable OTG mode. */ 115*4882a593Smuzhiyun #define OTGCMD_OTG_EN BIT(2) 116*4882a593Smuzhiyun /* Disable OTG mode */ 117*4882a593Smuzhiyun #define OTGCMD_OTG_DIS BIT(3) 118*4882a593Smuzhiyun /*"Configure OTG as A-Device. */ 119*4882a593Smuzhiyun #define OTGCMD_A_DEV_EN BIT(4) 120*4882a593Smuzhiyun /*"Configure OTG as A-Device. */ 121*4882a593Smuzhiyun #define OTGCMD_A_DEV_DIS BIT(5) 122*4882a593Smuzhiyun /* Drop the bus for Device mod e. */ 123*4882a593Smuzhiyun #define OTGCMD_DEV_BUS_DROP BIT(8) 124*4882a593Smuzhiyun /* Drop the bus for Host mode*/ 125*4882a593Smuzhiyun #define OTGCMD_HOST_BUS_DROP BIT(9) 126*4882a593Smuzhiyun /* Power Down USBSS-DEV - only for CDNS3.*/ 127*4882a593Smuzhiyun #define OTGCMD_DEV_POWER_OFF BIT(11) 128*4882a593Smuzhiyun /* Power Down CDNSXHCI - only for CDNS3. */ 129*4882a593Smuzhiyun #define OTGCMD_HOST_POWER_OFF BIT(12) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* OTGIEN - bitmasks */ 132*4882a593Smuzhiyun /* ID change interrupt enable */ 133*4882a593Smuzhiyun #define OTGIEN_ID_CHANGE_INT BIT(0) 134*4882a593Smuzhiyun /* Vbusvalid fall detected interrupt enable.*/ 135*4882a593Smuzhiyun #define OTGIEN_VBUSVALID_RISE_INT BIT(4) 136*4882a593Smuzhiyun /* Vbusvalid fall detected interrupt enable */ 137*4882a593Smuzhiyun #define OTGIEN_VBUSVALID_FALL_INT BIT(5) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* OTGSTS - bitmasks */ 140*4882a593Smuzhiyun /* 141*4882a593Smuzhiyun * Current value of the ID pin. It is only valid when idpullup in 142*4882a593Smuzhiyun * OTGCTRL1_TYPE register is set to '1'. 143*4882a593Smuzhiyun */ 144*4882a593Smuzhiyun #define OTGSTS_ID_VALUE BIT(0) 145*4882a593Smuzhiyun /* Current value of the vbus_valid */ 146*4882a593Smuzhiyun #define OTGSTS_VBUS_VALID BIT(1) 147*4882a593Smuzhiyun /* Current value of the b_sess_vld */ 148*4882a593Smuzhiyun #define OTGSTS_SESSION_VALID BIT(2) 149*4882a593Smuzhiyun /*Device mode is active*/ 150*4882a593Smuzhiyun #define OTGSTS_DEV_ACTIVE BIT(3) 151*4882a593Smuzhiyun /* Host mode is active. */ 152*4882a593Smuzhiyun #define OTGSTS_HOST_ACTIVE BIT(4) 153*4882a593Smuzhiyun /* OTG Controller not ready. */ 154*4882a593Smuzhiyun #define OTGSTS_OTG_NRDY_MASK BIT(11) 155*4882a593Smuzhiyun #define OTGSTS_OTG_NRDY(p) ((p) & OTGSTS_OTG_NRDY_MASK) 156*4882a593Smuzhiyun /* 157*4882a593Smuzhiyun * Value of the strap pins for: 158*4882a593Smuzhiyun * CDNS3: 159*4882a593Smuzhiyun * 000 - no default configuration 160*4882a593Smuzhiyun * 010 - Controller initiall configured as Host 161*4882a593Smuzhiyun * 100 - Controller initially configured as Device 162*4882a593Smuzhiyun * CDNSP: 163*4882a593Smuzhiyun * 000 - No default configuration. 164*4882a593Smuzhiyun * 010 - Controller initiall configured as Host. 165*4882a593Smuzhiyun * 100 - Controller initially configured as Device. 166*4882a593Smuzhiyun */ 167*4882a593Smuzhiyun #define OTGSTS_STRAP(p) (((p) & GENMASK(14, 12)) >> 12) 168*4882a593Smuzhiyun #define OTGSTS_STRAP_NO_DEFAULT_CFG 0x00 169*4882a593Smuzhiyun #define OTGSTS_STRAP_HOST_OTG 0x01 170*4882a593Smuzhiyun #define OTGSTS_STRAP_HOST 0x02 171*4882a593Smuzhiyun #define OTGSTS_STRAP_GADGET 0x04 172*4882a593Smuzhiyun #define OTGSTS_CDNSP_STRAP_HOST 0x01 173*4882a593Smuzhiyun #define OTGSTS_CDNSP_STRAP_GADGET 0x02 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* Host mode is turned on. */ 176*4882a593Smuzhiyun #define OTGSTS_CDNS3_XHCI_READY BIT(26) 177*4882a593Smuzhiyun #define OTGSTS_CDNSP_XHCI_READY BIT(27) 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* "Device mode is turned on .*/ 180*4882a593Smuzhiyun #define OTGSTS_CDNS3_DEV_READY BIT(27) 181*4882a593Smuzhiyun #define OTGSTS_CDNSP_DEV_READY BIT(26) 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* OTGSTATE- bitmasks */ 184*4882a593Smuzhiyun #define OTGSTATE_DEV_STATE_MASK GENMASK(2, 0) 185*4882a593Smuzhiyun #define OTGSTATE_HOST_STATE_MASK GENMASK(5, 3) 186*4882a593Smuzhiyun #define OTGSTATE_HOST_STATE_IDLE 0x0 187*4882a593Smuzhiyun #define OTGSTATE_HOST_STATE_VBUS_FALL 0x7 188*4882a593Smuzhiyun #define OTGSTATE_HOST_STATE(p) (((p) & OTGSTATE_HOST_STATE_MASK) >> 3) 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* OTGREFCLK - bitmasks */ 191*4882a593Smuzhiyun #define OTGREFCLK_STB_CLK_SWITCH_EN BIT(31) 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* OVERRIDE - bitmasks */ 194*4882a593Smuzhiyun #define OVERRIDE_IDPULLUP BIT(0) 195*4882a593Smuzhiyun /* Only for CDNS3_CONTROLLER_V0 version */ 196*4882a593Smuzhiyun #define OVERRIDE_IDPULLUP_V0 BIT(24) 197*4882a593Smuzhiyun /* Vbusvalid/Sesvalid override select. */ 198*4882a593Smuzhiyun #define OVERRIDE_SESS_VLD_SEL BIT(10) 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* PHYRST_CFG - bitmasks */ 201*4882a593Smuzhiyun #define PHYRST_CFG_PHYRST_A_ENABLE BIT(0) 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun #define CDNS3_ID_PERIPHERAL 1 204*4882a593Smuzhiyun #define CDNS3_ID_HOST 0 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun bool cdns3_is_host(struct cdns3 *cdns); 207*4882a593Smuzhiyun bool cdns3_is_device(struct cdns3 *cdns); 208*4882a593Smuzhiyun int cdns3_get_id(struct cdns3 *cdns); 209*4882a593Smuzhiyun int cdns3_get_vbus(struct cdns3 *cdns); 210*4882a593Smuzhiyun int cdns3_drd_init(struct cdns3 *cdns); 211*4882a593Smuzhiyun int cdns3_drd_exit(struct cdns3 *cdns); 212*4882a593Smuzhiyun int cdns3_drd_update_mode(struct cdns3 *cdns); 213*4882a593Smuzhiyun int cdns3_drd_gadget_on(struct cdns3 *cdns); 214*4882a593Smuzhiyun void cdns3_drd_gadget_off(struct cdns3 *cdns); 215*4882a593Smuzhiyun int cdns3_drd_host_on(struct cdns3 *cdns); 216*4882a593Smuzhiyun void cdns3_drd_host_off(struct cdns3 *cdns); 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #endif /* __LINUX_CDNS3_DRD */ 219