xref: /OK3568_Linux_fs/kernel/drivers/usb/c67x00/c67x00.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * c67x00.h: Cypress C67X00 USB register and field definitions
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2006-2008 Barco N.V.
6*4882a593Smuzhiyun  *    Derived from the Cypress cy7c67200/300 ezusb linux driver and
7*4882a593Smuzhiyun  *    based on multiple host controller drivers inside the linux kernel.
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #ifndef _USB_C67X00_H
11*4882a593Smuzhiyun #define _USB_C67X00_H
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/spinlock.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/completion.h>
16*4882a593Smuzhiyun #include <linux/mutex.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* ---------------------------------------------------------------------
19*4882a593Smuzhiyun  * Cypress C67x00 register definitions
20*4882a593Smuzhiyun  */
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* Hardware Revision Register */
23*4882a593Smuzhiyun #define HW_REV_REG		0xC004
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /* General USB registers */
26*4882a593Smuzhiyun /* ===================== */
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* USB Control Register */
29*4882a593Smuzhiyun #define USB_CTL_REG(x)		((x) ? 0xC0AA : 0xC08A)
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define LOW_SPEED_PORT(x)	((x) ? 0x0800 : 0x0400)
32*4882a593Smuzhiyun #define HOST_MODE		0x0200
33*4882a593Smuzhiyun #define PORT_RES_EN(x)		((x) ? 0x0100 : 0x0080)
34*4882a593Smuzhiyun #define SOF_EOP_EN(x)		((x) ? 0x0002 : 0x0001)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /* USB status register - Notice it has different content in hcd/udc mode */
37*4882a593Smuzhiyun #define USB_STAT_REG(x)		((x) ? 0xC0B0 : 0xC090)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define EP0_IRQ_FLG		0x0001
40*4882a593Smuzhiyun #define EP1_IRQ_FLG		0x0002
41*4882a593Smuzhiyun #define EP2_IRQ_FLG		0x0004
42*4882a593Smuzhiyun #define EP3_IRQ_FLG		0x0008
43*4882a593Smuzhiyun #define EP4_IRQ_FLG		0x0010
44*4882a593Smuzhiyun #define EP5_IRQ_FLG		0x0020
45*4882a593Smuzhiyun #define EP6_IRQ_FLG		0x0040
46*4882a593Smuzhiyun #define EP7_IRQ_FLG		0x0080
47*4882a593Smuzhiyun #define RESET_IRQ_FLG		0x0100
48*4882a593Smuzhiyun #define SOF_EOP_IRQ_FLG		0x0200
49*4882a593Smuzhiyun #define ID_IRQ_FLG		0x4000
50*4882a593Smuzhiyun #define VBUS_IRQ_FLG		0x8000
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* USB Host only registers */
53*4882a593Smuzhiyun /* ======================= */
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /* Host n Control Register */
56*4882a593Smuzhiyun #define HOST_CTL_REG(x)		((x) ? 0xC0A0 : 0xC080)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define PREAMBLE_EN		0x0080	/* Preamble enable */
59*4882a593Smuzhiyun #define SEQ_SEL			0x0040	/* Data Toggle Sequence Bit Select */
60*4882a593Smuzhiyun #define ISO_EN			0x0010	/* Isochronous enable  */
61*4882a593Smuzhiyun #define ARM_EN			0x0001	/* Arm operation */
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /* Host n Interrupt Enable Register */
64*4882a593Smuzhiyun #define HOST_IRQ_EN_REG(x)	((x) ? 0xC0AC : 0xC08C)
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define SOF_EOP_IRQ_EN		0x0200	/* SOF/EOP Interrupt Enable  */
67*4882a593Smuzhiyun #define SOF_EOP_TMOUT_IRQ_EN	0x0800	/* SOF/EOP Timeout Interrupt Enable  */
68*4882a593Smuzhiyun #define ID_IRQ_EN		0x4000	/* ID interrupt enable */
69*4882a593Smuzhiyun #define VBUS_IRQ_EN		0x8000	/* VBUS interrupt enable */
70*4882a593Smuzhiyun #define DONE_IRQ_EN		0x0001	/* Done Interrupt Enable  */
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* USB status register */
73*4882a593Smuzhiyun #define HOST_STAT_MASK		0x02FD
74*4882a593Smuzhiyun #define PORT_CONNECT_CHANGE(x)	((x) ? 0x0020 : 0x0010)
75*4882a593Smuzhiyun #define PORT_SE0_STATUS(x)	((x) ? 0x0008 : 0x0004)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun /* Host Frame Register */
78*4882a593Smuzhiyun #define HOST_FRAME_REG(x)	((x) ? 0xC0B6 : 0xC096)
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun #define HOST_FRAME_MASK		0x07FF
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /* USB Peripheral only registers */
83*4882a593Smuzhiyun /* ============================= */
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /* Device n Port Sel reg */
86*4882a593Smuzhiyun #define DEVICE_N_PORT_SEL(x)	((x) ? 0xC0A4 : 0xC084)
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /* Device n Interrupt Enable Register */
89*4882a593Smuzhiyun #define DEVICE_N_IRQ_EN_REG(x)	((x) ? 0xC0AC : 0xC08C)
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #define DEVICE_N_ENDPOINT_N_CTL_REG(dev, ep)	((dev)  		\
92*4882a593Smuzhiyun 						 ? (0x0280 + (ep << 4)) \
93*4882a593Smuzhiyun 						 : (0x0200 + (ep << 4)))
94*4882a593Smuzhiyun #define DEVICE_N_ENDPOINT_N_STAT_REG(dev, ep)	((dev)			\
95*4882a593Smuzhiyun 						 ? (0x0286 + (ep << 4)) \
96*4882a593Smuzhiyun 						 : (0x0206 + (ep << 4)))
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define DEVICE_N_ADDRESS(dev)	((dev) ? (0xC0AE) : (0xC08E))
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /* HPI registers */
101*4882a593Smuzhiyun /* ============= */
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* HPI Status register */
104*4882a593Smuzhiyun #define SOFEOP_FLG(x)		(1 << ((x) ? 12 : 10))
105*4882a593Smuzhiyun #define SIEMSG_FLG(x)		(1 << (4 + (x)))
106*4882a593Smuzhiyun #define RESET_FLG(x)		((x) ? 0x0200 : 0x0002)
107*4882a593Smuzhiyun #define DONE_FLG(x)		(1 << (2 + (x)))
108*4882a593Smuzhiyun #define RESUME_FLG(x)		(1 << (6 + (x)))
109*4882a593Smuzhiyun #define MBX_OUT_FLG		0x0001	/* Message out available */
110*4882a593Smuzhiyun #define MBX_IN_FLG		0x0100
111*4882a593Smuzhiyun #define ID_FLG			0x4000
112*4882a593Smuzhiyun #define VBUS_FLG		0x8000
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /* Interrupt routing register */
115*4882a593Smuzhiyun #define HPI_IRQ_ROUTING_REG	0x0142
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define HPI_SWAP_ENABLE(x)	((x) ? 0x0100 : 0x0001)
118*4882a593Smuzhiyun #define RESET_TO_HPI_ENABLE(x)	((x) ? 0x0200 : 0x0002)
119*4882a593Smuzhiyun #define DONE_TO_HPI_ENABLE(x)	((x) ? 0x0008 : 0x0004)
120*4882a593Smuzhiyun #define RESUME_TO_HPI_ENABLE(x)	((x) ? 0x0080 : 0x0040)
121*4882a593Smuzhiyun #define SOFEOP_TO_HPI_EN(x)	((x) ? 0x2000 : 0x0800)
122*4882a593Smuzhiyun #define SOFEOP_TO_CPU_EN(x)	((x) ? 0x1000 : 0x0400)
123*4882a593Smuzhiyun #define ID_TO_HPI_ENABLE	0x4000
124*4882a593Smuzhiyun #define VBUS_TO_HPI_ENABLE	0x8000
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* SIE msg registers */
127*4882a593Smuzhiyun #define SIEMSG_REG(x)		((x) ? 0x0148 : 0x0144)
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define HUSB_TDListDone		0x1000
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun #define SUSB_EP0_MSG		0x0001
132*4882a593Smuzhiyun #define SUSB_EP1_MSG		0x0002
133*4882a593Smuzhiyun #define SUSB_EP2_MSG		0x0004
134*4882a593Smuzhiyun #define SUSB_EP3_MSG		0x0008
135*4882a593Smuzhiyun #define SUSB_EP4_MSG		0x0010
136*4882a593Smuzhiyun #define SUSB_EP5_MSG		0x0020
137*4882a593Smuzhiyun #define SUSB_EP6_MSG		0x0040
138*4882a593Smuzhiyun #define SUSB_EP7_MSG		0x0080
139*4882a593Smuzhiyun #define SUSB_RST_MSG		0x0100
140*4882a593Smuzhiyun #define SUSB_SOF_MSG		0x0200
141*4882a593Smuzhiyun #define SUSB_CFG_MSG		0x0400
142*4882a593Smuzhiyun #define SUSB_SUS_MSG		0x0800
143*4882a593Smuzhiyun #define SUSB_ID_MSG	       	0x4000
144*4882a593Smuzhiyun #define SUSB_VBUS_MSG		0x8000
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /* BIOS interrupt routines */
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun #define SUSBx_RECEIVE_INT(x)	((x) ? 97 : 81)
149*4882a593Smuzhiyun #define SUSBx_SEND_INT(x)	((x) ? 96 : 80)
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun #define SUSBx_DEV_DESC_VEC(x)	((x) ? 0x00D4 : 0x00B4)
152*4882a593Smuzhiyun #define SUSBx_CONF_DESC_VEC(x)	((x) ? 0x00D6 : 0x00B6)
153*4882a593Smuzhiyun #define SUSBx_STRING_DESC_VEC(x) ((x) ? 0x00D8 : 0x00B8)
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun #define CY_HCD_BUF_ADDR		0x500	/* Base address for host */
156*4882a593Smuzhiyun #define SIE_TD_SIZE		0x200	/* size of the td list */
157*4882a593Smuzhiyun #define SIE_TD_BUF_SIZE		0x400	/* size of the data buffer */
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun #define SIE_TD_OFFSET(host)	((host) ? (SIE_TD_SIZE+SIE_TD_BUF_SIZE) : 0)
160*4882a593Smuzhiyun #define SIE_BUF_OFFSET(host)	(SIE_TD_OFFSET(host) + SIE_TD_SIZE)
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun /* Base address of HCD + 2 x TD_SIZE + 2 x TD_BUF_SIZE */
163*4882a593Smuzhiyun #define CY_UDC_REQ_HEADER_BASE	0x1100
164*4882a593Smuzhiyun /* 8- byte request headers for IN/OUT transfers */
165*4882a593Smuzhiyun #define CY_UDC_REQ_HEADER_SIZE	8
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define CY_UDC_REQ_HEADER_ADDR(ep_num)	(CY_UDC_REQ_HEADER_BASE + \
168*4882a593Smuzhiyun 					 ((ep_num) * CY_UDC_REQ_HEADER_SIZE))
169*4882a593Smuzhiyun #define CY_UDC_DESC_BASE_ADDRESS	(CY_UDC_REQ_HEADER_ADDR(8))
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun #define CY_UDC_BIOS_REPLACE_BASE	0x1800
172*4882a593Smuzhiyun #define CY_UDC_REQ_BUFFER_BASE		0x2000
173*4882a593Smuzhiyun #define CY_UDC_REQ_BUFFER_SIZE		0x0400
174*4882a593Smuzhiyun #define CY_UDC_REQ_BUFFER_ADDR(ep_num)	(CY_UDC_REQ_BUFFER_BASE + \
175*4882a593Smuzhiyun 					 ((ep_num) * CY_UDC_REQ_BUFFER_SIZE))
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun /* ---------------------------------------------------------------------
178*4882a593Smuzhiyun  * Driver data structures
179*4882a593Smuzhiyun  */
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun struct c67x00_device;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun /**
184*4882a593Smuzhiyun  * struct c67x00_sie - Common data associated with a SIE
185*4882a593Smuzhiyun  * @lock: lock to protect this struct and the associated chip registers
186*4882a593Smuzhiyun  * @private_data: subdriver dependent data
187*4882a593Smuzhiyun  * @irq: subdriver dependent irq handler, set NULL when not used
188*4882a593Smuzhiyun  * @dev: link to common driver structure
189*4882a593Smuzhiyun  * @sie_num: SIE number on chip, starting from 0
190*4882a593Smuzhiyun  * @mode: SIE mode (host/peripheral/otg/not used)
191*4882a593Smuzhiyun  */
192*4882a593Smuzhiyun struct c67x00_sie {
193*4882a593Smuzhiyun 	/* Entries to be used by the subdrivers */
194*4882a593Smuzhiyun 	spinlock_t lock;	/* protect this structure */
195*4882a593Smuzhiyun 	void *private_data;
196*4882a593Smuzhiyun 	void (*irq) (struct c67x00_sie *sie, u16 int_status, u16 msg);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	/* Read only: */
199*4882a593Smuzhiyun 	struct c67x00_device *dev;
200*4882a593Smuzhiyun 	int sie_num;
201*4882a593Smuzhiyun 	int mode;
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun #define sie_dev(s)	(&(s)->dev->pdev->dev)
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun /**
207*4882a593Smuzhiyun  * struct c67x00_lcp
208*4882a593Smuzhiyun  */
209*4882a593Smuzhiyun struct c67x00_lcp {
210*4882a593Smuzhiyun 	/* Internal use only */
211*4882a593Smuzhiyun 	struct mutex mutex;
212*4882a593Smuzhiyun 	struct completion msg_received;
213*4882a593Smuzhiyun 	u16 last_msg;
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun /*
217*4882a593Smuzhiyun  * struct c67x00_hpi
218*4882a593Smuzhiyun  */
219*4882a593Smuzhiyun struct c67x00_hpi {
220*4882a593Smuzhiyun 	void __iomem *base;
221*4882a593Smuzhiyun 	int regstep;
222*4882a593Smuzhiyun 	spinlock_t lock;
223*4882a593Smuzhiyun 	struct c67x00_lcp lcp;
224*4882a593Smuzhiyun };
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun #define C67X00_SIES	2
227*4882a593Smuzhiyun #define C67X00_PORTS	2
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun /**
230*4882a593Smuzhiyun  * struct c67x00_device - Common data associated with a c67x00 instance
231*4882a593Smuzhiyun  * @hpi: hpi addresses
232*4882a593Smuzhiyun  * @sie: array of sie's on this chip
233*4882a593Smuzhiyun  * @pdev: platform device of instance
234*4882a593Smuzhiyun  * @pdata: configuration provided by the platform
235*4882a593Smuzhiyun  */
236*4882a593Smuzhiyun struct c67x00_device {
237*4882a593Smuzhiyun 	struct c67x00_hpi hpi;
238*4882a593Smuzhiyun 	struct c67x00_sie sie[C67X00_SIES];
239*4882a593Smuzhiyun 	struct platform_device *pdev;
240*4882a593Smuzhiyun 	struct c67x00_platform_data *pdata;
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun /* ---------------------------------------------------------------------
244*4882a593Smuzhiyun  * Low level interface functions
245*4882a593Smuzhiyun  */
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun /* Host Port Interface (HPI) functions */
248*4882a593Smuzhiyun u16 c67x00_ll_hpi_status(struct c67x00_device *dev);
249*4882a593Smuzhiyun void c67x00_ll_hpi_reg_init(struct c67x00_device *dev);
250*4882a593Smuzhiyun void c67x00_ll_hpi_enable_sofeop(struct c67x00_sie *sie);
251*4882a593Smuzhiyun void c67x00_ll_hpi_disable_sofeop(struct c67x00_sie *sie);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun /* General functions */
254*4882a593Smuzhiyun u16 c67x00_ll_fetch_siemsg(struct c67x00_device *dev, int sie_num);
255*4882a593Smuzhiyun u16 c67x00_ll_get_usb_ctl(struct c67x00_sie *sie);
256*4882a593Smuzhiyun void c67x00_ll_usb_clear_status(struct c67x00_sie *sie, u16 bits);
257*4882a593Smuzhiyun u16 c67x00_ll_usb_get_status(struct c67x00_sie *sie);
258*4882a593Smuzhiyun void c67x00_ll_write_mem_le16(struct c67x00_device *dev, u16 addr,
259*4882a593Smuzhiyun 			      void *data, int len);
260*4882a593Smuzhiyun void c67x00_ll_read_mem_le16(struct c67x00_device *dev, u16 addr,
261*4882a593Smuzhiyun 			     void *data, int len);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun /* Host specific functions */
264*4882a593Smuzhiyun void c67x00_ll_set_husb_eot(struct c67x00_device *dev, u16 value);
265*4882a593Smuzhiyun void c67x00_ll_husb_reset(struct c67x00_sie *sie, int port);
266*4882a593Smuzhiyun void c67x00_ll_husb_set_current_td(struct c67x00_sie *sie, u16 addr);
267*4882a593Smuzhiyun u16 c67x00_ll_husb_get_current_td(struct c67x00_sie *sie);
268*4882a593Smuzhiyun u16 c67x00_ll_husb_get_frame(struct c67x00_sie *sie);
269*4882a593Smuzhiyun void c67x00_ll_husb_init_host_port(struct c67x00_sie *sie);
270*4882a593Smuzhiyun void c67x00_ll_husb_reset_port(struct c67x00_sie *sie, int port);
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun /* Called by c67x00_irq to handle lcp interrupts */
273*4882a593Smuzhiyun void c67x00_ll_irq(struct c67x00_device *dev, u16 int_status);
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun /* Setup and teardown */
276*4882a593Smuzhiyun void c67x00_ll_init(struct c67x00_device *dev);
277*4882a593Smuzhiyun void c67x00_ll_release(struct c67x00_device *dev);
278*4882a593Smuzhiyun int c67x00_ll_reset(struct c67x00_device *dev);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun #endif				/* _USB_C67X00_H */
281