1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* sunsab.h: Register Definitions for the Siemens SAB82532 DUSCC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _SUNSAB_H 8*4882a593Smuzhiyun #define _SUNSAB_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct sab82532_async_rd_regs { 11*4882a593Smuzhiyun u8 rfifo[0x20]; /* Receive FIFO */ 12*4882a593Smuzhiyun u8 star; /* Status Register */ 13*4882a593Smuzhiyun u8 __pad1; 14*4882a593Smuzhiyun u8 mode; /* Mode Register */ 15*4882a593Smuzhiyun u8 timr; /* Timer Register */ 16*4882a593Smuzhiyun u8 xon; /* XON Character */ 17*4882a593Smuzhiyun u8 xoff; /* XOFF Character */ 18*4882a593Smuzhiyun u8 tcr; /* Termination Character Register */ 19*4882a593Smuzhiyun u8 dafo; /* Data Format */ 20*4882a593Smuzhiyun u8 rfc; /* RFIFO Control Register */ 21*4882a593Smuzhiyun u8 __pad2; 22*4882a593Smuzhiyun u8 rbcl; /* Receive Byte Count Low */ 23*4882a593Smuzhiyun u8 rbch; /* Receive Byte Count High */ 24*4882a593Smuzhiyun u8 ccr0; /* Channel Configuration Register 0 */ 25*4882a593Smuzhiyun u8 ccr1; /* Channel Configuration Register 1 */ 26*4882a593Smuzhiyun u8 ccr2; /* Channel Configuration Register 2 */ 27*4882a593Smuzhiyun u8 ccr3; /* Channel Configuration Register 3 */ 28*4882a593Smuzhiyun u8 __pad3[4]; 29*4882a593Smuzhiyun u8 vstr; /* Version Status Register */ 30*4882a593Smuzhiyun u8 __pad4[3]; 31*4882a593Smuzhiyun u8 gis; /* Global Interrupt Status */ 32*4882a593Smuzhiyun u8 ipc; /* Interrupt Port Configuration */ 33*4882a593Smuzhiyun u8 isr0; /* Interrupt Status 0 */ 34*4882a593Smuzhiyun u8 isr1; /* Interrupt Status 1 */ 35*4882a593Smuzhiyun u8 pvr; /* Port Value Register */ 36*4882a593Smuzhiyun u8 pis; /* Port Interrupt Status */ 37*4882a593Smuzhiyun u8 pcr; /* Port Configuration Register */ 38*4882a593Smuzhiyun u8 ccr4; /* Channel Configuration Register 4 */ 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct sab82532_async_wr_regs { 42*4882a593Smuzhiyun u8 xfifo[0x20]; /* Transmit FIFO */ 43*4882a593Smuzhiyun u8 cmdr; /* Command Register */ 44*4882a593Smuzhiyun u8 __pad1; 45*4882a593Smuzhiyun u8 mode; 46*4882a593Smuzhiyun u8 timr; 47*4882a593Smuzhiyun u8 xon; 48*4882a593Smuzhiyun u8 xoff; 49*4882a593Smuzhiyun u8 tcr; 50*4882a593Smuzhiyun u8 dafo; 51*4882a593Smuzhiyun u8 rfc; 52*4882a593Smuzhiyun u8 __pad2; 53*4882a593Smuzhiyun u8 xbcl; /* Transmit Byte Count Low */ 54*4882a593Smuzhiyun u8 xbch; /* Transmit Byte Count High */ 55*4882a593Smuzhiyun u8 ccr0; 56*4882a593Smuzhiyun u8 ccr1; 57*4882a593Smuzhiyun u8 ccr2; 58*4882a593Smuzhiyun u8 ccr3; 59*4882a593Smuzhiyun u8 tsax; /* Time-Slot Assignment Reg. Transmit */ 60*4882a593Smuzhiyun u8 tsar; /* Time-Slot Assignment Reg. Receive */ 61*4882a593Smuzhiyun u8 xccr; /* Transmit Channel Capacity Register */ 62*4882a593Smuzhiyun u8 rccr; /* Receive Channel Capacity Register */ 63*4882a593Smuzhiyun u8 bgr; /* Baud Rate Generator Register */ 64*4882a593Smuzhiyun u8 tic; /* Transmit Immediate Character */ 65*4882a593Smuzhiyun u8 mxn; /* Mask XON Character */ 66*4882a593Smuzhiyun u8 mxf; /* Mask XOFF Character */ 67*4882a593Smuzhiyun u8 iva; /* Interrupt Vector Address */ 68*4882a593Smuzhiyun u8 ipc; 69*4882a593Smuzhiyun u8 imr0; /* Interrupt Mask Register 0 */ 70*4882a593Smuzhiyun u8 imr1; /* Interrupt Mask Register 1 */ 71*4882a593Smuzhiyun u8 pvr; 72*4882a593Smuzhiyun u8 pim; /* Port Interrupt Mask */ 73*4882a593Smuzhiyun u8 pcr; 74*4882a593Smuzhiyun u8 ccr4; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun struct sab82532_async_rw_regs { /* Read/Write registers */ 78*4882a593Smuzhiyun u8 __pad1[0x20]; 79*4882a593Smuzhiyun u8 __pad2; 80*4882a593Smuzhiyun u8 __pad3; 81*4882a593Smuzhiyun u8 mode; 82*4882a593Smuzhiyun u8 timr; 83*4882a593Smuzhiyun u8 xon; 84*4882a593Smuzhiyun u8 xoff; 85*4882a593Smuzhiyun u8 tcr; 86*4882a593Smuzhiyun u8 dafo; 87*4882a593Smuzhiyun u8 rfc; 88*4882a593Smuzhiyun u8 __pad4; 89*4882a593Smuzhiyun u8 __pad5; 90*4882a593Smuzhiyun u8 __pad6; 91*4882a593Smuzhiyun u8 ccr0; 92*4882a593Smuzhiyun u8 ccr1; 93*4882a593Smuzhiyun u8 ccr2; 94*4882a593Smuzhiyun u8 ccr3; 95*4882a593Smuzhiyun u8 __pad7; 96*4882a593Smuzhiyun u8 __pad8; 97*4882a593Smuzhiyun u8 __pad9; 98*4882a593Smuzhiyun u8 __pad10; 99*4882a593Smuzhiyun u8 __pad11; 100*4882a593Smuzhiyun u8 __pad12; 101*4882a593Smuzhiyun u8 __pad13; 102*4882a593Smuzhiyun u8 __pad14; 103*4882a593Smuzhiyun u8 __pad15; 104*4882a593Smuzhiyun u8 ipc; 105*4882a593Smuzhiyun u8 __pad16; 106*4882a593Smuzhiyun u8 __pad17; 107*4882a593Smuzhiyun u8 pvr; 108*4882a593Smuzhiyun u8 __pad18; 109*4882a593Smuzhiyun u8 pcr; 110*4882a593Smuzhiyun u8 ccr4; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun union sab82532_async_regs { 114*4882a593Smuzhiyun __volatile__ struct sab82532_async_rd_regs r; 115*4882a593Smuzhiyun __volatile__ struct sab82532_async_wr_regs w; 116*4882a593Smuzhiyun __volatile__ struct sab82532_async_rw_regs rw; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun union sab82532_irq_status { 120*4882a593Smuzhiyun unsigned short stat; 121*4882a593Smuzhiyun struct { 122*4882a593Smuzhiyun unsigned char isr0; 123*4882a593Smuzhiyun unsigned char isr1; 124*4882a593Smuzhiyun } sreg; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* irqflags bits */ 128*4882a593Smuzhiyun #define SAB82532_ALLS 0x00000001 129*4882a593Smuzhiyun #define SAB82532_XPR 0x00000002 130*4882a593Smuzhiyun #define SAB82532_REGS_PENDING 0x00000004 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* RFIFO Status Byte */ 133*4882a593Smuzhiyun #define SAB82532_RSTAT_PE 0x80 134*4882a593Smuzhiyun #define SAB82532_RSTAT_FE 0x40 135*4882a593Smuzhiyun #define SAB82532_RSTAT_PARITY 0x01 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* Status Register (STAR) */ 138*4882a593Smuzhiyun #define SAB82532_STAR_XDOV 0x80 139*4882a593Smuzhiyun #define SAB82532_STAR_XFW 0x40 140*4882a593Smuzhiyun #define SAB82532_STAR_RFNE 0x20 141*4882a593Smuzhiyun #define SAB82532_STAR_FCS 0x10 142*4882a593Smuzhiyun #define SAB82532_STAR_TEC 0x08 143*4882a593Smuzhiyun #define SAB82532_STAR_CEC 0x04 144*4882a593Smuzhiyun #define SAB82532_STAR_CTS 0x02 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Command Register (CMDR) */ 147*4882a593Smuzhiyun #define SAB82532_CMDR_RMC 0x80 148*4882a593Smuzhiyun #define SAB82532_CMDR_RRES 0x40 149*4882a593Smuzhiyun #define SAB82532_CMDR_RFRD 0x20 150*4882a593Smuzhiyun #define SAB82532_CMDR_STI 0x10 151*4882a593Smuzhiyun #define SAB82532_CMDR_XF 0x08 152*4882a593Smuzhiyun #define SAB82532_CMDR_XRES 0x01 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* Mode Register (MODE) */ 155*4882a593Smuzhiyun #define SAB82532_MODE_FRTS 0x40 156*4882a593Smuzhiyun #define SAB82532_MODE_FCTS 0x20 157*4882a593Smuzhiyun #define SAB82532_MODE_FLON 0x10 158*4882a593Smuzhiyun #define SAB82532_MODE_RAC 0x08 159*4882a593Smuzhiyun #define SAB82532_MODE_RTS 0x04 160*4882a593Smuzhiyun #define SAB82532_MODE_TRS 0x02 161*4882a593Smuzhiyun #define SAB82532_MODE_TLP 0x01 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* Timer Register (TIMR) */ 164*4882a593Smuzhiyun #define SAB82532_TIMR_CNT_MASK 0xe0 165*4882a593Smuzhiyun #define SAB82532_TIMR_VALUE_MASK 0x1f 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* Data Format (DAFO) */ 168*4882a593Smuzhiyun #define SAB82532_DAFO_XBRK 0x40 169*4882a593Smuzhiyun #define SAB82532_DAFO_STOP 0x20 170*4882a593Smuzhiyun #define SAB82532_DAFO_PAR_SPACE 0x00 171*4882a593Smuzhiyun #define SAB82532_DAFO_PAR_ODD 0x08 172*4882a593Smuzhiyun #define SAB82532_DAFO_PAR_EVEN 0x10 173*4882a593Smuzhiyun #define SAB82532_DAFO_PAR_MARK 0x18 174*4882a593Smuzhiyun #define SAB82532_DAFO_PARE 0x04 175*4882a593Smuzhiyun #define SAB82532_DAFO_CHL8 0x00 176*4882a593Smuzhiyun #define SAB82532_DAFO_CHL7 0x01 177*4882a593Smuzhiyun #define SAB82532_DAFO_CHL6 0x02 178*4882a593Smuzhiyun #define SAB82532_DAFO_CHL5 0x03 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* RFIFO Control Register (RFC) */ 181*4882a593Smuzhiyun #define SAB82532_RFC_DPS 0x40 182*4882a593Smuzhiyun #define SAB82532_RFC_DXS 0x20 183*4882a593Smuzhiyun #define SAB82532_RFC_RFDF 0x10 184*4882a593Smuzhiyun #define SAB82532_RFC_RFTH_1 0x00 185*4882a593Smuzhiyun #define SAB82532_RFC_RFTH_4 0x04 186*4882a593Smuzhiyun #define SAB82532_RFC_RFTH_16 0x08 187*4882a593Smuzhiyun #define SAB82532_RFC_RFTH_32 0x0c 188*4882a593Smuzhiyun #define SAB82532_RFC_TCDE 0x01 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun /* Received Byte Count High (RBCH) */ 191*4882a593Smuzhiyun #define SAB82532_RBCH_DMA 0x80 192*4882a593Smuzhiyun #define SAB82532_RBCH_CAS 0x20 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* Transmit Byte Count High (XBCH) */ 195*4882a593Smuzhiyun #define SAB82532_XBCH_DMA 0x80 196*4882a593Smuzhiyun #define SAB82532_XBCH_CAS 0x20 197*4882a593Smuzhiyun #define SAB82532_XBCH_XC 0x10 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* Channel Configuration Register 0 (CCR0) */ 200*4882a593Smuzhiyun #define SAB82532_CCR0_PU 0x80 201*4882a593Smuzhiyun #define SAB82532_CCR0_MCE 0x40 202*4882a593Smuzhiyun #define SAB82532_CCR0_SC_NRZ 0x00 203*4882a593Smuzhiyun #define SAB82532_CCR0_SC_NRZI 0x08 204*4882a593Smuzhiyun #define SAB82532_CCR0_SC_FM0 0x10 205*4882a593Smuzhiyun #define SAB82532_CCR0_SC_FM1 0x14 206*4882a593Smuzhiyun #define SAB82532_CCR0_SC_MANCH 0x18 207*4882a593Smuzhiyun #define SAB82532_CCR0_SM_HDLC 0x00 208*4882a593Smuzhiyun #define SAB82532_CCR0_SM_SDLC_LOOP 0x01 209*4882a593Smuzhiyun #define SAB82532_CCR0_SM_BISYNC 0x02 210*4882a593Smuzhiyun #define SAB82532_CCR0_SM_ASYNC 0x03 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun /* Channel Configuration Register 1 (CCR1) */ 213*4882a593Smuzhiyun #define SAB82532_CCR1_ODS 0x10 214*4882a593Smuzhiyun #define SAB82532_CCR1_BCR 0x08 215*4882a593Smuzhiyun #define SAB82532_CCR1_CM_MASK 0x07 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* Channel Configuration Register 2 (CCR2) */ 218*4882a593Smuzhiyun #define SAB82532_CCR2_SOC1 0x80 219*4882a593Smuzhiyun #define SAB82532_CCR2_SOC0 0x40 220*4882a593Smuzhiyun #define SAB82532_CCR2_BR9 0x80 221*4882a593Smuzhiyun #define SAB82532_CCR2_BR8 0x40 222*4882a593Smuzhiyun #define SAB82532_CCR2_BDF 0x20 223*4882a593Smuzhiyun #define SAB82532_CCR2_SSEL 0x10 224*4882a593Smuzhiyun #define SAB82532_CCR2_XCS0 0x20 225*4882a593Smuzhiyun #define SAB82532_CCR2_RCS0 0x10 226*4882a593Smuzhiyun #define SAB82532_CCR2_TOE 0x08 227*4882a593Smuzhiyun #define SAB82532_CCR2_RWX 0x04 228*4882a593Smuzhiyun #define SAB82532_CCR2_DIV 0x01 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun /* Channel Configuration Register 3 (CCR3) */ 231*4882a593Smuzhiyun #define SAB82532_CCR3_PSD 0x01 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun /* Time Slot Assignment Register Transmit (TSAX) */ 234*4882a593Smuzhiyun #define SAB82532_TSAX_TSNX_MASK 0xfc 235*4882a593Smuzhiyun #define SAB82532_TSAX_XCS2 0x02 /* see also CCR2 */ 236*4882a593Smuzhiyun #define SAB82532_TSAX_XCS1 0x01 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun /* Time Slot Assignment Register Receive (TSAR) */ 239*4882a593Smuzhiyun #define SAB82532_TSAR_TSNR_MASK 0xfc 240*4882a593Smuzhiyun #define SAB82532_TSAR_RCS2 0x02 /* see also CCR2 */ 241*4882a593Smuzhiyun #define SAB82532_TSAR_RCS1 0x01 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun /* Version Status Register (VSTR) */ 244*4882a593Smuzhiyun #define SAB82532_VSTR_CD 0x80 245*4882a593Smuzhiyun #define SAB82532_VSTR_DPLA 0x40 246*4882a593Smuzhiyun #define SAB82532_VSTR_VN_MASK 0x0f 247*4882a593Smuzhiyun #define SAB82532_VSTR_VN_1 0x00 248*4882a593Smuzhiyun #define SAB82532_VSTR_VN_2 0x01 249*4882a593Smuzhiyun #define SAB82532_VSTR_VN_3_2 0x02 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /* Global Interrupt Status Register (GIS) */ 252*4882a593Smuzhiyun #define SAB82532_GIS_PI 0x80 253*4882a593Smuzhiyun #define SAB82532_GIS_ISA1 0x08 254*4882a593Smuzhiyun #define SAB82532_GIS_ISA0 0x04 255*4882a593Smuzhiyun #define SAB82532_GIS_ISB1 0x02 256*4882a593Smuzhiyun #define SAB82532_GIS_ISB0 0x01 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun /* Interrupt Vector Address (IVA) */ 259*4882a593Smuzhiyun #define SAB82532_IVA_MASK 0xf1 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun /* Interrupt Port Configuration (IPC) */ 262*4882a593Smuzhiyun #define SAB82532_IPC_VIS 0x80 263*4882a593Smuzhiyun #define SAB82532_IPC_SLA1 0x10 264*4882a593Smuzhiyun #define SAB82532_IPC_SLA0 0x08 265*4882a593Smuzhiyun #define SAB82532_IPC_CASM 0x04 266*4882a593Smuzhiyun #define SAB82532_IPC_IC_OPEN_DRAIN 0x00 267*4882a593Smuzhiyun #define SAB82532_IPC_IC_ACT_LOW 0x01 268*4882a593Smuzhiyun #define SAB82532_IPC_IC_ACT_HIGH 0x03 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun /* Interrupt Status Register 0 (ISR0) */ 271*4882a593Smuzhiyun #define SAB82532_ISR0_TCD 0x80 272*4882a593Smuzhiyun #define SAB82532_ISR0_TIME 0x40 273*4882a593Smuzhiyun #define SAB82532_ISR0_PERR 0x20 274*4882a593Smuzhiyun #define SAB82532_ISR0_FERR 0x10 275*4882a593Smuzhiyun #define SAB82532_ISR0_PLLA 0x08 276*4882a593Smuzhiyun #define SAB82532_ISR0_CDSC 0x04 277*4882a593Smuzhiyun #define SAB82532_ISR0_RFO 0x02 278*4882a593Smuzhiyun #define SAB82532_ISR0_RPF 0x01 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun /* Interrupt Status Register 1 (ISR1) */ 281*4882a593Smuzhiyun #define SAB82532_ISR1_BRK 0x80 282*4882a593Smuzhiyun #define SAB82532_ISR1_BRKT 0x40 283*4882a593Smuzhiyun #define SAB82532_ISR1_ALLS 0x20 284*4882a593Smuzhiyun #define SAB82532_ISR1_XOFF 0x10 285*4882a593Smuzhiyun #define SAB82532_ISR1_TIN 0x08 286*4882a593Smuzhiyun #define SAB82532_ISR1_CSC 0x04 287*4882a593Smuzhiyun #define SAB82532_ISR1_XON 0x02 288*4882a593Smuzhiyun #define SAB82532_ISR1_XPR 0x01 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun /* Interrupt Mask Register 0 (IMR0) */ 291*4882a593Smuzhiyun #define SAB82532_IMR0_TCD 0x80 292*4882a593Smuzhiyun #define SAB82532_IMR0_TIME 0x40 293*4882a593Smuzhiyun #define SAB82532_IMR0_PERR 0x20 294*4882a593Smuzhiyun #define SAB82532_IMR0_FERR 0x10 295*4882a593Smuzhiyun #define SAB82532_IMR0_PLLA 0x08 296*4882a593Smuzhiyun #define SAB82532_IMR0_CDSC 0x04 297*4882a593Smuzhiyun #define SAB82532_IMR0_RFO 0x02 298*4882a593Smuzhiyun #define SAB82532_IMR0_RPF 0x01 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun /* Interrupt Mask Register 1 (IMR1) */ 301*4882a593Smuzhiyun #define SAB82532_IMR1_BRK 0x80 302*4882a593Smuzhiyun #define SAB82532_IMR1_BRKT 0x40 303*4882a593Smuzhiyun #define SAB82532_IMR1_ALLS 0x20 304*4882a593Smuzhiyun #define SAB82532_IMR1_XOFF 0x10 305*4882a593Smuzhiyun #define SAB82532_IMR1_TIN 0x08 306*4882a593Smuzhiyun #define SAB82532_IMR1_CSC 0x04 307*4882a593Smuzhiyun #define SAB82532_IMR1_XON 0x02 308*4882a593Smuzhiyun #define SAB82532_IMR1_XPR 0x01 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* Port Interrupt Status Register (PIS) */ 311*4882a593Smuzhiyun #define SAB82532_PIS_SYNC_B 0x08 312*4882a593Smuzhiyun #define SAB82532_PIS_DTR_B 0x04 313*4882a593Smuzhiyun #define SAB82532_PIS_DTR_A 0x02 314*4882a593Smuzhiyun #define SAB82532_PIS_SYNC_A 0x01 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* Channel Configuration Register 4 (CCR4) */ 317*4882a593Smuzhiyun #define SAB82532_CCR4_MCK4 0x80 318*4882a593Smuzhiyun #define SAB82532_CCR4_EBRG 0x40 319*4882a593Smuzhiyun #define SAB82532_CCR4_TST1 0x20 320*4882a593Smuzhiyun #define SAB82532_CCR4_ICD 0x10 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun #endif /* !(_SUNSAB_H) */ 324