1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Derived from many drivers using generic_serial interface,
4*4882a593Smuzhiyun * especially serial_tx3912.c by Steven J. Hill and r39xx_serial.c
5*4882a593Smuzhiyun * (was in Linux/VR tree) by Jim Pick.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 1999 Harald Koerfgen
8*4882a593Smuzhiyun * Copyright (C) 2000 Jim Pick <jim@jimpick.com>
9*4882a593Smuzhiyun * Copyright (C) 2001 Steven J. Hill (sjhill@realitydiluted.com)
10*4882a593Smuzhiyun * Copyright (C) 2000-2002 Toshiba Corporation
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Serial driver for TX3927/TX4927/TX4925/TX4938 internal SIO controller
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/ioport.h>
17*4882a593Smuzhiyun #include <linux/init.h>
18*4882a593Smuzhiyun #include <linux/console.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun #include <linux/platform_device.h>
21*4882a593Smuzhiyun #include <linux/pci.h>
22*4882a593Smuzhiyun #include <linux/serial_core.h>
23*4882a593Smuzhiyun #include <linux/serial.h>
24*4882a593Smuzhiyun #include <linux/tty.h>
25*4882a593Smuzhiyun #include <linux/tty_flip.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <asm/io.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static char *serial_version = "1.11";
30*4882a593Smuzhiyun static char *serial_name = "TX39/49 Serial driver";
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define PASS_LIMIT 256
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
35*4882a593Smuzhiyun /* "ttyS" is used for standard serial driver */
36*4882a593Smuzhiyun #define TXX9_TTY_NAME "ttyTX"
37*4882a593Smuzhiyun #define TXX9_TTY_MINOR_START 196
38*4882a593Smuzhiyun #define TXX9_TTY_MAJOR 204
39*4882a593Smuzhiyun #else
40*4882a593Smuzhiyun /* acts like standard serial driver */
41*4882a593Smuzhiyun #define TXX9_TTY_NAME "ttyS"
42*4882a593Smuzhiyun #define TXX9_TTY_MINOR_START 64
43*4882a593Smuzhiyun #define TXX9_TTY_MAJOR TTY_MAJOR
44*4882a593Smuzhiyun #endif
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* flag aliases */
47*4882a593Smuzhiyun #define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
48*4882a593Smuzhiyun #define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #ifdef CONFIG_PCI
51*4882a593Smuzhiyun /* support for Toshiba TC86C001 SIO */
52*4882a593Smuzhiyun #define ENABLE_SERIAL_TXX9_PCI
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * Number of serial ports
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun #define UART_NR CONFIG_SERIAL_TXX9_NR_UARTS
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun struct uart_txx9_port {
61*4882a593Smuzhiyun struct uart_port port;
62*4882a593Smuzhiyun /* No additional info for now */
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define TXX9_REGION_SIZE 0x24
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* TXX9 Serial Registers */
68*4882a593Smuzhiyun #define TXX9_SILCR 0x00
69*4882a593Smuzhiyun #define TXX9_SIDICR 0x04
70*4882a593Smuzhiyun #define TXX9_SIDISR 0x08
71*4882a593Smuzhiyun #define TXX9_SICISR 0x0c
72*4882a593Smuzhiyun #define TXX9_SIFCR 0x10
73*4882a593Smuzhiyun #define TXX9_SIFLCR 0x14
74*4882a593Smuzhiyun #define TXX9_SIBGR 0x18
75*4882a593Smuzhiyun #define TXX9_SITFIFO 0x1c
76*4882a593Smuzhiyun #define TXX9_SIRFIFO 0x20
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* SILCR : Line Control */
79*4882a593Smuzhiyun #define TXX9_SILCR_SCS_MASK 0x00000060
80*4882a593Smuzhiyun #define TXX9_SILCR_SCS_IMCLK 0x00000000
81*4882a593Smuzhiyun #define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
82*4882a593Smuzhiyun #define TXX9_SILCR_SCS_SCLK 0x00000040
83*4882a593Smuzhiyun #define TXX9_SILCR_SCS_SCLK_BG 0x00000060
84*4882a593Smuzhiyun #define TXX9_SILCR_UEPS 0x00000010
85*4882a593Smuzhiyun #define TXX9_SILCR_UPEN 0x00000008
86*4882a593Smuzhiyun #define TXX9_SILCR_USBL_MASK 0x00000004
87*4882a593Smuzhiyun #define TXX9_SILCR_USBL_1BIT 0x00000000
88*4882a593Smuzhiyun #define TXX9_SILCR_USBL_2BIT 0x00000004
89*4882a593Smuzhiyun #define TXX9_SILCR_UMODE_MASK 0x00000003
90*4882a593Smuzhiyun #define TXX9_SILCR_UMODE_8BIT 0x00000000
91*4882a593Smuzhiyun #define TXX9_SILCR_UMODE_7BIT 0x00000001
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* SIDICR : DMA/Int. Control */
94*4882a593Smuzhiyun #define TXX9_SIDICR_TDE 0x00008000
95*4882a593Smuzhiyun #define TXX9_SIDICR_RDE 0x00004000
96*4882a593Smuzhiyun #define TXX9_SIDICR_TIE 0x00002000
97*4882a593Smuzhiyun #define TXX9_SIDICR_RIE 0x00001000
98*4882a593Smuzhiyun #define TXX9_SIDICR_SPIE 0x00000800
99*4882a593Smuzhiyun #define TXX9_SIDICR_CTSAC 0x00000600
100*4882a593Smuzhiyun #define TXX9_SIDICR_STIE_MASK 0x0000003f
101*4882a593Smuzhiyun #define TXX9_SIDICR_STIE_OERS 0x00000020
102*4882a593Smuzhiyun #define TXX9_SIDICR_STIE_CTSS 0x00000010
103*4882a593Smuzhiyun #define TXX9_SIDICR_STIE_RBRKD 0x00000008
104*4882a593Smuzhiyun #define TXX9_SIDICR_STIE_TRDY 0x00000004
105*4882a593Smuzhiyun #define TXX9_SIDICR_STIE_TXALS 0x00000002
106*4882a593Smuzhiyun #define TXX9_SIDICR_STIE_UBRKD 0x00000001
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* SIDISR : DMA/Int. Status */
109*4882a593Smuzhiyun #define TXX9_SIDISR_UBRK 0x00008000
110*4882a593Smuzhiyun #define TXX9_SIDISR_UVALID 0x00004000
111*4882a593Smuzhiyun #define TXX9_SIDISR_UFER 0x00002000
112*4882a593Smuzhiyun #define TXX9_SIDISR_UPER 0x00001000
113*4882a593Smuzhiyun #define TXX9_SIDISR_UOER 0x00000800
114*4882a593Smuzhiyun #define TXX9_SIDISR_ERI 0x00000400
115*4882a593Smuzhiyun #define TXX9_SIDISR_TOUT 0x00000200
116*4882a593Smuzhiyun #define TXX9_SIDISR_TDIS 0x00000100
117*4882a593Smuzhiyun #define TXX9_SIDISR_RDIS 0x00000080
118*4882a593Smuzhiyun #define TXX9_SIDISR_STIS 0x00000040
119*4882a593Smuzhiyun #define TXX9_SIDISR_RFDN_MASK 0x0000001f
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* SICISR : Change Int. Status */
122*4882a593Smuzhiyun #define TXX9_SICISR_OERS 0x00000020
123*4882a593Smuzhiyun #define TXX9_SICISR_CTSS 0x00000010
124*4882a593Smuzhiyun #define TXX9_SICISR_RBRKD 0x00000008
125*4882a593Smuzhiyun #define TXX9_SICISR_TRDY 0x00000004
126*4882a593Smuzhiyun #define TXX9_SICISR_TXALS 0x00000002
127*4882a593Smuzhiyun #define TXX9_SICISR_UBRKD 0x00000001
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* SIFCR : FIFO Control */
130*4882a593Smuzhiyun #define TXX9_SIFCR_SWRST 0x00008000
131*4882a593Smuzhiyun #define TXX9_SIFCR_RDIL_MASK 0x00000180
132*4882a593Smuzhiyun #define TXX9_SIFCR_RDIL_1 0x00000000
133*4882a593Smuzhiyun #define TXX9_SIFCR_RDIL_4 0x00000080
134*4882a593Smuzhiyun #define TXX9_SIFCR_RDIL_8 0x00000100
135*4882a593Smuzhiyun #define TXX9_SIFCR_RDIL_12 0x00000180
136*4882a593Smuzhiyun #define TXX9_SIFCR_RDIL_MAX 0x00000180
137*4882a593Smuzhiyun #define TXX9_SIFCR_TDIL_MASK 0x00000018
138*4882a593Smuzhiyun #define TXX9_SIFCR_TDIL_1 0x00000000
139*4882a593Smuzhiyun #define TXX9_SIFCR_TDIL_4 0x00000001
140*4882a593Smuzhiyun #define TXX9_SIFCR_TDIL_8 0x00000010
141*4882a593Smuzhiyun #define TXX9_SIFCR_TDIL_MAX 0x00000010
142*4882a593Smuzhiyun #define TXX9_SIFCR_TFRST 0x00000004
143*4882a593Smuzhiyun #define TXX9_SIFCR_RFRST 0x00000002
144*4882a593Smuzhiyun #define TXX9_SIFCR_FRSTE 0x00000001
145*4882a593Smuzhiyun #define TXX9_SIO_TX_FIFO 8
146*4882a593Smuzhiyun #define TXX9_SIO_RX_FIFO 16
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* SIFLCR : Flow Control */
149*4882a593Smuzhiyun #define TXX9_SIFLCR_RCS 0x00001000
150*4882a593Smuzhiyun #define TXX9_SIFLCR_TES 0x00000800
151*4882a593Smuzhiyun #define TXX9_SIFLCR_RTSSC 0x00000200
152*4882a593Smuzhiyun #define TXX9_SIFLCR_RSDE 0x00000100
153*4882a593Smuzhiyun #define TXX9_SIFLCR_TSDE 0x00000080
154*4882a593Smuzhiyun #define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
155*4882a593Smuzhiyun #define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
156*4882a593Smuzhiyun #define TXX9_SIFLCR_TBRK 0x00000001
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* SIBGR : Baudrate Control */
159*4882a593Smuzhiyun #define TXX9_SIBGR_BCLK_MASK 0x00000300
160*4882a593Smuzhiyun #define TXX9_SIBGR_BCLK_T0 0x00000000
161*4882a593Smuzhiyun #define TXX9_SIBGR_BCLK_T2 0x00000100
162*4882a593Smuzhiyun #define TXX9_SIBGR_BCLK_T4 0x00000200
163*4882a593Smuzhiyun #define TXX9_SIBGR_BCLK_T6 0x00000300
164*4882a593Smuzhiyun #define TXX9_SIBGR_BRD_MASK 0x000000ff
165*4882a593Smuzhiyun
sio_in(struct uart_txx9_port * up,int offset)166*4882a593Smuzhiyun static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun switch (up->port.iotype) {
169*4882a593Smuzhiyun default:
170*4882a593Smuzhiyun return __raw_readl(up->port.membase + offset);
171*4882a593Smuzhiyun case UPIO_PORT:
172*4882a593Smuzhiyun return inl(up->port.iobase + offset);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static inline void
sio_out(struct uart_txx9_port * up,int offset,int value)177*4882a593Smuzhiyun sio_out(struct uart_txx9_port *up, int offset, int value)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun switch (up->port.iotype) {
180*4882a593Smuzhiyun default:
181*4882a593Smuzhiyun __raw_writel(value, up->port.membase + offset);
182*4882a593Smuzhiyun break;
183*4882a593Smuzhiyun case UPIO_PORT:
184*4882a593Smuzhiyun outl(value, up->port.iobase + offset);
185*4882a593Smuzhiyun break;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun static inline void
sio_mask(struct uart_txx9_port * up,int offset,unsigned int value)190*4882a593Smuzhiyun sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun sio_out(up, offset, sio_in(up, offset) & ~value);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun static inline void
sio_set(struct uart_txx9_port * up,int offset,unsigned int value)195*4882a593Smuzhiyun sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun sio_out(up, offset, sio_in(up, offset) | value);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static inline void
sio_quot_set(struct uart_txx9_port * up,int quot)201*4882a593Smuzhiyun sio_quot_set(struct uart_txx9_port *up, int quot)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun quot >>= 1;
204*4882a593Smuzhiyun if (quot < 256)
205*4882a593Smuzhiyun sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
206*4882a593Smuzhiyun else if (quot < (256 << 2))
207*4882a593Smuzhiyun sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
208*4882a593Smuzhiyun else if (quot < (256 << 4))
209*4882a593Smuzhiyun sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
210*4882a593Smuzhiyun else if (quot < (256 << 6))
211*4882a593Smuzhiyun sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
212*4882a593Smuzhiyun else
213*4882a593Smuzhiyun sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
to_uart_txx9_port(struct uart_port * port)216*4882a593Smuzhiyun static struct uart_txx9_port *to_uart_txx9_port(struct uart_port *port)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun return container_of(port, struct uart_txx9_port, port);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
serial_txx9_stop_tx(struct uart_port * port)221*4882a593Smuzhiyun static void serial_txx9_stop_tx(struct uart_port *port)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
224*4882a593Smuzhiyun sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun
serial_txx9_start_tx(struct uart_port * port)227*4882a593Smuzhiyun static void serial_txx9_start_tx(struct uart_port *port)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
230*4882a593Smuzhiyun sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
serial_txx9_stop_rx(struct uart_port * port)233*4882a593Smuzhiyun static void serial_txx9_stop_rx(struct uart_port *port)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
236*4882a593Smuzhiyun up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
serial_txx9_initialize(struct uart_port * port)239*4882a593Smuzhiyun static void serial_txx9_initialize(struct uart_port *port)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
242*4882a593Smuzhiyun unsigned int tmout = 10000;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
245*4882a593Smuzhiyun /* TX4925 BUG WORKAROUND. Accessing SIOC register
246*4882a593Smuzhiyun * immediately after soft reset causes bus error. */
247*4882a593Smuzhiyun udelay(1);
248*4882a593Smuzhiyun while ((sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST) && --tmout)
249*4882a593Smuzhiyun udelay(1);
250*4882a593Smuzhiyun /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
251*4882a593Smuzhiyun sio_set(up, TXX9_SIFCR,
252*4882a593Smuzhiyun TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
253*4882a593Smuzhiyun /* initial settings */
254*4882a593Smuzhiyun sio_out(up, TXX9_SILCR,
255*4882a593Smuzhiyun TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
256*4882a593Smuzhiyun ((up->port.flags & UPF_TXX9_USE_SCLK) ?
257*4882a593Smuzhiyun TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
258*4882a593Smuzhiyun sio_quot_set(up, uart_get_divisor(port, 9600));
259*4882a593Smuzhiyun sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX /* 15 */);
260*4882a593Smuzhiyun sio_out(up, TXX9_SIDICR, 0);
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun static inline void
receive_chars(struct uart_txx9_port * up,unsigned int * status)264*4882a593Smuzhiyun receive_chars(struct uart_txx9_port *up, unsigned int *status)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun unsigned char ch;
267*4882a593Smuzhiyun unsigned int disr = *status;
268*4882a593Smuzhiyun int max_count = 256;
269*4882a593Smuzhiyun char flag;
270*4882a593Smuzhiyun unsigned int next_ignore_status_mask;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun do {
273*4882a593Smuzhiyun ch = sio_in(up, TXX9_SIRFIFO);
274*4882a593Smuzhiyun flag = TTY_NORMAL;
275*4882a593Smuzhiyun up->port.icount.rx++;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun /* mask out RFDN_MASK bit added by previous overrun */
278*4882a593Smuzhiyun next_ignore_status_mask =
279*4882a593Smuzhiyun up->port.ignore_status_mask & ~TXX9_SIDISR_RFDN_MASK;
280*4882a593Smuzhiyun if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
281*4882a593Smuzhiyun TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
282*4882a593Smuzhiyun /*
283*4882a593Smuzhiyun * For statistics only
284*4882a593Smuzhiyun */
285*4882a593Smuzhiyun if (disr & TXX9_SIDISR_UBRK) {
286*4882a593Smuzhiyun disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
287*4882a593Smuzhiyun up->port.icount.brk++;
288*4882a593Smuzhiyun /*
289*4882a593Smuzhiyun * We do the SysRQ and SAK checking
290*4882a593Smuzhiyun * here because otherwise the break
291*4882a593Smuzhiyun * may get masked by ignore_status_mask
292*4882a593Smuzhiyun * or read_status_mask.
293*4882a593Smuzhiyun */
294*4882a593Smuzhiyun if (uart_handle_break(&up->port))
295*4882a593Smuzhiyun goto ignore_char;
296*4882a593Smuzhiyun } else if (disr & TXX9_SIDISR_UPER)
297*4882a593Smuzhiyun up->port.icount.parity++;
298*4882a593Smuzhiyun else if (disr & TXX9_SIDISR_UFER)
299*4882a593Smuzhiyun up->port.icount.frame++;
300*4882a593Smuzhiyun if (disr & TXX9_SIDISR_UOER) {
301*4882a593Smuzhiyun up->port.icount.overrun++;
302*4882a593Smuzhiyun /*
303*4882a593Smuzhiyun * The receiver read buffer still hold
304*4882a593Smuzhiyun * a char which caused overrun.
305*4882a593Smuzhiyun * Ignore next char by adding RFDN_MASK
306*4882a593Smuzhiyun * to ignore_status_mask temporarily.
307*4882a593Smuzhiyun */
308*4882a593Smuzhiyun next_ignore_status_mask |=
309*4882a593Smuzhiyun TXX9_SIDISR_RFDN_MASK;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /*
313*4882a593Smuzhiyun * Mask off conditions which should be ingored.
314*4882a593Smuzhiyun */
315*4882a593Smuzhiyun disr &= up->port.read_status_mask;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun if (disr & TXX9_SIDISR_UBRK) {
318*4882a593Smuzhiyun flag = TTY_BREAK;
319*4882a593Smuzhiyun } else if (disr & TXX9_SIDISR_UPER)
320*4882a593Smuzhiyun flag = TTY_PARITY;
321*4882a593Smuzhiyun else if (disr & TXX9_SIDISR_UFER)
322*4882a593Smuzhiyun flag = TTY_FRAME;
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun if (uart_handle_sysrq_char(&up->port, ch))
325*4882a593Smuzhiyun goto ignore_char;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun ignore_char:
330*4882a593Smuzhiyun up->port.ignore_status_mask = next_ignore_status_mask;
331*4882a593Smuzhiyun disr = sio_in(up, TXX9_SIDISR);
332*4882a593Smuzhiyun } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
333*4882a593Smuzhiyun spin_unlock(&up->port.lock);
334*4882a593Smuzhiyun tty_flip_buffer_push(&up->port.state->port);
335*4882a593Smuzhiyun spin_lock(&up->port.lock);
336*4882a593Smuzhiyun *status = disr;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
transmit_chars(struct uart_txx9_port * up)339*4882a593Smuzhiyun static inline void transmit_chars(struct uart_txx9_port *up)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun struct circ_buf *xmit = &up->port.state->xmit;
342*4882a593Smuzhiyun int count;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun if (up->port.x_char) {
345*4882a593Smuzhiyun sio_out(up, TXX9_SITFIFO, up->port.x_char);
346*4882a593Smuzhiyun up->port.icount.tx++;
347*4882a593Smuzhiyun up->port.x_char = 0;
348*4882a593Smuzhiyun return;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
351*4882a593Smuzhiyun serial_txx9_stop_tx(&up->port);
352*4882a593Smuzhiyun return;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun count = TXX9_SIO_TX_FIFO;
356*4882a593Smuzhiyun do {
357*4882a593Smuzhiyun sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
358*4882a593Smuzhiyun xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
359*4882a593Smuzhiyun up->port.icount.tx++;
360*4882a593Smuzhiyun if (uart_circ_empty(xmit))
361*4882a593Smuzhiyun break;
362*4882a593Smuzhiyun } while (--count > 0);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
365*4882a593Smuzhiyun uart_write_wakeup(&up->port);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun if (uart_circ_empty(xmit))
368*4882a593Smuzhiyun serial_txx9_stop_tx(&up->port);
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
serial_txx9_interrupt(int irq,void * dev_id)371*4882a593Smuzhiyun static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun int pass_counter = 0;
374*4882a593Smuzhiyun struct uart_txx9_port *up = dev_id;
375*4882a593Smuzhiyun unsigned int status;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun while (1) {
378*4882a593Smuzhiyun spin_lock(&up->port.lock);
379*4882a593Smuzhiyun status = sio_in(up, TXX9_SIDISR);
380*4882a593Smuzhiyun if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
381*4882a593Smuzhiyun status &= ~TXX9_SIDISR_TDIS;
382*4882a593Smuzhiyun if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
383*4882a593Smuzhiyun TXX9_SIDISR_TOUT))) {
384*4882a593Smuzhiyun spin_unlock(&up->port.lock);
385*4882a593Smuzhiyun break;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (status & TXX9_SIDISR_RDIS)
389*4882a593Smuzhiyun receive_chars(up, &status);
390*4882a593Smuzhiyun if (status & TXX9_SIDISR_TDIS)
391*4882a593Smuzhiyun transmit_chars(up);
392*4882a593Smuzhiyun /* Clear TX/RX Int. Status */
393*4882a593Smuzhiyun sio_mask(up, TXX9_SIDISR,
394*4882a593Smuzhiyun TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
395*4882a593Smuzhiyun TXX9_SIDISR_TOUT);
396*4882a593Smuzhiyun spin_unlock(&up->port.lock);
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun if (pass_counter++ > PASS_LIMIT)
399*4882a593Smuzhiyun break;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun return pass_counter ? IRQ_HANDLED : IRQ_NONE;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun
serial_txx9_tx_empty(struct uart_port * port)405*4882a593Smuzhiyun static unsigned int serial_txx9_tx_empty(struct uart_port *port)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
408*4882a593Smuzhiyun unsigned long flags;
409*4882a593Smuzhiyun unsigned int ret;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
412*4882a593Smuzhiyun ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
413*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun return ret;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
serial_txx9_get_mctrl(struct uart_port * port)418*4882a593Smuzhiyun static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
421*4882a593Smuzhiyun unsigned int ret;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun /* no modem control lines */
424*4882a593Smuzhiyun ret = TIOCM_CAR | TIOCM_DSR;
425*4882a593Smuzhiyun ret |= (sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS;
426*4882a593Smuzhiyun ret |= (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun return ret;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
serial_txx9_set_mctrl(struct uart_port * port,unsigned int mctrl)431*4882a593Smuzhiyun static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun if (mctrl & TIOCM_RTS)
436*4882a593Smuzhiyun sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
437*4882a593Smuzhiyun else
438*4882a593Smuzhiyun sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
serial_txx9_break_ctl(struct uart_port * port,int break_state)441*4882a593Smuzhiyun static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
444*4882a593Smuzhiyun unsigned long flags;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
447*4882a593Smuzhiyun if (break_state == -1)
448*4882a593Smuzhiyun sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
449*4882a593Smuzhiyun else
450*4882a593Smuzhiyun sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
451*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun #if defined(CONFIG_SERIAL_TXX9_CONSOLE) || defined(CONFIG_CONSOLE_POLL)
455*4882a593Smuzhiyun /*
456*4882a593Smuzhiyun * Wait for transmitter & holding register to empty
457*4882a593Smuzhiyun */
wait_for_xmitr(struct uart_txx9_port * up)458*4882a593Smuzhiyun static void wait_for_xmitr(struct uart_txx9_port *up)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun unsigned int tmout = 10000;
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /* Wait up to 10ms for the character(s) to be sent. */
463*4882a593Smuzhiyun while (--tmout &&
464*4882a593Smuzhiyun !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
465*4882a593Smuzhiyun udelay(1);
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun /* Wait up to 1s for flow control if necessary */
468*4882a593Smuzhiyun if (up->port.flags & UPF_CONS_FLOW) {
469*4882a593Smuzhiyun tmout = 1000000;
470*4882a593Smuzhiyun while (--tmout &&
471*4882a593Smuzhiyun (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
472*4882a593Smuzhiyun udelay(1);
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun #endif
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun #ifdef CONFIG_CONSOLE_POLL
478*4882a593Smuzhiyun /*
479*4882a593Smuzhiyun * Console polling routines for writing and reading from the uart while
480*4882a593Smuzhiyun * in an interrupt or debug context.
481*4882a593Smuzhiyun */
482*4882a593Smuzhiyun
serial_txx9_get_poll_char(struct uart_port * port)483*4882a593Smuzhiyun static int serial_txx9_get_poll_char(struct uart_port *port)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun unsigned int ier;
486*4882a593Smuzhiyun unsigned char c;
487*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun /*
490*4882a593Smuzhiyun * First save the IER then disable the interrupts
491*4882a593Smuzhiyun */
492*4882a593Smuzhiyun ier = sio_in(up, TXX9_SIDICR);
493*4882a593Smuzhiyun sio_out(up, TXX9_SIDICR, 0);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun while (sio_in(up, TXX9_SIDISR) & TXX9_SIDISR_UVALID)
496*4882a593Smuzhiyun ;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun c = sio_in(up, TXX9_SIRFIFO);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun /*
501*4882a593Smuzhiyun * Finally, clear RX interrupt status
502*4882a593Smuzhiyun * and restore the IER
503*4882a593Smuzhiyun */
504*4882a593Smuzhiyun sio_mask(up, TXX9_SIDISR, TXX9_SIDISR_RDIS);
505*4882a593Smuzhiyun sio_out(up, TXX9_SIDICR, ier);
506*4882a593Smuzhiyun return c;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun
serial_txx9_put_poll_char(struct uart_port * port,unsigned char c)510*4882a593Smuzhiyun static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c)
511*4882a593Smuzhiyun {
512*4882a593Smuzhiyun unsigned int ier;
513*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun /*
516*4882a593Smuzhiyun * First save the IER then disable the interrupts
517*4882a593Smuzhiyun */
518*4882a593Smuzhiyun ier = sio_in(up, TXX9_SIDICR);
519*4882a593Smuzhiyun sio_out(up, TXX9_SIDICR, 0);
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun wait_for_xmitr(up);
522*4882a593Smuzhiyun /*
523*4882a593Smuzhiyun * Send the character out.
524*4882a593Smuzhiyun */
525*4882a593Smuzhiyun sio_out(up, TXX9_SITFIFO, c);
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun /*
528*4882a593Smuzhiyun * Finally, wait for transmitter to become empty
529*4882a593Smuzhiyun * and restore the IER
530*4882a593Smuzhiyun */
531*4882a593Smuzhiyun wait_for_xmitr(up);
532*4882a593Smuzhiyun sio_out(up, TXX9_SIDICR, ier);
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun #endif /* CONFIG_CONSOLE_POLL */
536*4882a593Smuzhiyun
serial_txx9_startup(struct uart_port * port)537*4882a593Smuzhiyun static int serial_txx9_startup(struct uart_port *port)
538*4882a593Smuzhiyun {
539*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
540*4882a593Smuzhiyun unsigned long flags;
541*4882a593Smuzhiyun int retval;
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun /*
544*4882a593Smuzhiyun * Clear the FIFO buffers and disable them.
545*4882a593Smuzhiyun * (they will be reenabled in set_termios())
546*4882a593Smuzhiyun */
547*4882a593Smuzhiyun sio_set(up, TXX9_SIFCR,
548*4882a593Smuzhiyun TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
549*4882a593Smuzhiyun /* clear reset */
550*4882a593Smuzhiyun sio_mask(up, TXX9_SIFCR,
551*4882a593Smuzhiyun TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
552*4882a593Smuzhiyun sio_out(up, TXX9_SIDICR, 0);
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun /*
555*4882a593Smuzhiyun * Clear the interrupt registers.
556*4882a593Smuzhiyun */
557*4882a593Smuzhiyun sio_out(up, TXX9_SIDISR, 0);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun retval = request_irq(up->port.irq, serial_txx9_interrupt,
560*4882a593Smuzhiyun IRQF_SHARED, "serial_txx9", up);
561*4882a593Smuzhiyun if (retval)
562*4882a593Smuzhiyun return retval;
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun /*
565*4882a593Smuzhiyun * Now, initialize the UART
566*4882a593Smuzhiyun */
567*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
568*4882a593Smuzhiyun serial_txx9_set_mctrl(&up->port, up->port.mctrl);
569*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun /* Enable RX/TX */
572*4882a593Smuzhiyun sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun /*
575*4882a593Smuzhiyun * Finally, enable interrupts.
576*4882a593Smuzhiyun */
577*4882a593Smuzhiyun sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun return 0;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
serial_txx9_shutdown(struct uart_port * port)582*4882a593Smuzhiyun static void serial_txx9_shutdown(struct uart_port *port)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
585*4882a593Smuzhiyun unsigned long flags;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun /*
588*4882a593Smuzhiyun * Disable interrupts from this port
589*4882a593Smuzhiyun */
590*4882a593Smuzhiyun sio_out(up, TXX9_SIDICR, 0); /* disable all intrs */
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
593*4882a593Smuzhiyun serial_txx9_set_mctrl(&up->port, up->port.mctrl);
594*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun /*
597*4882a593Smuzhiyun * Disable break condition
598*4882a593Smuzhiyun */
599*4882a593Smuzhiyun sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_TXX9_CONSOLE
602*4882a593Smuzhiyun if (up->port.cons && up->port.line == up->port.cons->index) {
603*4882a593Smuzhiyun free_irq(up->port.irq, up);
604*4882a593Smuzhiyun return;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun #endif
607*4882a593Smuzhiyun /* reset FIFOs */
608*4882a593Smuzhiyun sio_set(up, TXX9_SIFCR,
609*4882a593Smuzhiyun TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
610*4882a593Smuzhiyun /* clear reset */
611*4882a593Smuzhiyun sio_mask(up, TXX9_SIFCR,
612*4882a593Smuzhiyun TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun /* Disable RX/TX */
615*4882a593Smuzhiyun sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun free_irq(up->port.irq, up);
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun static void
serial_txx9_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)621*4882a593Smuzhiyun serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios,
622*4882a593Smuzhiyun struct ktermios *old)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
625*4882a593Smuzhiyun unsigned int cval, fcr = 0;
626*4882a593Smuzhiyun unsigned long flags;
627*4882a593Smuzhiyun unsigned int baud, quot;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun /*
630*4882a593Smuzhiyun * We don't support modem control lines.
631*4882a593Smuzhiyun */
632*4882a593Smuzhiyun termios->c_cflag &= ~(HUPCL | CMSPAR);
633*4882a593Smuzhiyun termios->c_cflag |= CLOCAL;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun cval = sio_in(up, TXX9_SILCR);
636*4882a593Smuzhiyun /* byte size and parity */
637*4882a593Smuzhiyun cval &= ~TXX9_SILCR_UMODE_MASK;
638*4882a593Smuzhiyun switch (termios->c_cflag & CSIZE) {
639*4882a593Smuzhiyun case CS7:
640*4882a593Smuzhiyun cval |= TXX9_SILCR_UMODE_7BIT;
641*4882a593Smuzhiyun break;
642*4882a593Smuzhiyun default:
643*4882a593Smuzhiyun case CS5: /* not supported */
644*4882a593Smuzhiyun case CS6: /* not supported */
645*4882a593Smuzhiyun case CS8:
646*4882a593Smuzhiyun cval |= TXX9_SILCR_UMODE_8BIT;
647*4882a593Smuzhiyun termios->c_cflag &= ~CSIZE;
648*4882a593Smuzhiyun termios->c_cflag |= CS8;
649*4882a593Smuzhiyun break;
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun cval &= ~TXX9_SILCR_USBL_MASK;
653*4882a593Smuzhiyun if (termios->c_cflag & CSTOPB)
654*4882a593Smuzhiyun cval |= TXX9_SILCR_USBL_2BIT;
655*4882a593Smuzhiyun else
656*4882a593Smuzhiyun cval |= TXX9_SILCR_USBL_1BIT;
657*4882a593Smuzhiyun cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
658*4882a593Smuzhiyun if (termios->c_cflag & PARENB)
659*4882a593Smuzhiyun cval |= TXX9_SILCR_UPEN;
660*4882a593Smuzhiyun if (!(termios->c_cflag & PARODD))
661*4882a593Smuzhiyun cval |= TXX9_SILCR_UEPS;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun /*
664*4882a593Smuzhiyun * Ask the core to calculate the divisor for us.
665*4882a593Smuzhiyun */
666*4882a593Smuzhiyun baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
667*4882a593Smuzhiyun quot = uart_get_divisor(port, baud);
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun /* Set up FIFOs */
670*4882a593Smuzhiyun /* TX Int by FIFO Empty, RX Int by Receiving 1 char. */
671*4882a593Smuzhiyun fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun /*
674*4882a593Smuzhiyun * Ok, we're now changing the port state. Do it with
675*4882a593Smuzhiyun * interrupts disabled.
676*4882a593Smuzhiyun */
677*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun /*
680*4882a593Smuzhiyun * Update the per-port timeout.
681*4882a593Smuzhiyun */
682*4882a593Smuzhiyun uart_update_timeout(port, termios->c_cflag, baud);
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun up->port.read_status_mask = TXX9_SIDISR_UOER |
685*4882a593Smuzhiyun TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
686*4882a593Smuzhiyun if (termios->c_iflag & INPCK)
687*4882a593Smuzhiyun up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
688*4882a593Smuzhiyun if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
689*4882a593Smuzhiyun up->port.read_status_mask |= TXX9_SIDISR_UBRK;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun /*
692*4882a593Smuzhiyun * Characteres to ignore
693*4882a593Smuzhiyun */
694*4882a593Smuzhiyun up->port.ignore_status_mask = 0;
695*4882a593Smuzhiyun if (termios->c_iflag & IGNPAR)
696*4882a593Smuzhiyun up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
697*4882a593Smuzhiyun if (termios->c_iflag & IGNBRK) {
698*4882a593Smuzhiyun up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
699*4882a593Smuzhiyun /*
700*4882a593Smuzhiyun * If we're ignoring parity and break indicators,
701*4882a593Smuzhiyun * ignore overruns too (for real raw support).
702*4882a593Smuzhiyun */
703*4882a593Smuzhiyun if (termios->c_iflag & IGNPAR)
704*4882a593Smuzhiyun up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
705*4882a593Smuzhiyun }
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun /*
708*4882a593Smuzhiyun * ignore all characters if CREAD is not set
709*4882a593Smuzhiyun */
710*4882a593Smuzhiyun if ((termios->c_cflag & CREAD) == 0)
711*4882a593Smuzhiyun up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun /* CTS flow control flag */
714*4882a593Smuzhiyun if ((termios->c_cflag & CRTSCTS) &&
715*4882a593Smuzhiyun (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
716*4882a593Smuzhiyun sio_set(up, TXX9_SIFLCR,
717*4882a593Smuzhiyun TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
718*4882a593Smuzhiyun } else {
719*4882a593Smuzhiyun sio_mask(up, TXX9_SIFLCR,
720*4882a593Smuzhiyun TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun sio_out(up, TXX9_SILCR, cval);
724*4882a593Smuzhiyun sio_quot_set(up, quot);
725*4882a593Smuzhiyun sio_out(up, TXX9_SIFCR, fcr);
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun serial_txx9_set_mctrl(&up->port, up->port.mctrl);
728*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun static void
serial_txx9_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)732*4882a593Smuzhiyun serial_txx9_pm(struct uart_port *port, unsigned int state,
733*4882a593Smuzhiyun unsigned int oldstate)
734*4882a593Smuzhiyun {
735*4882a593Smuzhiyun /*
736*4882a593Smuzhiyun * If oldstate was -1 this is called from
737*4882a593Smuzhiyun * uart_configure_port(). In this case do not initialize the
738*4882a593Smuzhiyun * port now, because the port was already initialized (for
739*4882a593Smuzhiyun * non-console port) or should not be initialized here (for
740*4882a593Smuzhiyun * console port). If we initialized the port here we lose
741*4882a593Smuzhiyun * serial console settings.
742*4882a593Smuzhiyun */
743*4882a593Smuzhiyun if (state == 0 && oldstate != -1)
744*4882a593Smuzhiyun serial_txx9_initialize(port);
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun
serial_txx9_request_resource(struct uart_txx9_port * up)747*4882a593Smuzhiyun static int serial_txx9_request_resource(struct uart_txx9_port *up)
748*4882a593Smuzhiyun {
749*4882a593Smuzhiyun unsigned int size = TXX9_REGION_SIZE;
750*4882a593Smuzhiyun int ret = 0;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun switch (up->port.iotype) {
753*4882a593Smuzhiyun default:
754*4882a593Smuzhiyun if (!up->port.mapbase)
755*4882a593Smuzhiyun break;
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
758*4882a593Smuzhiyun ret = -EBUSY;
759*4882a593Smuzhiyun break;
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun if (up->port.flags & UPF_IOREMAP) {
763*4882a593Smuzhiyun up->port.membase = ioremap(up->port.mapbase, size);
764*4882a593Smuzhiyun if (!up->port.membase) {
765*4882a593Smuzhiyun release_mem_region(up->port.mapbase, size);
766*4882a593Smuzhiyun ret = -ENOMEM;
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun }
769*4882a593Smuzhiyun break;
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun case UPIO_PORT:
772*4882a593Smuzhiyun if (!request_region(up->port.iobase, size, "serial_txx9"))
773*4882a593Smuzhiyun ret = -EBUSY;
774*4882a593Smuzhiyun break;
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun return ret;
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun
serial_txx9_release_resource(struct uart_txx9_port * up)779*4882a593Smuzhiyun static void serial_txx9_release_resource(struct uart_txx9_port *up)
780*4882a593Smuzhiyun {
781*4882a593Smuzhiyun unsigned int size = TXX9_REGION_SIZE;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun switch (up->port.iotype) {
784*4882a593Smuzhiyun default:
785*4882a593Smuzhiyun if (!up->port.mapbase)
786*4882a593Smuzhiyun break;
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun if (up->port.flags & UPF_IOREMAP) {
789*4882a593Smuzhiyun iounmap(up->port.membase);
790*4882a593Smuzhiyun up->port.membase = NULL;
791*4882a593Smuzhiyun }
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun release_mem_region(up->port.mapbase, size);
794*4882a593Smuzhiyun break;
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun case UPIO_PORT:
797*4882a593Smuzhiyun release_region(up->port.iobase, size);
798*4882a593Smuzhiyun break;
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun
serial_txx9_release_port(struct uart_port * port)802*4882a593Smuzhiyun static void serial_txx9_release_port(struct uart_port *port)
803*4882a593Smuzhiyun {
804*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
805*4882a593Smuzhiyun serial_txx9_release_resource(up);
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun
serial_txx9_request_port(struct uart_port * port)808*4882a593Smuzhiyun static int serial_txx9_request_port(struct uart_port *port)
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
811*4882a593Smuzhiyun return serial_txx9_request_resource(up);
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun
serial_txx9_config_port(struct uart_port * port,int uflags)814*4882a593Smuzhiyun static void serial_txx9_config_port(struct uart_port *port, int uflags)
815*4882a593Smuzhiyun {
816*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
817*4882a593Smuzhiyun int ret;
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun /*
820*4882a593Smuzhiyun * Find the region that we can probe for. This in turn
821*4882a593Smuzhiyun * tells us whether we can probe for the type of port.
822*4882a593Smuzhiyun */
823*4882a593Smuzhiyun ret = serial_txx9_request_resource(up);
824*4882a593Smuzhiyun if (ret < 0)
825*4882a593Smuzhiyun return;
826*4882a593Smuzhiyun port->type = PORT_TXX9;
827*4882a593Smuzhiyun up->port.fifosize = TXX9_SIO_TX_FIFO;
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_TXX9_CONSOLE
830*4882a593Smuzhiyun if (up->port.line == up->port.cons->index)
831*4882a593Smuzhiyun return;
832*4882a593Smuzhiyun #endif
833*4882a593Smuzhiyun serial_txx9_initialize(port);
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun static const char *
serial_txx9_type(struct uart_port * port)837*4882a593Smuzhiyun serial_txx9_type(struct uart_port *port)
838*4882a593Smuzhiyun {
839*4882a593Smuzhiyun return "txx9";
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun static const struct uart_ops serial_txx9_pops = {
843*4882a593Smuzhiyun .tx_empty = serial_txx9_tx_empty,
844*4882a593Smuzhiyun .set_mctrl = serial_txx9_set_mctrl,
845*4882a593Smuzhiyun .get_mctrl = serial_txx9_get_mctrl,
846*4882a593Smuzhiyun .stop_tx = serial_txx9_stop_tx,
847*4882a593Smuzhiyun .start_tx = serial_txx9_start_tx,
848*4882a593Smuzhiyun .stop_rx = serial_txx9_stop_rx,
849*4882a593Smuzhiyun .break_ctl = serial_txx9_break_ctl,
850*4882a593Smuzhiyun .startup = serial_txx9_startup,
851*4882a593Smuzhiyun .shutdown = serial_txx9_shutdown,
852*4882a593Smuzhiyun .set_termios = serial_txx9_set_termios,
853*4882a593Smuzhiyun .pm = serial_txx9_pm,
854*4882a593Smuzhiyun .type = serial_txx9_type,
855*4882a593Smuzhiyun .release_port = serial_txx9_release_port,
856*4882a593Smuzhiyun .request_port = serial_txx9_request_port,
857*4882a593Smuzhiyun .config_port = serial_txx9_config_port,
858*4882a593Smuzhiyun #ifdef CONFIG_CONSOLE_POLL
859*4882a593Smuzhiyun .poll_get_char = serial_txx9_get_poll_char,
860*4882a593Smuzhiyun .poll_put_char = serial_txx9_put_poll_char,
861*4882a593Smuzhiyun #endif
862*4882a593Smuzhiyun };
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun static struct uart_txx9_port serial_txx9_ports[UART_NR];
865*4882a593Smuzhiyun
serial_txx9_register_ports(struct uart_driver * drv,struct device * dev)866*4882a593Smuzhiyun static void __init serial_txx9_register_ports(struct uart_driver *drv,
867*4882a593Smuzhiyun struct device *dev)
868*4882a593Smuzhiyun {
869*4882a593Smuzhiyun int i;
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun for (i = 0; i < UART_NR; i++) {
872*4882a593Smuzhiyun struct uart_txx9_port *up = &serial_txx9_ports[i];
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun up->port.line = i;
875*4882a593Smuzhiyun up->port.ops = &serial_txx9_pops;
876*4882a593Smuzhiyun up->port.dev = dev;
877*4882a593Smuzhiyun if (up->port.iobase || up->port.mapbase)
878*4882a593Smuzhiyun uart_add_one_port(drv, &up->port);
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun }
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_TXX9_CONSOLE
883*4882a593Smuzhiyun
serial_txx9_console_putchar(struct uart_port * port,int ch)884*4882a593Smuzhiyun static void serial_txx9_console_putchar(struct uart_port *port, int ch)
885*4882a593Smuzhiyun {
886*4882a593Smuzhiyun struct uart_txx9_port *up = to_uart_txx9_port(port);
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun wait_for_xmitr(up);
889*4882a593Smuzhiyun sio_out(up, TXX9_SITFIFO, ch);
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun /*
893*4882a593Smuzhiyun * Print a string to the serial port trying not to disturb
894*4882a593Smuzhiyun * any possible real use of the port...
895*4882a593Smuzhiyun *
896*4882a593Smuzhiyun * The console_lock must be held when we get here.
897*4882a593Smuzhiyun */
898*4882a593Smuzhiyun static void
serial_txx9_console_write(struct console * co,const char * s,unsigned int count)899*4882a593Smuzhiyun serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
900*4882a593Smuzhiyun {
901*4882a593Smuzhiyun struct uart_txx9_port *up = &serial_txx9_ports[co->index];
902*4882a593Smuzhiyun unsigned int ier, flcr;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun /*
905*4882a593Smuzhiyun * First save the UER then disable the interrupts
906*4882a593Smuzhiyun */
907*4882a593Smuzhiyun ier = sio_in(up, TXX9_SIDICR);
908*4882a593Smuzhiyun sio_out(up, TXX9_SIDICR, 0);
909*4882a593Smuzhiyun /*
910*4882a593Smuzhiyun * Disable flow-control if enabled (and unnecessary)
911*4882a593Smuzhiyun */
912*4882a593Smuzhiyun flcr = sio_in(up, TXX9_SIFLCR);
913*4882a593Smuzhiyun if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
914*4882a593Smuzhiyun sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun uart_console_write(&up->port, s, count, serial_txx9_console_putchar);
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun /*
919*4882a593Smuzhiyun * Finally, wait for transmitter to become empty
920*4882a593Smuzhiyun * and restore the IER
921*4882a593Smuzhiyun */
922*4882a593Smuzhiyun wait_for_xmitr(up);
923*4882a593Smuzhiyun sio_out(up, TXX9_SIFLCR, flcr);
924*4882a593Smuzhiyun sio_out(up, TXX9_SIDICR, ier);
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun
serial_txx9_console_setup(struct console * co,char * options)927*4882a593Smuzhiyun static int __init serial_txx9_console_setup(struct console *co, char *options)
928*4882a593Smuzhiyun {
929*4882a593Smuzhiyun struct uart_port *port;
930*4882a593Smuzhiyun struct uart_txx9_port *up;
931*4882a593Smuzhiyun int baud = 9600;
932*4882a593Smuzhiyun int bits = 8;
933*4882a593Smuzhiyun int parity = 'n';
934*4882a593Smuzhiyun int flow = 'n';
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun /*
937*4882a593Smuzhiyun * Check whether an invalid uart number has been specified, and
938*4882a593Smuzhiyun * if so, search for the first available port that does have
939*4882a593Smuzhiyun * console support.
940*4882a593Smuzhiyun */
941*4882a593Smuzhiyun if (co->index >= UART_NR)
942*4882a593Smuzhiyun co->index = 0;
943*4882a593Smuzhiyun up = &serial_txx9_ports[co->index];
944*4882a593Smuzhiyun port = &up->port;
945*4882a593Smuzhiyun if (!port->ops)
946*4882a593Smuzhiyun return -ENODEV;
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun serial_txx9_initialize(&up->port);
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun if (options)
951*4882a593Smuzhiyun uart_parse_options(options, &baud, &parity, &bits, &flow);
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun return uart_set_options(port, co, baud, parity, bits, flow);
954*4882a593Smuzhiyun }
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun static struct uart_driver serial_txx9_reg;
957*4882a593Smuzhiyun static struct console serial_txx9_console = {
958*4882a593Smuzhiyun .name = TXX9_TTY_NAME,
959*4882a593Smuzhiyun .write = serial_txx9_console_write,
960*4882a593Smuzhiyun .device = uart_console_device,
961*4882a593Smuzhiyun .setup = serial_txx9_console_setup,
962*4882a593Smuzhiyun .flags = CON_PRINTBUFFER,
963*4882a593Smuzhiyun .index = -1,
964*4882a593Smuzhiyun .data = &serial_txx9_reg,
965*4882a593Smuzhiyun };
966*4882a593Smuzhiyun
serial_txx9_console_init(void)967*4882a593Smuzhiyun static int __init serial_txx9_console_init(void)
968*4882a593Smuzhiyun {
969*4882a593Smuzhiyun register_console(&serial_txx9_console);
970*4882a593Smuzhiyun return 0;
971*4882a593Smuzhiyun }
972*4882a593Smuzhiyun console_initcall(serial_txx9_console_init);
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun #define SERIAL_TXX9_CONSOLE &serial_txx9_console
975*4882a593Smuzhiyun #else
976*4882a593Smuzhiyun #define SERIAL_TXX9_CONSOLE NULL
977*4882a593Smuzhiyun #endif
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun static struct uart_driver serial_txx9_reg = {
980*4882a593Smuzhiyun .owner = THIS_MODULE,
981*4882a593Smuzhiyun .driver_name = "serial_txx9",
982*4882a593Smuzhiyun .dev_name = TXX9_TTY_NAME,
983*4882a593Smuzhiyun .major = TXX9_TTY_MAJOR,
984*4882a593Smuzhiyun .minor = TXX9_TTY_MINOR_START,
985*4882a593Smuzhiyun .nr = UART_NR,
986*4882a593Smuzhiyun .cons = SERIAL_TXX9_CONSOLE,
987*4882a593Smuzhiyun };
988*4882a593Smuzhiyun
early_serial_txx9_setup(struct uart_port * port)989*4882a593Smuzhiyun int __init early_serial_txx9_setup(struct uart_port *port)
990*4882a593Smuzhiyun {
991*4882a593Smuzhiyun if (port->line >= ARRAY_SIZE(serial_txx9_ports))
992*4882a593Smuzhiyun return -ENODEV;
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun serial_txx9_ports[port->line].port = *port;
995*4882a593Smuzhiyun serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
996*4882a593Smuzhiyun serial_txx9_ports[port->line].port.flags |=
997*4882a593Smuzhiyun UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
998*4882a593Smuzhiyun return 0;
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun static DEFINE_MUTEX(serial_txx9_mutex);
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun /**
1004*4882a593Smuzhiyun * serial_txx9_register_port - register a serial port
1005*4882a593Smuzhiyun * @port: serial port template
1006*4882a593Smuzhiyun *
1007*4882a593Smuzhiyun * Configure the serial port specified by the request.
1008*4882a593Smuzhiyun *
1009*4882a593Smuzhiyun * The port is then probed and if necessary the IRQ is autodetected
1010*4882a593Smuzhiyun * If this fails an error is returned.
1011*4882a593Smuzhiyun *
1012*4882a593Smuzhiyun * On success the port is ready to use and the line number is returned.
1013*4882a593Smuzhiyun */
serial_txx9_register_port(struct uart_port * port)1014*4882a593Smuzhiyun static int serial_txx9_register_port(struct uart_port *port)
1015*4882a593Smuzhiyun {
1016*4882a593Smuzhiyun int i;
1017*4882a593Smuzhiyun struct uart_txx9_port *uart;
1018*4882a593Smuzhiyun int ret = -ENOSPC;
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun mutex_lock(&serial_txx9_mutex);
1021*4882a593Smuzhiyun for (i = 0; i < UART_NR; i++) {
1022*4882a593Smuzhiyun uart = &serial_txx9_ports[i];
1023*4882a593Smuzhiyun if (uart_match_port(&uart->port, port)) {
1024*4882a593Smuzhiyun uart_remove_one_port(&serial_txx9_reg, &uart->port);
1025*4882a593Smuzhiyun break;
1026*4882a593Smuzhiyun }
1027*4882a593Smuzhiyun }
1028*4882a593Smuzhiyun if (i == UART_NR) {
1029*4882a593Smuzhiyun /* Find unused port */
1030*4882a593Smuzhiyun for (i = 0; i < UART_NR; i++) {
1031*4882a593Smuzhiyun uart = &serial_txx9_ports[i];
1032*4882a593Smuzhiyun if (!(uart->port.iobase || uart->port.mapbase))
1033*4882a593Smuzhiyun break;
1034*4882a593Smuzhiyun }
1035*4882a593Smuzhiyun }
1036*4882a593Smuzhiyun if (i < UART_NR) {
1037*4882a593Smuzhiyun uart->port.iobase = port->iobase;
1038*4882a593Smuzhiyun uart->port.membase = port->membase;
1039*4882a593Smuzhiyun uart->port.irq = port->irq;
1040*4882a593Smuzhiyun uart->port.uartclk = port->uartclk;
1041*4882a593Smuzhiyun uart->port.iotype = port->iotype;
1042*4882a593Smuzhiyun uart->port.flags = port->flags
1043*4882a593Smuzhiyun | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1044*4882a593Smuzhiyun uart->port.mapbase = port->mapbase;
1045*4882a593Smuzhiyun if (port->dev)
1046*4882a593Smuzhiyun uart->port.dev = port->dev;
1047*4882a593Smuzhiyun ret = uart_add_one_port(&serial_txx9_reg, &uart->port);
1048*4882a593Smuzhiyun if (ret == 0)
1049*4882a593Smuzhiyun ret = uart->port.line;
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun mutex_unlock(&serial_txx9_mutex);
1052*4882a593Smuzhiyun return ret;
1053*4882a593Smuzhiyun }
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun /**
1056*4882a593Smuzhiyun * serial_txx9_unregister_port - remove a txx9 serial port at runtime
1057*4882a593Smuzhiyun * @line: serial line number
1058*4882a593Smuzhiyun *
1059*4882a593Smuzhiyun * Remove one serial port. This may not be called from interrupt
1060*4882a593Smuzhiyun * context. We hand the port back to the our control.
1061*4882a593Smuzhiyun */
serial_txx9_unregister_port(int line)1062*4882a593Smuzhiyun static void serial_txx9_unregister_port(int line)
1063*4882a593Smuzhiyun {
1064*4882a593Smuzhiyun struct uart_txx9_port *uart = &serial_txx9_ports[line];
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun mutex_lock(&serial_txx9_mutex);
1067*4882a593Smuzhiyun uart_remove_one_port(&serial_txx9_reg, &uart->port);
1068*4882a593Smuzhiyun uart->port.flags = 0;
1069*4882a593Smuzhiyun uart->port.type = PORT_UNKNOWN;
1070*4882a593Smuzhiyun uart->port.iobase = 0;
1071*4882a593Smuzhiyun uart->port.mapbase = 0;
1072*4882a593Smuzhiyun uart->port.membase = NULL;
1073*4882a593Smuzhiyun uart->port.dev = NULL;
1074*4882a593Smuzhiyun mutex_unlock(&serial_txx9_mutex);
1075*4882a593Smuzhiyun }
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun /*
1078*4882a593Smuzhiyun * Register a set of serial devices attached to a platform device.
1079*4882a593Smuzhiyun */
serial_txx9_probe(struct platform_device * dev)1080*4882a593Smuzhiyun static int serial_txx9_probe(struct platform_device *dev)
1081*4882a593Smuzhiyun {
1082*4882a593Smuzhiyun struct uart_port *p = dev_get_platdata(&dev->dev);
1083*4882a593Smuzhiyun struct uart_port port;
1084*4882a593Smuzhiyun int ret, i;
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun memset(&port, 0, sizeof(struct uart_port));
1087*4882a593Smuzhiyun for (i = 0; p && p->uartclk != 0; p++, i++) {
1088*4882a593Smuzhiyun port.iobase = p->iobase;
1089*4882a593Smuzhiyun port.membase = p->membase;
1090*4882a593Smuzhiyun port.irq = p->irq;
1091*4882a593Smuzhiyun port.uartclk = p->uartclk;
1092*4882a593Smuzhiyun port.iotype = p->iotype;
1093*4882a593Smuzhiyun port.flags = p->flags;
1094*4882a593Smuzhiyun port.mapbase = p->mapbase;
1095*4882a593Smuzhiyun port.dev = &dev->dev;
1096*4882a593Smuzhiyun port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_TXX9_CONSOLE);
1097*4882a593Smuzhiyun ret = serial_txx9_register_port(&port);
1098*4882a593Smuzhiyun if (ret < 0) {
1099*4882a593Smuzhiyun dev_err(&dev->dev, "unable to register port at index %d "
1100*4882a593Smuzhiyun "(IO%lx MEM%llx IRQ%d): %d\n", i,
1101*4882a593Smuzhiyun p->iobase, (unsigned long long)p->mapbase,
1102*4882a593Smuzhiyun p->irq, ret);
1103*4882a593Smuzhiyun }
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun return 0;
1106*4882a593Smuzhiyun }
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun /*
1109*4882a593Smuzhiyun * Remove serial ports registered against a platform device.
1110*4882a593Smuzhiyun */
serial_txx9_remove(struct platform_device * dev)1111*4882a593Smuzhiyun static int serial_txx9_remove(struct platform_device *dev)
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun int i;
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun for (i = 0; i < UART_NR; i++) {
1116*4882a593Smuzhiyun struct uart_txx9_port *up = &serial_txx9_ports[i];
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun if (up->port.dev == &dev->dev)
1119*4882a593Smuzhiyun serial_txx9_unregister_port(i);
1120*4882a593Smuzhiyun }
1121*4882a593Smuzhiyun return 0;
1122*4882a593Smuzhiyun }
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun #ifdef CONFIG_PM
serial_txx9_suspend(struct platform_device * dev,pm_message_t state)1125*4882a593Smuzhiyun static int serial_txx9_suspend(struct platform_device *dev, pm_message_t state)
1126*4882a593Smuzhiyun {
1127*4882a593Smuzhiyun int i;
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun for (i = 0; i < UART_NR; i++) {
1130*4882a593Smuzhiyun struct uart_txx9_port *up = &serial_txx9_ports[i];
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1133*4882a593Smuzhiyun uart_suspend_port(&serial_txx9_reg, &up->port);
1134*4882a593Smuzhiyun }
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun return 0;
1137*4882a593Smuzhiyun }
1138*4882a593Smuzhiyun
serial_txx9_resume(struct platform_device * dev)1139*4882a593Smuzhiyun static int serial_txx9_resume(struct platform_device *dev)
1140*4882a593Smuzhiyun {
1141*4882a593Smuzhiyun int i;
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun for (i = 0; i < UART_NR; i++) {
1144*4882a593Smuzhiyun struct uart_txx9_port *up = &serial_txx9_ports[i];
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1147*4882a593Smuzhiyun uart_resume_port(&serial_txx9_reg, &up->port);
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun return 0;
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun #endif
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun static struct platform_driver serial_txx9_plat_driver = {
1155*4882a593Smuzhiyun .probe = serial_txx9_probe,
1156*4882a593Smuzhiyun .remove = serial_txx9_remove,
1157*4882a593Smuzhiyun #ifdef CONFIG_PM
1158*4882a593Smuzhiyun .suspend = serial_txx9_suspend,
1159*4882a593Smuzhiyun .resume = serial_txx9_resume,
1160*4882a593Smuzhiyun #endif
1161*4882a593Smuzhiyun .driver = {
1162*4882a593Smuzhiyun .name = "serial_txx9",
1163*4882a593Smuzhiyun },
1164*4882a593Smuzhiyun };
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun #ifdef ENABLE_SERIAL_TXX9_PCI
1167*4882a593Smuzhiyun /*
1168*4882a593Smuzhiyun * Probe one serial board. Unfortunately, there is no rhyme nor reason
1169*4882a593Smuzhiyun * to the arrangement of serial ports on a PCI card.
1170*4882a593Smuzhiyun */
1171*4882a593Smuzhiyun static int
pciserial_txx9_init_one(struct pci_dev * dev,const struct pci_device_id * ent)1172*4882a593Smuzhiyun pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1173*4882a593Smuzhiyun {
1174*4882a593Smuzhiyun struct uart_port port;
1175*4882a593Smuzhiyun int line;
1176*4882a593Smuzhiyun int rc;
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun rc = pci_enable_device(dev);
1179*4882a593Smuzhiyun if (rc)
1180*4882a593Smuzhiyun return rc;
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun memset(&port, 0, sizeof(port));
1183*4882a593Smuzhiyun port.ops = &serial_txx9_pops;
1184*4882a593Smuzhiyun port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1185*4882a593Smuzhiyun port.uartclk = 66670000;
1186*4882a593Smuzhiyun port.irq = dev->irq;
1187*4882a593Smuzhiyun port.iotype = UPIO_PORT;
1188*4882a593Smuzhiyun port.iobase = pci_resource_start(dev, 1);
1189*4882a593Smuzhiyun port.dev = &dev->dev;
1190*4882a593Smuzhiyun line = serial_txx9_register_port(&port);
1191*4882a593Smuzhiyun if (line < 0) {
1192*4882a593Smuzhiyun printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1193*4882a593Smuzhiyun pci_disable_device(dev);
1194*4882a593Smuzhiyun return line;
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun pci_set_drvdata(dev, &serial_txx9_ports[line]);
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun return 0;
1199*4882a593Smuzhiyun }
1200*4882a593Smuzhiyun
pciserial_txx9_remove_one(struct pci_dev * dev)1201*4882a593Smuzhiyun static void pciserial_txx9_remove_one(struct pci_dev *dev)
1202*4882a593Smuzhiyun {
1203*4882a593Smuzhiyun struct uart_txx9_port *up = pci_get_drvdata(dev);
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun if (up) {
1206*4882a593Smuzhiyun serial_txx9_unregister_port(up->port.line);
1207*4882a593Smuzhiyun pci_disable_device(dev);
1208*4882a593Smuzhiyun }
1209*4882a593Smuzhiyun }
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun #ifdef CONFIG_PM
pciserial_txx9_suspend_one(struct pci_dev * dev,pm_message_t state)1212*4882a593Smuzhiyun static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1213*4882a593Smuzhiyun {
1214*4882a593Smuzhiyun struct uart_txx9_port *up = pci_get_drvdata(dev);
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun if (up)
1217*4882a593Smuzhiyun uart_suspend_port(&serial_txx9_reg, &up->port);
1218*4882a593Smuzhiyun pci_save_state(dev);
1219*4882a593Smuzhiyun pci_set_power_state(dev, pci_choose_state(dev, state));
1220*4882a593Smuzhiyun return 0;
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun
pciserial_txx9_resume_one(struct pci_dev * dev)1223*4882a593Smuzhiyun static int pciserial_txx9_resume_one(struct pci_dev *dev)
1224*4882a593Smuzhiyun {
1225*4882a593Smuzhiyun struct uart_txx9_port *up = pci_get_drvdata(dev);
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun pci_set_power_state(dev, PCI_D0);
1228*4882a593Smuzhiyun pci_restore_state(dev);
1229*4882a593Smuzhiyun if (up)
1230*4882a593Smuzhiyun uart_resume_port(&serial_txx9_reg, &up->port);
1231*4882a593Smuzhiyun return 0;
1232*4882a593Smuzhiyun }
1233*4882a593Smuzhiyun #endif
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun static const struct pci_device_id serial_txx9_pci_tbl[] = {
1236*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC) },
1237*4882a593Smuzhiyun { 0, }
1238*4882a593Smuzhiyun };
1239*4882a593Smuzhiyun
1240*4882a593Smuzhiyun static struct pci_driver serial_txx9_pci_driver = {
1241*4882a593Smuzhiyun .name = "serial_txx9",
1242*4882a593Smuzhiyun .probe = pciserial_txx9_init_one,
1243*4882a593Smuzhiyun .remove = pciserial_txx9_remove_one,
1244*4882a593Smuzhiyun #ifdef CONFIG_PM
1245*4882a593Smuzhiyun .suspend = pciserial_txx9_suspend_one,
1246*4882a593Smuzhiyun .resume = pciserial_txx9_resume_one,
1247*4882a593Smuzhiyun #endif
1248*4882a593Smuzhiyun .id_table = serial_txx9_pci_tbl,
1249*4882a593Smuzhiyun };
1250*4882a593Smuzhiyun
1251*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1252*4882a593Smuzhiyun #endif /* ENABLE_SERIAL_TXX9_PCI */
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun static struct platform_device *serial_txx9_plat_devs;
1255*4882a593Smuzhiyun
serial_txx9_init(void)1256*4882a593Smuzhiyun static int __init serial_txx9_init(void)
1257*4882a593Smuzhiyun {
1258*4882a593Smuzhiyun int ret;
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun ret = uart_register_driver(&serial_txx9_reg);
1263*4882a593Smuzhiyun if (ret)
1264*4882a593Smuzhiyun goto out;
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun serial_txx9_plat_devs = platform_device_alloc("serial_txx9", -1);
1267*4882a593Smuzhiyun if (!serial_txx9_plat_devs) {
1268*4882a593Smuzhiyun ret = -ENOMEM;
1269*4882a593Smuzhiyun goto unreg_uart_drv;
1270*4882a593Smuzhiyun }
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun ret = platform_device_add(serial_txx9_plat_devs);
1273*4882a593Smuzhiyun if (ret)
1274*4882a593Smuzhiyun goto put_dev;
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun serial_txx9_register_ports(&serial_txx9_reg,
1277*4882a593Smuzhiyun &serial_txx9_plat_devs->dev);
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun ret = platform_driver_register(&serial_txx9_plat_driver);
1280*4882a593Smuzhiyun if (ret)
1281*4882a593Smuzhiyun goto del_dev;
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun #ifdef ENABLE_SERIAL_TXX9_PCI
1284*4882a593Smuzhiyun ret = pci_register_driver(&serial_txx9_pci_driver);
1285*4882a593Smuzhiyun if (ret) {
1286*4882a593Smuzhiyun platform_driver_unregister(&serial_txx9_plat_driver);
1287*4882a593Smuzhiyun }
1288*4882a593Smuzhiyun #endif
1289*4882a593Smuzhiyun if (ret == 0)
1290*4882a593Smuzhiyun goto out;
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun del_dev:
1293*4882a593Smuzhiyun platform_device_del(serial_txx9_plat_devs);
1294*4882a593Smuzhiyun put_dev:
1295*4882a593Smuzhiyun platform_device_put(serial_txx9_plat_devs);
1296*4882a593Smuzhiyun unreg_uart_drv:
1297*4882a593Smuzhiyun uart_unregister_driver(&serial_txx9_reg);
1298*4882a593Smuzhiyun out:
1299*4882a593Smuzhiyun return ret;
1300*4882a593Smuzhiyun }
1301*4882a593Smuzhiyun
serial_txx9_exit(void)1302*4882a593Smuzhiyun static void __exit serial_txx9_exit(void)
1303*4882a593Smuzhiyun {
1304*4882a593Smuzhiyun int i;
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun #ifdef ENABLE_SERIAL_TXX9_PCI
1307*4882a593Smuzhiyun pci_unregister_driver(&serial_txx9_pci_driver);
1308*4882a593Smuzhiyun #endif
1309*4882a593Smuzhiyun platform_driver_unregister(&serial_txx9_plat_driver);
1310*4882a593Smuzhiyun platform_device_unregister(serial_txx9_plat_devs);
1311*4882a593Smuzhiyun for (i = 0; i < UART_NR; i++) {
1312*4882a593Smuzhiyun struct uart_txx9_port *up = &serial_txx9_ports[i];
1313*4882a593Smuzhiyun if (up->port.iobase || up->port.mapbase)
1314*4882a593Smuzhiyun uart_remove_one_port(&serial_txx9_reg, &up->port);
1315*4882a593Smuzhiyun }
1316*4882a593Smuzhiyun
1317*4882a593Smuzhiyun uart_unregister_driver(&serial_txx9_reg);
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun module_init(serial_txx9_init);
1321*4882a593Smuzhiyun module_exit(serial_txx9_exit);
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1324*4882a593Smuzhiyun MODULE_DESCRIPTION("TX39/49 serial driver");
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
1327