1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Based on drivers/serial/8250.c by Russell King.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Nicolas Pitre
6*4882a593Smuzhiyun * Created: Feb 20, 2003
7*4882a593Smuzhiyun * Copyright: (C) 2003 Monta Vista Software, Inc.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Note 1: This driver is made separate from the already too overloaded
10*4882a593Smuzhiyun * 8250.c because it needs some kirks of its own and that'll make it
11*4882a593Smuzhiyun * easier to add DMA support.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * Note 2: I'm too sick of device allocation policies for serial ports.
14*4882a593Smuzhiyun * If someone else wants to request an "official" allocation of major/minor
15*4882a593Smuzhiyun * for this driver please be my guest. And don't forget that new hardware
16*4882a593Smuzhiyun * to come from Intel might have more than 3 or 4 of those UARTs. Let's
17*4882a593Smuzhiyun * hope for a better port registration and dynamic device allocation scheme
18*4882a593Smuzhiyun * with the serial core maintainer satisfaction to appear soon.
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <linux/ioport.h>
23*4882a593Smuzhiyun #include <linux/init.h>
24*4882a593Smuzhiyun #include <linux/console.h>
25*4882a593Smuzhiyun #include <linux/sysrq.h>
26*4882a593Smuzhiyun #include <linux/serial_reg.h>
27*4882a593Smuzhiyun #include <linux/circ_buf.h>
28*4882a593Smuzhiyun #include <linux/delay.h>
29*4882a593Smuzhiyun #include <linux/interrupt.h>
30*4882a593Smuzhiyun #include <linux/of.h>
31*4882a593Smuzhiyun #include <linux/platform_device.h>
32*4882a593Smuzhiyun #include <linux/tty.h>
33*4882a593Smuzhiyun #include <linux/tty_flip.h>
34*4882a593Smuzhiyun #include <linux/serial_core.h>
35*4882a593Smuzhiyun #include <linux/clk.h>
36*4882a593Smuzhiyun #include <linux/io.h>
37*4882a593Smuzhiyun #include <linux/slab.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define PXA_NAME_LEN 8
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct uart_pxa_port {
42*4882a593Smuzhiyun struct uart_port port;
43*4882a593Smuzhiyun unsigned char ier;
44*4882a593Smuzhiyun unsigned char lcr;
45*4882a593Smuzhiyun unsigned char mcr;
46*4882a593Smuzhiyun unsigned int lsr_break_flag;
47*4882a593Smuzhiyun struct clk *clk;
48*4882a593Smuzhiyun char name[PXA_NAME_LEN];
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
serial_in(struct uart_pxa_port * up,int offset)51*4882a593Smuzhiyun static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun offset <<= 2;
54*4882a593Smuzhiyun return readl(up->port.membase + offset);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
serial_out(struct uart_pxa_port * up,int offset,int value)57*4882a593Smuzhiyun static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun offset <<= 2;
60*4882a593Smuzhiyun writel(value, up->port.membase + offset);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
serial_pxa_enable_ms(struct uart_port * port)63*4882a593Smuzhiyun static void serial_pxa_enable_ms(struct uart_port *port)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun up->ier |= UART_IER_MSI;
68*4882a593Smuzhiyun serial_out(up, UART_IER, up->ier);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
serial_pxa_stop_tx(struct uart_port * port)71*4882a593Smuzhiyun static void serial_pxa_stop_tx(struct uart_port *port)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (up->ier & UART_IER_THRI) {
76*4882a593Smuzhiyun up->ier &= ~UART_IER_THRI;
77*4882a593Smuzhiyun serial_out(up, UART_IER, up->ier);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
serial_pxa_stop_rx(struct uart_port * port)81*4882a593Smuzhiyun static void serial_pxa_stop_rx(struct uart_port *port)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun up->ier &= ~UART_IER_RLSI;
86*4882a593Smuzhiyun up->port.read_status_mask &= ~UART_LSR_DR;
87*4882a593Smuzhiyun serial_out(up, UART_IER, up->ier);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
receive_chars(struct uart_pxa_port * up,int * status)90*4882a593Smuzhiyun static inline void receive_chars(struct uart_pxa_port *up, int *status)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun unsigned int ch, flag;
93*4882a593Smuzhiyun int max_count = 256;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun do {
96*4882a593Smuzhiyun /* work around Errata #20 according to
97*4882a593Smuzhiyun * Intel(R) PXA27x Processor Family
98*4882a593Smuzhiyun * Specification Update (May 2005)
99*4882a593Smuzhiyun *
100*4882a593Smuzhiyun * Step 2
101*4882a593Smuzhiyun * Disable the Reciever Time Out Interrupt via IER[RTOEI]
102*4882a593Smuzhiyun */
103*4882a593Smuzhiyun up->ier &= ~UART_IER_RTOIE;
104*4882a593Smuzhiyun serial_out(up, UART_IER, up->ier);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun ch = serial_in(up, UART_RX);
107*4882a593Smuzhiyun flag = TTY_NORMAL;
108*4882a593Smuzhiyun up->port.icount.rx++;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
111*4882a593Smuzhiyun UART_LSR_FE | UART_LSR_OE))) {
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun * For statistics only
114*4882a593Smuzhiyun */
115*4882a593Smuzhiyun if (*status & UART_LSR_BI) {
116*4882a593Smuzhiyun *status &= ~(UART_LSR_FE | UART_LSR_PE);
117*4882a593Smuzhiyun up->port.icount.brk++;
118*4882a593Smuzhiyun /*
119*4882a593Smuzhiyun * We do the SysRQ and SAK checking
120*4882a593Smuzhiyun * here because otherwise the break
121*4882a593Smuzhiyun * may get masked by ignore_status_mask
122*4882a593Smuzhiyun * or read_status_mask.
123*4882a593Smuzhiyun */
124*4882a593Smuzhiyun if (uart_handle_break(&up->port))
125*4882a593Smuzhiyun goto ignore_char;
126*4882a593Smuzhiyun } else if (*status & UART_LSR_PE)
127*4882a593Smuzhiyun up->port.icount.parity++;
128*4882a593Smuzhiyun else if (*status & UART_LSR_FE)
129*4882a593Smuzhiyun up->port.icount.frame++;
130*4882a593Smuzhiyun if (*status & UART_LSR_OE)
131*4882a593Smuzhiyun up->port.icount.overrun++;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /*
134*4882a593Smuzhiyun * Mask off conditions which should be ignored.
135*4882a593Smuzhiyun */
136*4882a593Smuzhiyun *status &= up->port.read_status_mask;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_PXA_CONSOLE
139*4882a593Smuzhiyun if (up->port.line == up->port.cons->index) {
140*4882a593Smuzhiyun /* Recover the break flag from console xmit */
141*4882a593Smuzhiyun *status |= up->lsr_break_flag;
142*4882a593Smuzhiyun up->lsr_break_flag = 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun #endif
145*4882a593Smuzhiyun if (*status & UART_LSR_BI) {
146*4882a593Smuzhiyun flag = TTY_BREAK;
147*4882a593Smuzhiyun } else if (*status & UART_LSR_PE)
148*4882a593Smuzhiyun flag = TTY_PARITY;
149*4882a593Smuzhiyun else if (*status & UART_LSR_FE)
150*4882a593Smuzhiyun flag = TTY_FRAME;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun if (uart_handle_sysrq_char(&up->port, ch))
154*4882a593Smuzhiyun goto ignore_char;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun ignore_char:
159*4882a593Smuzhiyun *status = serial_in(up, UART_LSR);
160*4882a593Smuzhiyun } while ((*status & UART_LSR_DR) && (max_count-- > 0));
161*4882a593Smuzhiyun tty_flip_buffer_push(&up->port.state->port);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /* work around Errata #20 according to
164*4882a593Smuzhiyun * Intel(R) PXA27x Processor Family
165*4882a593Smuzhiyun * Specification Update (May 2005)
166*4882a593Smuzhiyun *
167*4882a593Smuzhiyun * Step 6:
168*4882a593Smuzhiyun * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
169*4882a593Smuzhiyun */
170*4882a593Smuzhiyun up->ier |= UART_IER_RTOIE;
171*4882a593Smuzhiyun serial_out(up, UART_IER, up->ier);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
transmit_chars(struct uart_pxa_port * up)174*4882a593Smuzhiyun static void transmit_chars(struct uart_pxa_port *up)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun struct circ_buf *xmit = &up->port.state->xmit;
177*4882a593Smuzhiyun int count;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (up->port.x_char) {
180*4882a593Smuzhiyun serial_out(up, UART_TX, up->port.x_char);
181*4882a593Smuzhiyun up->port.icount.tx++;
182*4882a593Smuzhiyun up->port.x_char = 0;
183*4882a593Smuzhiyun return;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
186*4882a593Smuzhiyun serial_pxa_stop_tx(&up->port);
187*4882a593Smuzhiyun return;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun count = up->port.fifosize / 2;
191*4882a593Smuzhiyun do {
192*4882a593Smuzhiyun serial_out(up, UART_TX, xmit->buf[xmit->tail]);
193*4882a593Smuzhiyun xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
194*4882a593Smuzhiyun up->port.icount.tx++;
195*4882a593Smuzhiyun if (uart_circ_empty(xmit))
196*4882a593Smuzhiyun break;
197*4882a593Smuzhiyun } while (--count > 0);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
200*4882a593Smuzhiyun uart_write_wakeup(&up->port);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun if (uart_circ_empty(xmit))
204*4882a593Smuzhiyun serial_pxa_stop_tx(&up->port);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
serial_pxa_start_tx(struct uart_port * port)207*4882a593Smuzhiyun static void serial_pxa_start_tx(struct uart_port *port)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun if (!(up->ier & UART_IER_THRI)) {
212*4882a593Smuzhiyun up->ier |= UART_IER_THRI;
213*4882a593Smuzhiyun serial_out(up, UART_IER, up->ier);
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* should hold up->port.lock */
check_modem_status(struct uart_pxa_port * up)218*4882a593Smuzhiyun static inline void check_modem_status(struct uart_pxa_port *up)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun int status;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun status = serial_in(up, UART_MSR);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun if ((status & UART_MSR_ANY_DELTA) == 0)
225*4882a593Smuzhiyun return;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun if (status & UART_MSR_TERI)
228*4882a593Smuzhiyun up->port.icount.rng++;
229*4882a593Smuzhiyun if (status & UART_MSR_DDSR)
230*4882a593Smuzhiyun up->port.icount.dsr++;
231*4882a593Smuzhiyun if (status & UART_MSR_DDCD)
232*4882a593Smuzhiyun uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
233*4882a593Smuzhiyun if (status & UART_MSR_DCTS)
234*4882a593Smuzhiyun uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun wake_up_interruptible(&up->port.state->port.delta_msr_wait);
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /*
240*4882a593Smuzhiyun * This handles the interrupt from one port.
241*4882a593Smuzhiyun */
serial_pxa_irq(int irq,void * dev_id)242*4882a593Smuzhiyun static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun struct uart_pxa_port *up = dev_id;
245*4882a593Smuzhiyun unsigned int iir, lsr;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun iir = serial_in(up, UART_IIR);
248*4882a593Smuzhiyun if (iir & UART_IIR_NO_INT)
249*4882a593Smuzhiyun return IRQ_NONE;
250*4882a593Smuzhiyun spin_lock(&up->port.lock);
251*4882a593Smuzhiyun lsr = serial_in(up, UART_LSR);
252*4882a593Smuzhiyun if (lsr & UART_LSR_DR)
253*4882a593Smuzhiyun receive_chars(up, &lsr);
254*4882a593Smuzhiyun check_modem_status(up);
255*4882a593Smuzhiyun if (lsr & UART_LSR_THRE)
256*4882a593Smuzhiyun transmit_chars(up);
257*4882a593Smuzhiyun spin_unlock(&up->port.lock);
258*4882a593Smuzhiyun return IRQ_HANDLED;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
serial_pxa_tx_empty(struct uart_port * port)261*4882a593Smuzhiyun static unsigned int serial_pxa_tx_empty(struct uart_port *port)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
264*4882a593Smuzhiyun unsigned long flags;
265*4882a593Smuzhiyun unsigned int ret;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
268*4882a593Smuzhiyun ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
269*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun return ret;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
serial_pxa_get_mctrl(struct uart_port * port)274*4882a593Smuzhiyun static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
277*4882a593Smuzhiyun unsigned char status;
278*4882a593Smuzhiyun unsigned int ret;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun status = serial_in(up, UART_MSR);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun ret = 0;
283*4882a593Smuzhiyun if (status & UART_MSR_DCD)
284*4882a593Smuzhiyun ret |= TIOCM_CAR;
285*4882a593Smuzhiyun if (status & UART_MSR_RI)
286*4882a593Smuzhiyun ret |= TIOCM_RNG;
287*4882a593Smuzhiyun if (status & UART_MSR_DSR)
288*4882a593Smuzhiyun ret |= TIOCM_DSR;
289*4882a593Smuzhiyun if (status & UART_MSR_CTS)
290*4882a593Smuzhiyun ret |= TIOCM_CTS;
291*4882a593Smuzhiyun return ret;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
serial_pxa_set_mctrl(struct uart_port * port,unsigned int mctrl)294*4882a593Smuzhiyun static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
297*4882a593Smuzhiyun unsigned char mcr = 0;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun if (mctrl & TIOCM_RTS)
300*4882a593Smuzhiyun mcr |= UART_MCR_RTS;
301*4882a593Smuzhiyun if (mctrl & TIOCM_DTR)
302*4882a593Smuzhiyun mcr |= UART_MCR_DTR;
303*4882a593Smuzhiyun if (mctrl & TIOCM_OUT1)
304*4882a593Smuzhiyun mcr |= UART_MCR_OUT1;
305*4882a593Smuzhiyun if (mctrl & TIOCM_OUT2)
306*4882a593Smuzhiyun mcr |= UART_MCR_OUT2;
307*4882a593Smuzhiyun if (mctrl & TIOCM_LOOP)
308*4882a593Smuzhiyun mcr |= UART_MCR_LOOP;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun mcr |= up->mcr;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun serial_out(up, UART_MCR, mcr);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
serial_pxa_break_ctl(struct uart_port * port,int break_state)315*4882a593Smuzhiyun static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
318*4882a593Smuzhiyun unsigned long flags;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
321*4882a593Smuzhiyun if (break_state == -1)
322*4882a593Smuzhiyun up->lcr |= UART_LCR_SBC;
323*4882a593Smuzhiyun else
324*4882a593Smuzhiyun up->lcr &= ~UART_LCR_SBC;
325*4882a593Smuzhiyun serial_out(up, UART_LCR, up->lcr);
326*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
serial_pxa_startup(struct uart_port * port)329*4882a593Smuzhiyun static int serial_pxa_startup(struct uart_port *port)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
332*4882a593Smuzhiyun unsigned long flags;
333*4882a593Smuzhiyun int retval;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (port->line == 3) /* HWUART */
336*4882a593Smuzhiyun up->mcr |= UART_MCR_AFE;
337*4882a593Smuzhiyun else
338*4882a593Smuzhiyun up->mcr = 0;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun up->port.uartclk = clk_get_rate(up->clk);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun /*
343*4882a593Smuzhiyun * Allocate the IRQ
344*4882a593Smuzhiyun */
345*4882a593Smuzhiyun retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
346*4882a593Smuzhiyun if (retval)
347*4882a593Smuzhiyun return retval;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun /*
350*4882a593Smuzhiyun * Clear the FIFO buffers and disable them.
351*4882a593Smuzhiyun * (they will be reenabled in set_termios())
352*4882a593Smuzhiyun */
353*4882a593Smuzhiyun serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
354*4882a593Smuzhiyun serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
355*4882a593Smuzhiyun UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
356*4882a593Smuzhiyun serial_out(up, UART_FCR, 0);
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun /*
359*4882a593Smuzhiyun * Clear the interrupt registers.
360*4882a593Smuzhiyun */
361*4882a593Smuzhiyun (void) serial_in(up, UART_LSR);
362*4882a593Smuzhiyun (void) serial_in(up, UART_RX);
363*4882a593Smuzhiyun (void) serial_in(up, UART_IIR);
364*4882a593Smuzhiyun (void) serial_in(up, UART_MSR);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /*
367*4882a593Smuzhiyun * Now, initialize the UART
368*4882a593Smuzhiyun */
369*4882a593Smuzhiyun serial_out(up, UART_LCR, UART_LCR_WLEN8);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
372*4882a593Smuzhiyun up->port.mctrl |= TIOCM_OUT2;
373*4882a593Smuzhiyun serial_pxa_set_mctrl(&up->port, up->port.mctrl);
374*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun /*
377*4882a593Smuzhiyun * Finally, enable interrupts. Note: Modem status interrupts
378*4882a593Smuzhiyun * are set via set_termios(), which will be occurring imminently
379*4882a593Smuzhiyun * anyway, so we don't enable them here.
380*4882a593Smuzhiyun */
381*4882a593Smuzhiyun up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
382*4882a593Smuzhiyun serial_out(up, UART_IER, up->ier);
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun /*
385*4882a593Smuzhiyun * And clear the interrupt registers again for luck.
386*4882a593Smuzhiyun */
387*4882a593Smuzhiyun (void) serial_in(up, UART_LSR);
388*4882a593Smuzhiyun (void) serial_in(up, UART_RX);
389*4882a593Smuzhiyun (void) serial_in(up, UART_IIR);
390*4882a593Smuzhiyun (void) serial_in(up, UART_MSR);
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun return 0;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
serial_pxa_shutdown(struct uart_port * port)395*4882a593Smuzhiyun static void serial_pxa_shutdown(struct uart_port *port)
396*4882a593Smuzhiyun {
397*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
398*4882a593Smuzhiyun unsigned long flags;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun free_irq(up->port.irq, up);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun /*
403*4882a593Smuzhiyun * Disable interrupts from this port
404*4882a593Smuzhiyun */
405*4882a593Smuzhiyun up->ier = 0;
406*4882a593Smuzhiyun serial_out(up, UART_IER, 0);
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
409*4882a593Smuzhiyun up->port.mctrl &= ~TIOCM_OUT2;
410*4882a593Smuzhiyun serial_pxa_set_mctrl(&up->port, up->port.mctrl);
411*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun /*
414*4882a593Smuzhiyun * Disable break condition and FIFOs
415*4882a593Smuzhiyun */
416*4882a593Smuzhiyun serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
417*4882a593Smuzhiyun serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
418*4882a593Smuzhiyun UART_FCR_CLEAR_RCVR |
419*4882a593Smuzhiyun UART_FCR_CLEAR_XMIT);
420*4882a593Smuzhiyun serial_out(up, UART_FCR, 0);
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun static void
serial_pxa_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)424*4882a593Smuzhiyun serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
425*4882a593Smuzhiyun struct ktermios *old)
426*4882a593Smuzhiyun {
427*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
428*4882a593Smuzhiyun unsigned char cval, fcr = 0;
429*4882a593Smuzhiyun unsigned long flags;
430*4882a593Smuzhiyun unsigned int baud, quot;
431*4882a593Smuzhiyun unsigned int dll;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun switch (termios->c_cflag & CSIZE) {
434*4882a593Smuzhiyun case CS5:
435*4882a593Smuzhiyun cval = UART_LCR_WLEN5;
436*4882a593Smuzhiyun break;
437*4882a593Smuzhiyun case CS6:
438*4882a593Smuzhiyun cval = UART_LCR_WLEN6;
439*4882a593Smuzhiyun break;
440*4882a593Smuzhiyun case CS7:
441*4882a593Smuzhiyun cval = UART_LCR_WLEN7;
442*4882a593Smuzhiyun break;
443*4882a593Smuzhiyun default:
444*4882a593Smuzhiyun case CS8:
445*4882a593Smuzhiyun cval = UART_LCR_WLEN8;
446*4882a593Smuzhiyun break;
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun if (termios->c_cflag & CSTOPB)
450*4882a593Smuzhiyun cval |= UART_LCR_STOP;
451*4882a593Smuzhiyun if (termios->c_cflag & PARENB)
452*4882a593Smuzhiyun cval |= UART_LCR_PARITY;
453*4882a593Smuzhiyun if (!(termios->c_cflag & PARODD))
454*4882a593Smuzhiyun cval |= UART_LCR_EPAR;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun /*
457*4882a593Smuzhiyun * Ask the core to calculate the divisor for us.
458*4882a593Smuzhiyun */
459*4882a593Smuzhiyun baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
460*4882a593Smuzhiyun quot = uart_get_divisor(port, baud);
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun if ((up->port.uartclk / quot) < (2400 * 16))
463*4882a593Smuzhiyun fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
464*4882a593Smuzhiyun else if ((up->port.uartclk / quot) < (230400 * 16))
465*4882a593Smuzhiyun fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
466*4882a593Smuzhiyun else
467*4882a593Smuzhiyun fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun /*
470*4882a593Smuzhiyun * Ok, we're now changing the port state. Do it with
471*4882a593Smuzhiyun * interrupts disabled.
472*4882a593Smuzhiyun */
473*4882a593Smuzhiyun spin_lock_irqsave(&up->port.lock, flags);
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun /*
476*4882a593Smuzhiyun * Ensure the port will be enabled.
477*4882a593Smuzhiyun * This is required especially for serial console.
478*4882a593Smuzhiyun */
479*4882a593Smuzhiyun up->ier |= UART_IER_UUE;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun /*
482*4882a593Smuzhiyun * Update the per-port timeout.
483*4882a593Smuzhiyun */
484*4882a593Smuzhiyun uart_update_timeout(port, termios->c_cflag, baud);
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
487*4882a593Smuzhiyun if (termios->c_iflag & INPCK)
488*4882a593Smuzhiyun up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
489*4882a593Smuzhiyun if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
490*4882a593Smuzhiyun up->port.read_status_mask |= UART_LSR_BI;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun /*
493*4882a593Smuzhiyun * Characters to ignore
494*4882a593Smuzhiyun */
495*4882a593Smuzhiyun up->port.ignore_status_mask = 0;
496*4882a593Smuzhiyun if (termios->c_iflag & IGNPAR)
497*4882a593Smuzhiyun up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
498*4882a593Smuzhiyun if (termios->c_iflag & IGNBRK) {
499*4882a593Smuzhiyun up->port.ignore_status_mask |= UART_LSR_BI;
500*4882a593Smuzhiyun /*
501*4882a593Smuzhiyun * If we're ignoring parity and break indicators,
502*4882a593Smuzhiyun * ignore overruns too (for real raw support).
503*4882a593Smuzhiyun */
504*4882a593Smuzhiyun if (termios->c_iflag & IGNPAR)
505*4882a593Smuzhiyun up->port.ignore_status_mask |= UART_LSR_OE;
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun /*
509*4882a593Smuzhiyun * ignore all characters if CREAD is not set
510*4882a593Smuzhiyun */
511*4882a593Smuzhiyun if ((termios->c_cflag & CREAD) == 0)
512*4882a593Smuzhiyun up->port.ignore_status_mask |= UART_LSR_DR;
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun /*
515*4882a593Smuzhiyun * CTS flow control flag and modem status interrupts
516*4882a593Smuzhiyun */
517*4882a593Smuzhiyun up->ier &= ~UART_IER_MSI;
518*4882a593Smuzhiyun if (UART_ENABLE_MS(&up->port, termios->c_cflag))
519*4882a593Smuzhiyun up->ier |= UART_IER_MSI;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun serial_out(up, UART_IER, up->ier);
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun if (termios->c_cflag & CRTSCTS)
524*4882a593Smuzhiyun up->mcr |= UART_MCR_AFE;
525*4882a593Smuzhiyun else
526*4882a593Smuzhiyun up->mcr &= ~UART_MCR_AFE;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
529*4882a593Smuzhiyun serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun /*
532*4882a593Smuzhiyun * work around Errata #75 according to Intel(R) PXA27x Processor Family
533*4882a593Smuzhiyun * Specification Update (Nov 2005)
534*4882a593Smuzhiyun */
535*4882a593Smuzhiyun dll = serial_in(up, UART_DLL);
536*4882a593Smuzhiyun WARN_ON(dll != (quot & 0xff));
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
539*4882a593Smuzhiyun serial_out(up, UART_LCR, cval); /* reset DLAB */
540*4882a593Smuzhiyun up->lcr = cval; /* Save LCR */
541*4882a593Smuzhiyun serial_pxa_set_mctrl(&up->port, up->port.mctrl);
542*4882a593Smuzhiyun serial_out(up, UART_FCR, fcr);
543*4882a593Smuzhiyun spin_unlock_irqrestore(&up->port.lock, flags);
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun static void
serial_pxa_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)547*4882a593Smuzhiyun serial_pxa_pm(struct uart_port *port, unsigned int state,
548*4882a593Smuzhiyun unsigned int oldstate)
549*4882a593Smuzhiyun {
550*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun if (!state)
553*4882a593Smuzhiyun clk_prepare_enable(up->clk);
554*4882a593Smuzhiyun else
555*4882a593Smuzhiyun clk_disable_unprepare(up->clk);
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
serial_pxa_release_port(struct uart_port * port)558*4882a593Smuzhiyun static void serial_pxa_release_port(struct uart_port *port)
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun
serial_pxa_request_port(struct uart_port * port)562*4882a593Smuzhiyun static int serial_pxa_request_port(struct uart_port *port)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun return 0;
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun
serial_pxa_config_port(struct uart_port * port,int flags)567*4882a593Smuzhiyun static void serial_pxa_config_port(struct uart_port *port, int flags)
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
570*4882a593Smuzhiyun up->port.type = PORT_PXA;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun static int
serial_pxa_verify_port(struct uart_port * port,struct serial_struct * ser)574*4882a593Smuzhiyun serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
575*4882a593Smuzhiyun {
576*4882a593Smuzhiyun /* we don't want the core code to modify any port params */
577*4882a593Smuzhiyun return -EINVAL;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun static const char *
serial_pxa_type(struct uart_port * port)581*4882a593Smuzhiyun serial_pxa_type(struct uart_port *port)
582*4882a593Smuzhiyun {
583*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
584*4882a593Smuzhiyun return up->name;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun static struct uart_pxa_port *serial_pxa_ports[4];
588*4882a593Smuzhiyun static struct uart_driver serial_pxa_reg;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_PXA_CONSOLE
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun /*
595*4882a593Smuzhiyun * Wait for transmitter & holding register to empty
596*4882a593Smuzhiyun */
wait_for_xmitr(struct uart_pxa_port * up)597*4882a593Smuzhiyun static void wait_for_xmitr(struct uart_pxa_port *up)
598*4882a593Smuzhiyun {
599*4882a593Smuzhiyun unsigned int status, tmout = 10000;
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun /* Wait up to 10ms for the character(s) to be sent. */
602*4882a593Smuzhiyun do {
603*4882a593Smuzhiyun status = serial_in(up, UART_LSR);
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun if (status & UART_LSR_BI)
606*4882a593Smuzhiyun up->lsr_break_flag = UART_LSR_BI;
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun if (--tmout == 0)
609*4882a593Smuzhiyun break;
610*4882a593Smuzhiyun udelay(1);
611*4882a593Smuzhiyun } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun /* Wait up to 1s for flow control if necessary */
614*4882a593Smuzhiyun if (up->port.flags & UPF_CONS_FLOW) {
615*4882a593Smuzhiyun tmout = 1000000;
616*4882a593Smuzhiyun while (--tmout &&
617*4882a593Smuzhiyun ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
618*4882a593Smuzhiyun udelay(1);
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun
serial_pxa_console_putchar(struct uart_port * port,int ch)622*4882a593Smuzhiyun static void serial_pxa_console_putchar(struct uart_port *port, int ch)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun wait_for_xmitr(up);
627*4882a593Smuzhiyun serial_out(up, UART_TX, ch);
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun /*
631*4882a593Smuzhiyun * Print a string to the serial port trying not to disturb
632*4882a593Smuzhiyun * any possible real use of the port...
633*4882a593Smuzhiyun *
634*4882a593Smuzhiyun * The console_lock must be held when we get here.
635*4882a593Smuzhiyun */
636*4882a593Smuzhiyun static void
serial_pxa_console_write(struct console * co,const char * s,unsigned int count)637*4882a593Smuzhiyun serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
638*4882a593Smuzhiyun {
639*4882a593Smuzhiyun struct uart_pxa_port *up = serial_pxa_ports[co->index];
640*4882a593Smuzhiyun unsigned int ier;
641*4882a593Smuzhiyun unsigned long flags;
642*4882a593Smuzhiyun int locked = 1;
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun clk_enable(up->clk);
645*4882a593Smuzhiyun local_irq_save(flags);
646*4882a593Smuzhiyun if (up->port.sysrq)
647*4882a593Smuzhiyun locked = 0;
648*4882a593Smuzhiyun else if (oops_in_progress)
649*4882a593Smuzhiyun locked = spin_trylock(&up->port.lock);
650*4882a593Smuzhiyun else
651*4882a593Smuzhiyun spin_lock(&up->port.lock);
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun /*
654*4882a593Smuzhiyun * First save the IER then disable the interrupts
655*4882a593Smuzhiyun */
656*4882a593Smuzhiyun ier = serial_in(up, UART_IER);
657*4882a593Smuzhiyun serial_out(up, UART_IER, UART_IER_UUE);
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun /*
662*4882a593Smuzhiyun * Finally, wait for transmitter to become empty
663*4882a593Smuzhiyun * and restore the IER
664*4882a593Smuzhiyun */
665*4882a593Smuzhiyun wait_for_xmitr(up);
666*4882a593Smuzhiyun serial_out(up, UART_IER, ier);
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun if (locked)
669*4882a593Smuzhiyun spin_unlock(&up->port.lock);
670*4882a593Smuzhiyun local_irq_restore(flags);
671*4882a593Smuzhiyun clk_disable(up->clk);
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun #ifdef CONFIG_CONSOLE_POLL
676*4882a593Smuzhiyun /*
677*4882a593Smuzhiyun * Console polling routines for writing and reading from the uart while
678*4882a593Smuzhiyun * in an interrupt or debug context.
679*4882a593Smuzhiyun */
680*4882a593Smuzhiyun
serial_pxa_get_poll_char(struct uart_port * port)681*4882a593Smuzhiyun static int serial_pxa_get_poll_char(struct uart_port *port)
682*4882a593Smuzhiyun {
683*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
684*4882a593Smuzhiyun unsigned char lsr = serial_in(up, UART_LSR);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun while (!(lsr & UART_LSR_DR))
687*4882a593Smuzhiyun lsr = serial_in(up, UART_LSR);
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun return serial_in(up, UART_RX);
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun
serial_pxa_put_poll_char(struct uart_port * port,unsigned char c)693*4882a593Smuzhiyun static void serial_pxa_put_poll_char(struct uart_port *port,
694*4882a593Smuzhiyun unsigned char c)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun unsigned int ier;
697*4882a593Smuzhiyun struct uart_pxa_port *up = (struct uart_pxa_port *)port;
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun /*
700*4882a593Smuzhiyun * First save the IER then disable the interrupts
701*4882a593Smuzhiyun */
702*4882a593Smuzhiyun ier = serial_in(up, UART_IER);
703*4882a593Smuzhiyun serial_out(up, UART_IER, UART_IER_UUE);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun wait_for_xmitr(up);
706*4882a593Smuzhiyun /*
707*4882a593Smuzhiyun * Send the character out.
708*4882a593Smuzhiyun */
709*4882a593Smuzhiyun serial_out(up, UART_TX, c);
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun /*
712*4882a593Smuzhiyun * Finally, wait for transmitter to become empty
713*4882a593Smuzhiyun * and restore the IER
714*4882a593Smuzhiyun */
715*4882a593Smuzhiyun wait_for_xmitr(up);
716*4882a593Smuzhiyun serial_out(up, UART_IER, ier);
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun #endif /* CONFIG_CONSOLE_POLL */
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun static int __init
serial_pxa_console_setup(struct console * co,char * options)722*4882a593Smuzhiyun serial_pxa_console_setup(struct console *co, char *options)
723*4882a593Smuzhiyun {
724*4882a593Smuzhiyun struct uart_pxa_port *up;
725*4882a593Smuzhiyun int baud = 9600;
726*4882a593Smuzhiyun int bits = 8;
727*4882a593Smuzhiyun int parity = 'n';
728*4882a593Smuzhiyun int flow = 'n';
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun if (co->index == -1 || co->index >= serial_pxa_reg.nr)
731*4882a593Smuzhiyun co->index = 0;
732*4882a593Smuzhiyun up = serial_pxa_ports[co->index];
733*4882a593Smuzhiyun if (!up)
734*4882a593Smuzhiyun return -ENODEV;
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun if (options)
737*4882a593Smuzhiyun uart_parse_options(options, &baud, &parity, &bits, &flow);
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun return uart_set_options(&up->port, co, baud, parity, bits, flow);
740*4882a593Smuzhiyun }
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun static struct console serial_pxa_console = {
743*4882a593Smuzhiyun .name = "ttyS",
744*4882a593Smuzhiyun .write = serial_pxa_console_write,
745*4882a593Smuzhiyun .device = uart_console_device,
746*4882a593Smuzhiyun .setup = serial_pxa_console_setup,
747*4882a593Smuzhiyun .flags = CON_PRINTBUFFER,
748*4882a593Smuzhiyun .index = -1,
749*4882a593Smuzhiyun .data = &serial_pxa_reg,
750*4882a593Smuzhiyun };
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun #define PXA_CONSOLE &serial_pxa_console
753*4882a593Smuzhiyun #else
754*4882a593Smuzhiyun #define PXA_CONSOLE NULL
755*4882a593Smuzhiyun #endif
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun static const struct uart_ops serial_pxa_pops = {
758*4882a593Smuzhiyun .tx_empty = serial_pxa_tx_empty,
759*4882a593Smuzhiyun .set_mctrl = serial_pxa_set_mctrl,
760*4882a593Smuzhiyun .get_mctrl = serial_pxa_get_mctrl,
761*4882a593Smuzhiyun .stop_tx = serial_pxa_stop_tx,
762*4882a593Smuzhiyun .start_tx = serial_pxa_start_tx,
763*4882a593Smuzhiyun .stop_rx = serial_pxa_stop_rx,
764*4882a593Smuzhiyun .enable_ms = serial_pxa_enable_ms,
765*4882a593Smuzhiyun .break_ctl = serial_pxa_break_ctl,
766*4882a593Smuzhiyun .startup = serial_pxa_startup,
767*4882a593Smuzhiyun .shutdown = serial_pxa_shutdown,
768*4882a593Smuzhiyun .set_termios = serial_pxa_set_termios,
769*4882a593Smuzhiyun .pm = serial_pxa_pm,
770*4882a593Smuzhiyun .type = serial_pxa_type,
771*4882a593Smuzhiyun .release_port = serial_pxa_release_port,
772*4882a593Smuzhiyun .request_port = serial_pxa_request_port,
773*4882a593Smuzhiyun .config_port = serial_pxa_config_port,
774*4882a593Smuzhiyun .verify_port = serial_pxa_verify_port,
775*4882a593Smuzhiyun #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
776*4882a593Smuzhiyun .poll_get_char = serial_pxa_get_poll_char,
777*4882a593Smuzhiyun .poll_put_char = serial_pxa_put_poll_char,
778*4882a593Smuzhiyun #endif
779*4882a593Smuzhiyun };
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun static struct uart_driver serial_pxa_reg = {
782*4882a593Smuzhiyun .owner = THIS_MODULE,
783*4882a593Smuzhiyun .driver_name = "PXA serial",
784*4882a593Smuzhiyun .dev_name = "ttyS",
785*4882a593Smuzhiyun .major = TTY_MAJOR,
786*4882a593Smuzhiyun .minor = 64,
787*4882a593Smuzhiyun .nr = 4,
788*4882a593Smuzhiyun .cons = PXA_CONSOLE,
789*4882a593Smuzhiyun };
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun #ifdef CONFIG_PM
serial_pxa_suspend(struct device * dev)792*4882a593Smuzhiyun static int serial_pxa_suspend(struct device *dev)
793*4882a593Smuzhiyun {
794*4882a593Smuzhiyun struct uart_pxa_port *sport = dev_get_drvdata(dev);
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun if (sport)
797*4882a593Smuzhiyun uart_suspend_port(&serial_pxa_reg, &sport->port);
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun return 0;
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun
serial_pxa_resume(struct device * dev)802*4882a593Smuzhiyun static int serial_pxa_resume(struct device *dev)
803*4882a593Smuzhiyun {
804*4882a593Smuzhiyun struct uart_pxa_port *sport = dev_get_drvdata(dev);
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun if (sport)
807*4882a593Smuzhiyun uart_resume_port(&serial_pxa_reg, &sport->port);
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun return 0;
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun static const struct dev_pm_ops serial_pxa_pm_ops = {
813*4882a593Smuzhiyun .suspend = serial_pxa_suspend,
814*4882a593Smuzhiyun .resume = serial_pxa_resume,
815*4882a593Smuzhiyun };
816*4882a593Smuzhiyun #endif
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun static const struct of_device_id serial_pxa_dt_ids[] = {
819*4882a593Smuzhiyun { .compatible = "mrvl,pxa-uart", },
820*4882a593Smuzhiyun { .compatible = "mrvl,mmp-uart", },
821*4882a593Smuzhiyun {}
822*4882a593Smuzhiyun };
823*4882a593Smuzhiyun
serial_pxa_probe_dt(struct platform_device * pdev,struct uart_pxa_port * sport)824*4882a593Smuzhiyun static int serial_pxa_probe_dt(struct platform_device *pdev,
825*4882a593Smuzhiyun struct uart_pxa_port *sport)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
828*4882a593Smuzhiyun int ret;
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun if (!np)
831*4882a593Smuzhiyun return 1;
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun ret = of_alias_get_id(np, "serial");
834*4882a593Smuzhiyun if (ret < 0) {
835*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
836*4882a593Smuzhiyun return ret;
837*4882a593Smuzhiyun }
838*4882a593Smuzhiyun sport->port.line = ret;
839*4882a593Smuzhiyun return 0;
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun
serial_pxa_probe(struct platform_device * dev)842*4882a593Smuzhiyun static int serial_pxa_probe(struct platform_device *dev)
843*4882a593Smuzhiyun {
844*4882a593Smuzhiyun struct uart_pxa_port *sport;
845*4882a593Smuzhiyun struct resource *mmres, *irqres;
846*4882a593Smuzhiyun int ret;
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
849*4882a593Smuzhiyun irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
850*4882a593Smuzhiyun if (!mmres || !irqres)
851*4882a593Smuzhiyun return -ENODEV;
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
854*4882a593Smuzhiyun if (!sport)
855*4882a593Smuzhiyun return -ENOMEM;
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun sport->clk = clk_get(&dev->dev, NULL);
858*4882a593Smuzhiyun if (IS_ERR(sport->clk)) {
859*4882a593Smuzhiyun ret = PTR_ERR(sport->clk);
860*4882a593Smuzhiyun goto err_free;
861*4882a593Smuzhiyun }
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun ret = clk_prepare(sport->clk);
864*4882a593Smuzhiyun if (ret) {
865*4882a593Smuzhiyun clk_put(sport->clk);
866*4882a593Smuzhiyun goto err_free;
867*4882a593Smuzhiyun }
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun sport->port.type = PORT_PXA;
870*4882a593Smuzhiyun sport->port.iotype = UPIO_MEM;
871*4882a593Smuzhiyun sport->port.mapbase = mmres->start;
872*4882a593Smuzhiyun sport->port.irq = irqres->start;
873*4882a593Smuzhiyun sport->port.fifosize = 64;
874*4882a593Smuzhiyun sport->port.ops = &serial_pxa_pops;
875*4882a593Smuzhiyun sport->port.dev = &dev->dev;
876*4882a593Smuzhiyun sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
877*4882a593Smuzhiyun sport->port.uartclk = clk_get_rate(sport->clk);
878*4882a593Smuzhiyun sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PXA_CONSOLE);
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun ret = serial_pxa_probe_dt(dev, sport);
881*4882a593Smuzhiyun if (ret > 0)
882*4882a593Smuzhiyun sport->port.line = dev->id;
883*4882a593Smuzhiyun else if (ret < 0)
884*4882a593Smuzhiyun goto err_clk;
885*4882a593Smuzhiyun if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) {
886*4882a593Smuzhiyun dev_err(&dev->dev, "serial%d out of range\n", sport->port.line);
887*4882a593Smuzhiyun ret = -EINVAL;
888*4882a593Smuzhiyun goto err_clk;
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun sport->port.membase = ioremap(mmres->start, resource_size(mmres));
893*4882a593Smuzhiyun if (!sport->port.membase) {
894*4882a593Smuzhiyun ret = -ENOMEM;
895*4882a593Smuzhiyun goto err_clk;
896*4882a593Smuzhiyun }
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun serial_pxa_ports[sport->port.line] = sport;
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun uart_add_one_port(&serial_pxa_reg, &sport->port);
901*4882a593Smuzhiyun platform_set_drvdata(dev, sport);
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun return 0;
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun err_clk:
906*4882a593Smuzhiyun clk_unprepare(sport->clk);
907*4882a593Smuzhiyun clk_put(sport->clk);
908*4882a593Smuzhiyun err_free:
909*4882a593Smuzhiyun kfree(sport);
910*4882a593Smuzhiyun return ret;
911*4882a593Smuzhiyun }
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun static struct platform_driver serial_pxa_driver = {
914*4882a593Smuzhiyun .probe = serial_pxa_probe,
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun .driver = {
917*4882a593Smuzhiyun .name = "pxa2xx-uart",
918*4882a593Smuzhiyun #ifdef CONFIG_PM
919*4882a593Smuzhiyun .pm = &serial_pxa_pm_ops,
920*4882a593Smuzhiyun #endif
921*4882a593Smuzhiyun .suppress_bind_attrs = true,
922*4882a593Smuzhiyun .of_match_table = serial_pxa_dt_ids,
923*4882a593Smuzhiyun },
924*4882a593Smuzhiyun };
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun /* 8250 driver for PXA serial ports should be used */
serial_pxa_init(void)928*4882a593Smuzhiyun static int __init serial_pxa_init(void)
929*4882a593Smuzhiyun {
930*4882a593Smuzhiyun int ret;
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun ret = uart_register_driver(&serial_pxa_reg);
933*4882a593Smuzhiyun if (ret != 0)
934*4882a593Smuzhiyun return ret;
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun ret = platform_driver_register(&serial_pxa_driver);
937*4882a593Smuzhiyun if (ret != 0)
938*4882a593Smuzhiyun uart_unregister_driver(&serial_pxa_reg);
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun return ret;
941*4882a593Smuzhiyun }
942*4882a593Smuzhiyun device_initcall(serial_pxa_init);
943