1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * UART driver for PNX8XXX SoCs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Per Hallsmark per.hallsmark@mvista.com
6*4882a593Smuzhiyun * Ported to 2.6 kernel by EmbeddedAlley
7*4882a593Smuzhiyun * Reworked by Vitaly Wool <vitalywool@gmail.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
10*4882a593Smuzhiyun * Copyright (C) 2000 Deep Blue Solutions Ltd.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/ioport.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/console.h>
17*4882a593Smuzhiyun #include <linux/sysrq.h>
18*4882a593Smuzhiyun #include <linux/device.h>
19*4882a593Smuzhiyun #include <linux/platform_device.h>
20*4882a593Smuzhiyun #include <linux/tty.h>
21*4882a593Smuzhiyun #include <linux/tty_flip.h>
22*4882a593Smuzhiyun #include <linux/serial_core.h>
23*4882a593Smuzhiyun #include <linux/serial.h>
24*4882a593Smuzhiyun #include <linux/serial_pnx8xxx.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <asm/io.h>
27*4882a593Smuzhiyun #include <asm/irq.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* We'll be using StrongARM sa1100 serial port major/minor */
30*4882a593Smuzhiyun #define SERIAL_PNX8XXX_MAJOR 204
31*4882a593Smuzhiyun #define MINOR_START 5
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define NR_PORTS 2
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define PNX8XXX_ISR_PASS_LIMIT 256
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * Convert from ignore_status_mask or read_status_mask to FIFO
39*4882a593Smuzhiyun * and interrupt status bits
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun #define SM_TO_FIFO(x) ((x) >> 10)
42*4882a593Smuzhiyun #define SM_TO_ISTAT(x) ((x) & 0x000001ff)
43*4882a593Smuzhiyun #define FIFO_TO_SM(x) ((x) << 10)
44*4882a593Smuzhiyun #define ISTAT_TO_SM(x) ((x) & 0x000001ff)
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * This is the size of our serial port register set.
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun #define UART_PORT_SIZE 0x1000
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * This determines how often we check the modem status signals
53*4882a593Smuzhiyun * for any change. They generally aren't connected to an IRQ
54*4882a593Smuzhiyun * so we have to poll them. We also check immediately before
55*4882a593Smuzhiyun * filling the TX fifo incase CTS has been dropped.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun #define MCTRL_TIMEOUT (250*HZ/1000)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun extern struct pnx8xxx_port pnx8xxx_ports[];
60*4882a593Smuzhiyun
serial_in(struct pnx8xxx_port * sport,int offset)61*4882a593Smuzhiyun static inline int serial_in(struct pnx8xxx_port *sport, int offset)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun return (__raw_readl(sport->port.membase + offset));
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
serial_out(struct pnx8xxx_port * sport,int offset,int value)66*4882a593Smuzhiyun static inline void serial_out(struct pnx8xxx_port *sport, int offset, int value)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun __raw_writel(value, sport->port.membase + offset);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun * Handle any change of modem status signal since we were last called.
73*4882a593Smuzhiyun */
pnx8xxx_mctrl_check(struct pnx8xxx_port * sport)74*4882a593Smuzhiyun static void pnx8xxx_mctrl_check(struct pnx8xxx_port *sport)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun unsigned int status, changed;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun status = sport->port.ops->get_mctrl(&sport->port);
79*4882a593Smuzhiyun changed = status ^ sport->old_status;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (changed == 0)
82*4882a593Smuzhiyun return;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun sport->old_status = status;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun if (changed & TIOCM_RI)
87*4882a593Smuzhiyun sport->port.icount.rng++;
88*4882a593Smuzhiyun if (changed & TIOCM_DSR)
89*4882a593Smuzhiyun sport->port.icount.dsr++;
90*4882a593Smuzhiyun if (changed & TIOCM_CAR)
91*4882a593Smuzhiyun uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
92*4882a593Smuzhiyun if (changed & TIOCM_CTS)
93*4882a593Smuzhiyun uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /*
99*4882a593Smuzhiyun * This is our per-port timeout handler, for checking the
100*4882a593Smuzhiyun * modem status signals.
101*4882a593Smuzhiyun */
pnx8xxx_timeout(struct timer_list * t)102*4882a593Smuzhiyun static void pnx8xxx_timeout(struct timer_list *t)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct pnx8xxx_port *sport = from_timer(sport, t, timer);
105*4882a593Smuzhiyun unsigned long flags;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun if (sport->port.state) {
108*4882a593Smuzhiyun spin_lock_irqsave(&sport->port.lock, flags);
109*4882a593Smuzhiyun pnx8xxx_mctrl_check(sport);
110*4882a593Smuzhiyun spin_unlock_irqrestore(&sport->port.lock, flags);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /*
117*4882a593Smuzhiyun * interrupts disabled on entry
118*4882a593Smuzhiyun */
pnx8xxx_stop_tx(struct uart_port * port)119*4882a593Smuzhiyun static void pnx8xxx_stop_tx(struct uart_port *port)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct pnx8xxx_port *sport =
122*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
123*4882a593Smuzhiyun u32 ien;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* Disable TX intr */
126*4882a593Smuzhiyun ien = serial_in(sport, PNX8XXX_IEN);
127*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, ien & ~PNX8XXX_UART_INT_ALLTX);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* Clear all pending TX intr */
130*4882a593Smuzhiyun serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLTX);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /*
134*4882a593Smuzhiyun * interrupts may not be disabled on entry
135*4882a593Smuzhiyun */
pnx8xxx_start_tx(struct uart_port * port)136*4882a593Smuzhiyun static void pnx8xxx_start_tx(struct uart_port *port)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct pnx8xxx_port *sport =
139*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
140*4882a593Smuzhiyun u32 ien;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /* Clear all pending TX intr */
143*4882a593Smuzhiyun serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLTX);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* Enable TX intr */
146*4882a593Smuzhiyun ien = serial_in(sport, PNX8XXX_IEN);
147*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, ien | PNX8XXX_UART_INT_ALLTX);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /*
151*4882a593Smuzhiyun * Interrupts enabled
152*4882a593Smuzhiyun */
pnx8xxx_stop_rx(struct uart_port * port)153*4882a593Smuzhiyun static void pnx8xxx_stop_rx(struct uart_port *port)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun struct pnx8xxx_port *sport =
156*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
157*4882a593Smuzhiyun u32 ien;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* Disable RX intr */
160*4882a593Smuzhiyun ien = serial_in(sport, PNX8XXX_IEN);
161*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, ien & ~PNX8XXX_UART_INT_ALLRX);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /* Clear all pending RX intr */
164*4882a593Smuzhiyun serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX);
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun /*
168*4882a593Smuzhiyun * Set the modem control timer to fire immediately.
169*4882a593Smuzhiyun */
pnx8xxx_enable_ms(struct uart_port * port)170*4882a593Smuzhiyun static void pnx8xxx_enable_ms(struct uart_port *port)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun struct pnx8xxx_port *sport =
173*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun mod_timer(&sport->timer, jiffies);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
pnx8xxx_rx_chars(struct pnx8xxx_port * sport)178*4882a593Smuzhiyun static void pnx8xxx_rx_chars(struct pnx8xxx_port *sport)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun unsigned int status, ch, flg;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun status = FIFO_TO_SM(serial_in(sport, PNX8XXX_FIFO)) |
183*4882a593Smuzhiyun ISTAT_TO_SM(serial_in(sport, PNX8XXX_ISTAT));
184*4882a593Smuzhiyun while (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFIFO)) {
185*4882a593Smuzhiyun ch = serial_in(sport, PNX8XXX_FIFO) & 0xff;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun sport->port.icount.rx++;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun flg = TTY_NORMAL;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /*
192*4882a593Smuzhiyun * note that the error handling code is
193*4882a593Smuzhiyun * out of the main execution path
194*4882a593Smuzhiyun */
195*4882a593Smuzhiyun if (status & (FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE |
196*4882a593Smuzhiyun PNX8XXX_UART_FIFO_RXPAR |
197*4882a593Smuzhiyun PNX8XXX_UART_FIFO_RXBRK) |
198*4882a593Smuzhiyun ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN))) {
199*4882a593Smuzhiyun if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXBRK)) {
200*4882a593Smuzhiyun status &= ~(FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
201*4882a593Smuzhiyun FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR));
202*4882a593Smuzhiyun sport->port.icount.brk++;
203*4882a593Smuzhiyun if (uart_handle_break(&sport->port))
204*4882a593Smuzhiyun goto ignore_char;
205*4882a593Smuzhiyun } else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR))
206*4882a593Smuzhiyun sport->port.icount.parity++;
207*4882a593Smuzhiyun else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE))
208*4882a593Smuzhiyun sport->port.icount.frame++;
209*4882a593Smuzhiyun if (status & ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN))
210*4882a593Smuzhiyun sport->port.icount.overrun++;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun status &= sport->port.read_status_mask;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR))
215*4882a593Smuzhiyun flg = TTY_PARITY;
216*4882a593Smuzhiyun else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE))
217*4882a593Smuzhiyun flg = TTY_FRAME;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun sport->port.sysrq = 0;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (uart_handle_sysrq_char(&sport->port, ch))
223*4882a593Smuzhiyun goto ignore_char;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun uart_insert_char(&sport->port, status,
226*4882a593Smuzhiyun ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN), ch, flg);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun ignore_char:
229*4882a593Smuzhiyun serial_out(sport, PNX8XXX_LCR, serial_in(sport, PNX8XXX_LCR) |
230*4882a593Smuzhiyun PNX8XXX_UART_LCR_RX_NEXT);
231*4882a593Smuzhiyun status = FIFO_TO_SM(serial_in(sport, PNX8XXX_FIFO)) |
232*4882a593Smuzhiyun ISTAT_TO_SM(serial_in(sport, PNX8XXX_ISTAT));
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun spin_unlock(&sport->port.lock);
236*4882a593Smuzhiyun tty_flip_buffer_push(&sport->port.state->port);
237*4882a593Smuzhiyun spin_lock(&sport->port.lock);
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
pnx8xxx_tx_chars(struct pnx8xxx_port * sport)240*4882a593Smuzhiyun static void pnx8xxx_tx_chars(struct pnx8xxx_port *sport)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun struct circ_buf *xmit = &sport->port.state->xmit;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun if (sport->port.x_char) {
245*4882a593Smuzhiyun serial_out(sport, PNX8XXX_FIFO, sport->port.x_char);
246*4882a593Smuzhiyun sport->port.icount.tx++;
247*4882a593Smuzhiyun sport->port.x_char = 0;
248*4882a593Smuzhiyun return;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /*
252*4882a593Smuzhiyun * Check the modem control lines before
253*4882a593Smuzhiyun * transmitting anything.
254*4882a593Smuzhiyun */
255*4882a593Smuzhiyun pnx8xxx_mctrl_check(sport);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
258*4882a593Smuzhiyun pnx8xxx_stop_tx(&sport->port);
259*4882a593Smuzhiyun return;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun /*
263*4882a593Smuzhiyun * TX while bytes available
264*4882a593Smuzhiyun */
265*4882a593Smuzhiyun while (((serial_in(sport, PNX8XXX_FIFO) &
266*4882a593Smuzhiyun PNX8XXX_UART_FIFO_TXFIFO) >> 16) < 16) {
267*4882a593Smuzhiyun serial_out(sport, PNX8XXX_FIFO, xmit->buf[xmit->tail]);
268*4882a593Smuzhiyun xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
269*4882a593Smuzhiyun sport->port.icount.tx++;
270*4882a593Smuzhiyun if (uart_circ_empty(xmit))
271*4882a593Smuzhiyun break;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
275*4882a593Smuzhiyun uart_write_wakeup(&sport->port);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun if (uart_circ_empty(xmit))
278*4882a593Smuzhiyun pnx8xxx_stop_tx(&sport->port);
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
pnx8xxx_int(int irq,void * dev_id)281*4882a593Smuzhiyun static irqreturn_t pnx8xxx_int(int irq, void *dev_id)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun struct pnx8xxx_port *sport = dev_id;
284*4882a593Smuzhiyun unsigned int status;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun spin_lock(&sport->port.lock);
287*4882a593Smuzhiyun /* Get the interrupts */
288*4882a593Smuzhiyun status = serial_in(sport, PNX8XXX_ISTAT) & serial_in(sport, PNX8XXX_IEN);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun /* Byte or break signal received */
291*4882a593Smuzhiyun if (status & (PNX8XXX_UART_INT_RX | PNX8XXX_UART_INT_BREAK))
292*4882a593Smuzhiyun pnx8xxx_rx_chars(sport);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun /* TX holding register empty - transmit a byte */
295*4882a593Smuzhiyun if (status & PNX8XXX_UART_INT_TX)
296*4882a593Smuzhiyun pnx8xxx_tx_chars(sport);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun /* Clear the ISTAT register */
299*4882a593Smuzhiyun serial_out(sport, PNX8XXX_ICLR, status);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun spin_unlock(&sport->port.lock);
302*4882a593Smuzhiyun return IRQ_HANDLED;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun /*
306*4882a593Smuzhiyun * Return TIOCSER_TEMT when transmitter is not busy.
307*4882a593Smuzhiyun */
pnx8xxx_tx_empty(struct uart_port * port)308*4882a593Smuzhiyun static unsigned int pnx8xxx_tx_empty(struct uart_port *port)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun struct pnx8xxx_port *sport =
311*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun return serial_in(sport, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO_STA ? 0 : TIOCSER_TEMT;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
pnx8xxx_get_mctrl(struct uart_port * port)316*4882a593Smuzhiyun static unsigned int pnx8xxx_get_mctrl(struct uart_port *port)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun struct pnx8xxx_port *sport =
319*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
320*4882a593Smuzhiyun unsigned int mctrl = TIOCM_DSR;
321*4882a593Smuzhiyun unsigned int msr;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun /* REVISIT */
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun msr = serial_in(sport, PNX8XXX_MCR);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun mctrl |= msr & PNX8XXX_UART_MCR_CTS ? TIOCM_CTS : 0;
328*4882a593Smuzhiyun mctrl |= msr & PNX8XXX_UART_MCR_DCD ? TIOCM_CAR : 0;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return mctrl;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
pnx8xxx_set_mctrl(struct uart_port * port,unsigned int mctrl)333*4882a593Smuzhiyun static void pnx8xxx_set_mctrl(struct uart_port *port, unsigned int mctrl)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun #if 0 /* FIXME */
336*4882a593Smuzhiyun struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
337*4882a593Smuzhiyun unsigned int msr;
338*4882a593Smuzhiyun #endif
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /*
342*4882a593Smuzhiyun * Interrupts always disabled.
343*4882a593Smuzhiyun */
pnx8xxx_break_ctl(struct uart_port * port,int break_state)344*4882a593Smuzhiyun static void pnx8xxx_break_ctl(struct uart_port *port, int break_state)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun struct pnx8xxx_port *sport =
347*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
348*4882a593Smuzhiyun unsigned long flags;
349*4882a593Smuzhiyun unsigned int lcr;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun spin_lock_irqsave(&sport->port.lock, flags);
352*4882a593Smuzhiyun lcr = serial_in(sport, PNX8XXX_LCR);
353*4882a593Smuzhiyun if (break_state == -1)
354*4882a593Smuzhiyun lcr |= PNX8XXX_UART_LCR_TXBREAK;
355*4882a593Smuzhiyun else
356*4882a593Smuzhiyun lcr &= ~PNX8XXX_UART_LCR_TXBREAK;
357*4882a593Smuzhiyun serial_out(sport, PNX8XXX_LCR, lcr);
358*4882a593Smuzhiyun spin_unlock_irqrestore(&sport->port.lock, flags);
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
pnx8xxx_startup(struct uart_port * port)361*4882a593Smuzhiyun static int pnx8xxx_startup(struct uart_port *port)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun struct pnx8xxx_port *sport =
364*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
365*4882a593Smuzhiyun int retval;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /*
368*4882a593Smuzhiyun * Allocate the IRQ
369*4882a593Smuzhiyun */
370*4882a593Smuzhiyun retval = request_irq(sport->port.irq, pnx8xxx_int, 0,
371*4882a593Smuzhiyun "pnx8xxx-uart", sport);
372*4882a593Smuzhiyun if (retval)
373*4882a593Smuzhiyun return retval;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun /*
376*4882a593Smuzhiyun * Finally, clear and enable interrupts
377*4882a593Smuzhiyun */
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX |
380*4882a593Smuzhiyun PNX8XXX_UART_INT_ALLTX);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, serial_in(sport, PNX8XXX_IEN) |
383*4882a593Smuzhiyun PNX8XXX_UART_INT_ALLRX |
384*4882a593Smuzhiyun PNX8XXX_UART_INT_ALLTX);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun /*
387*4882a593Smuzhiyun * Enable modem status interrupts
388*4882a593Smuzhiyun */
389*4882a593Smuzhiyun spin_lock_irq(&sport->port.lock);
390*4882a593Smuzhiyun pnx8xxx_enable_ms(&sport->port);
391*4882a593Smuzhiyun spin_unlock_irq(&sport->port.lock);
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun return 0;
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun
pnx8xxx_shutdown(struct uart_port * port)396*4882a593Smuzhiyun static void pnx8xxx_shutdown(struct uart_port *port)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun struct pnx8xxx_port *sport =
399*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
400*4882a593Smuzhiyun int lcr;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun /*
403*4882a593Smuzhiyun * Stop our timer.
404*4882a593Smuzhiyun */
405*4882a593Smuzhiyun del_timer_sync(&sport->timer);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /*
408*4882a593Smuzhiyun * Disable all interrupts
409*4882a593Smuzhiyun */
410*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, 0);
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun /*
413*4882a593Smuzhiyun * Reset the Tx and Rx FIFOS, disable the break condition
414*4882a593Smuzhiyun */
415*4882a593Smuzhiyun lcr = serial_in(sport, PNX8XXX_LCR);
416*4882a593Smuzhiyun lcr &= ~PNX8XXX_UART_LCR_TXBREAK;
417*4882a593Smuzhiyun lcr |= PNX8XXX_UART_LCR_TX_RST | PNX8XXX_UART_LCR_RX_RST;
418*4882a593Smuzhiyun serial_out(sport, PNX8XXX_LCR, lcr);
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun /*
421*4882a593Smuzhiyun * Clear all interrupts
422*4882a593Smuzhiyun */
423*4882a593Smuzhiyun serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX |
424*4882a593Smuzhiyun PNX8XXX_UART_INT_ALLTX);
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun /*
427*4882a593Smuzhiyun * Free the interrupt
428*4882a593Smuzhiyun */
429*4882a593Smuzhiyun free_irq(sport->port.irq, sport);
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun static void
pnx8xxx_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)433*4882a593Smuzhiyun pnx8xxx_set_termios(struct uart_port *port, struct ktermios *termios,
434*4882a593Smuzhiyun struct ktermios *old)
435*4882a593Smuzhiyun {
436*4882a593Smuzhiyun struct pnx8xxx_port *sport =
437*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
438*4882a593Smuzhiyun unsigned long flags;
439*4882a593Smuzhiyun unsigned int lcr_fcr, old_ien, baud, quot;
440*4882a593Smuzhiyun unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun /*
443*4882a593Smuzhiyun * We only support CS7 and CS8.
444*4882a593Smuzhiyun */
445*4882a593Smuzhiyun while ((termios->c_cflag & CSIZE) != CS7 &&
446*4882a593Smuzhiyun (termios->c_cflag & CSIZE) != CS8) {
447*4882a593Smuzhiyun termios->c_cflag &= ~CSIZE;
448*4882a593Smuzhiyun termios->c_cflag |= old_csize;
449*4882a593Smuzhiyun old_csize = CS8;
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun if ((termios->c_cflag & CSIZE) == CS8)
453*4882a593Smuzhiyun lcr_fcr = PNX8XXX_UART_LCR_8BIT;
454*4882a593Smuzhiyun else
455*4882a593Smuzhiyun lcr_fcr = 0;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun if (termios->c_cflag & CSTOPB)
458*4882a593Smuzhiyun lcr_fcr |= PNX8XXX_UART_LCR_2STOPB;
459*4882a593Smuzhiyun if (termios->c_cflag & PARENB) {
460*4882a593Smuzhiyun lcr_fcr |= PNX8XXX_UART_LCR_PAREN;
461*4882a593Smuzhiyun if (!(termios->c_cflag & PARODD))
462*4882a593Smuzhiyun lcr_fcr |= PNX8XXX_UART_LCR_PAREVN;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun /*
466*4882a593Smuzhiyun * Ask the core to calculate the divisor for us.
467*4882a593Smuzhiyun */
468*4882a593Smuzhiyun baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
469*4882a593Smuzhiyun quot = uart_get_divisor(port, baud);
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun spin_lock_irqsave(&sport->port.lock, flags);
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun sport->port.read_status_mask = ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN) |
474*4882a593Smuzhiyun ISTAT_TO_SM(PNX8XXX_UART_INT_EMPTY) |
475*4882a593Smuzhiyun ISTAT_TO_SM(PNX8XXX_UART_INT_RX);
476*4882a593Smuzhiyun if (termios->c_iflag & INPCK)
477*4882a593Smuzhiyun sport->port.read_status_mask |=
478*4882a593Smuzhiyun FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
479*4882a593Smuzhiyun FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR);
480*4882a593Smuzhiyun if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
481*4882a593Smuzhiyun sport->port.read_status_mask |=
482*4882a593Smuzhiyun ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun /*
485*4882a593Smuzhiyun * Characters to ignore
486*4882a593Smuzhiyun */
487*4882a593Smuzhiyun sport->port.ignore_status_mask = 0;
488*4882a593Smuzhiyun if (termios->c_iflag & IGNPAR)
489*4882a593Smuzhiyun sport->port.ignore_status_mask |=
490*4882a593Smuzhiyun FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
491*4882a593Smuzhiyun FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR);
492*4882a593Smuzhiyun if (termios->c_iflag & IGNBRK) {
493*4882a593Smuzhiyun sport->port.ignore_status_mask |=
494*4882a593Smuzhiyun ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK);
495*4882a593Smuzhiyun /*
496*4882a593Smuzhiyun * If we're ignoring parity and break indicators,
497*4882a593Smuzhiyun * ignore overruns too (for real raw support).
498*4882a593Smuzhiyun */
499*4882a593Smuzhiyun if (termios->c_iflag & IGNPAR)
500*4882a593Smuzhiyun sport->port.ignore_status_mask |=
501*4882a593Smuzhiyun ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN);
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /*
505*4882a593Smuzhiyun * ignore all characters if CREAD is not set
506*4882a593Smuzhiyun */
507*4882a593Smuzhiyun if ((termios->c_cflag & CREAD) == 0)
508*4882a593Smuzhiyun sport->port.ignore_status_mask |=
509*4882a593Smuzhiyun ISTAT_TO_SM(PNX8XXX_UART_INT_RX);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun del_timer_sync(&sport->timer);
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun /*
514*4882a593Smuzhiyun * Update the per-port timeout.
515*4882a593Smuzhiyun */
516*4882a593Smuzhiyun uart_update_timeout(port, termios->c_cflag, baud);
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun /*
519*4882a593Smuzhiyun * disable interrupts and drain transmitter
520*4882a593Smuzhiyun */
521*4882a593Smuzhiyun old_ien = serial_in(sport, PNX8XXX_IEN);
522*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, old_ien & ~(PNX8XXX_UART_INT_ALLTX |
523*4882a593Smuzhiyun PNX8XXX_UART_INT_ALLRX));
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun while (serial_in(sport, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO_STA)
526*4882a593Smuzhiyun barrier();
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun /* then, disable everything */
529*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, 0);
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun /* Reset the Rx and Tx FIFOs too */
532*4882a593Smuzhiyun lcr_fcr |= PNX8XXX_UART_LCR_TX_RST;
533*4882a593Smuzhiyun lcr_fcr |= PNX8XXX_UART_LCR_RX_RST;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun /* set the parity, stop bits and data size */
536*4882a593Smuzhiyun serial_out(sport, PNX8XXX_LCR, lcr_fcr);
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun /* set the baud rate */
539*4882a593Smuzhiyun quot -= 1;
540*4882a593Smuzhiyun serial_out(sport, PNX8XXX_BAUD, quot);
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun serial_out(sport, PNX8XXX_ICLR, -1);
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, old_ien);
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
547*4882a593Smuzhiyun pnx8xxx_enable_ms(&sport->port);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun spin_unlock_irqrestore(&sport->port.lock, flags);
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun
pnx8xxx_type(struct uart_port * port)552*4882a593Smuzhiyun static const char *pnx8xxx_type(struct uart_port *port)
553*4882a593Smuzhiyun {
554*4882a593Smuzhiyun struct pnx8xxx_port *sport =
555*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun return sport->port.type == PORT_PNX8XXX ? "PNX8XXX" : NULL;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun /*
561*4882a593Smuzhiyun * Release the memory region(s) being used by 'port'.
562*4882a593Smuzhiyun */
pnx8xxx_release_port(struct uart_port * port)563*4882a593Smuzhiyun static void pnx8xxx_release_port(struct uart_port *port)
564*4882a593Smuzhiyun {
565*4882a593Smuzhiyun struct pnx8xxx_port *sport =
566*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
569*4882a593Smuzhiyun }
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun /*
572*4882a593Smuzhiyun * Request the memory region(s) being used by 'port'.
573*4882a593Smuzhiyun */
pnx8xxx_request_port(struct uart_port * port)574*4882a593Smuzhiyun static int pnx8xxx_request_port(struct uart_port *port)
575*4882a593Smuzhiyun {
576*4882a593Smuzhiyun struct pnx8xxx_port *sport =
577*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
578*4882a593Smuzhiyun return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
579*4882a593Smuzhiyun "pnx8xxx-uart") != NULL ? 0 : -EBUSY;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun /*
583*4882a593Smuzhiyun * Configure/autoconfigure the port.
584*4882a593Smuzhiyun */
pnx8xxx_config_port(struct uart_port * port,int flags)585*4882a593Smuzhiyun static void pnx8xxx_config_port(struct uart_port *port, int flags)
586*4882a593Smuzhiyun {
587*4882a593Smuzhiyun struct pnx8xxx_port *sport =
588*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun if (flags & UART_CONFIG_TYPE &&
591*4882a593Smuzhiyun pnx8xxx_request_port(&sport->port) == 0)
592*4882a593Smuzhiyun sport->port.type = PORT_PNX8XXX;
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun /*
596*4882a593Smuzhiyun * Verify the new serial_struct (for TIOCSSERIAL).
597*4882a593Smuzhiyun * The only change we allow are to the flags and type, and
598*4882a593Smuzhiyun * even then only between PORT_PNX8XXX and PORT_UNKNOWN
599*4882a593Smuzhiyun */
600*4882a593Smuzhiyun static int
pnx8xxx_verify_port(struct uart_port * port,struct serial_struct * ser)601*4882a593Smuzhiyun pnx8xxx_verify_port(struct uart_port *port, struct serial_struct *ser)
602*4882a593Smuzhiyun {
603*4882a593Smuzhiyun struct pnx8xxx_port *sport =
604*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
605*4882a593Smuzhiyun int ret = 0;
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun if (ser->type != PORT_UNKNOWN && ser->type != PORT_PNX8XXX)
608*4882a593Smuzhiyun ret = -EINVAL;
609*4882a593Smuzhiyun if (sport->port.irq != ser->irq)
610*4882a593Smuzhiyun ret = -EINVAL;
611*4882a593Smuzhiyun if (ser->io_type != SERIAL_IO_MEM)
612*4882a593Smuzhiyun ret = -EINVAL;
613*4882a593Smuzhiyun if (sport->port.uartclk / 16 != ser->baud_base)
614*4882a593Smuzhiyun ret = -EINVAL;
615*4882a593Smuzhiyun if ((void *)sport->port.mapbase != ser->iomem_base)
616*4882a593Smuzhiyun ret = -EINVAL;
617*4882a593Smuzhiyun if (sport->port.iobase != ser->port)
618*4882a593Smuzhiyun ret = -EINVAL;
619*4882a593Smuzhiyun if (ser->hub6 != 0)
620*4882a593Smuzhiyun ret = -EINVAL;
621*4882a593Smuzhiyun return ret;
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun static const struct uart_ops pnx8xxx_pops = {
625*4882a593Smuzhiyun .tx_empty = pnx8xxx_tx_empty,
626*4882a593Smuzhiyun .set_mctrl = pnx8xxx_set_mctrl,
627*4882a593Smuzhiyun .get_mctrl = pnx8xxx_get_mctrl,
628*4882a593Smuzhiyun .stop_tx = pnx8xxx_stop_tx,
629*4882a593Smuzhiyun .start_tx = pnx8xxx_start_tx,
630*4882a593Smuzhiyun .stop_rx = pnx8xxx_stop_rx,
631*4882a593Smuzhiyun .enable_ms = pnx8xxx_enable_ms,
632*4882a593Smuzhiyun .break_ctl = pnx8xxx_break_ctl,
633*4882a593Smuzhiyun .startup = pnx8xxx_startup,
634*4882a593Smuzhiyun .shutdown = pnx8xxx_shutdown,
635*4882a593Smuzhiyun .set_termios = pnx8xxx_set_termios,
636*4882a593Smuzhiyun .type = pnx8xxx_type,
637*4882a593Smuzhiyun .release_port = pnx8xxx_release_port,
638*4882a593Smuzhiyun .request_port = pnx8xxx_request_port,
639*4882a593Smuzhiyun .config_port = pnx8xxx_config_port,
640*4882a593Smuzhiyun .verify_port = pnx8xxx_verify_port,
641*4882a593Smuzhiyun };
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun /*
645*4882a593Smuzhiyun * Setup the PNX8XXX serial ports.
646*4882a593Smuzhiyun *
647*4882a593Smuzhiyun * Note also that we support "console=ttySx" where "x" is either 0 or 1.
648*4882a593Smuzhiyun */
pnx8xxx_init_ports(void)649*4882a593Smuzhiyun static void __init pnx8xxx_init_ports(void)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun static int first = 1;
652*4882a593Smuzhiyun int i;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun if (!first)
655*4882a593Smuzhiyun return;
656*4882a593Smuzhiyun first = 0;
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun for (i = 0; i < NR_PORTS; i++) {
659*4882a593Smuzhiyun timer_setup(&pnx8xxx_ports[i].timer, pnx8xxx_timeout, 0);
660*4882a593Smuzhiyun pnx8xxx_ports[i].port.ops = &pnx8xxx_pops;
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_PNX8XXX_CONSOLE
665*4882a593Smuzhiyun
pnx8xxx_console_putchar(struct uart_port * port,int ch)666*4882a593Smuzhiyun static void pnx8xxx_console_putchar(struct uart_port *port, int ch)
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun struct pnx8xxx_port *sport =
669*4882a593Smuzhiyun container_of(port, struct pnx8xxx_port, port);
670*4882a593Smuzhiyun int status;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun do {
673*4882a593Smuzhiyun /* Wait for UART_TX register to empty */
674*4882a593Smuzhiyun status = serial_in(sport, PNX8XXX_FIFO);
675*4882a593Smuzhiyun } while (status & PNX8XXX_UART_FIFO_TXFIFO);
676*4882a593Smuzhiyun serial_out(sport, PNX8XXX_FIFO, ch);
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun /*
680*4882a593Smuzhiyun * Interrupts are disabled on entering
681*4882a593Smuzhiyun */static void
pnx8xxx_console_write(struct console * co,const char * s,unsigned int count)682*4882a593Smuzhiyun pnx8xxx_console_write(struct console *co, const char *s, unsigned int count)
683*4882a593Smuzhiyun {
684*4882a593Smuzhiyun struct pnx8xxx_port *sport = &pnx8xxx_ports[co->index];
685*4882a593Smuzhiyun unsigned int old_ien, status;
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun /*
688*4882a593Smuzhiyun * First, save IEN and then disable interrupts
689*4882a593Smuzhiyun */
690*4882a593Smuzhiyun old_ien = serial_in(sport, PNX8XXX_IEN);
691*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, old_ien & ~(PNX8XXX_UART_INT_ALLTX |
692*4882a593Smuzhiyun PNX8XXX_UART_INT_ALLRX));
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun uart_console_write(&sport->port, s, count, pnx8xxx_console_putchar);
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun /*
697*4882a593Smuzhiyun * Finally, wait for transmitter to become empty
698*4882a593Smuzhiyun * and restore IEN
699*4882a593Smuzhiyun */
700*4882a593Smuzhiyun do {
701*4882a593Smuzhiyun /* Wait for UART_TX register to empty */
702*4882a593Smuzhiyun status = serial_in(sport, PNX8XXX_FIFO);
703*4882a593Smuzhiyun } while (status & PNX8XXX_UART_FIFO_TXFIFO);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun /* Clear TX and EMPTY interrupt */
706*4882a593Smuzhiyun serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_TX |
707*4882a593Smuzhiyun PNX8XXX_UART_INT_EMPTY);
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun serial_out(sport, PNX8XXX_IEN, old_ien);
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun static int __init
pnx8xxx_console_setup(struct console * co,char * options)713*4882a593Smuzhiyun pnx8xxx_console_setup(struct console *co, char *options)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun struct pnx8xxx_port *sport;
716*4882a593Smuzhiyun int baud = 38400;
717*4882a593Smuzhiyun int bits = 8;
718*4882a593Smuzhiyun int parity = 'n';
719*4882a593Smuzhiyun int flow = 'n';
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun /*
722*4882a593Smuzhiyun * Check whether an invalid uart number has been specified, and
723*4882a593Smuzhiyun * if so, search for the first available port that does have
724*4882a593Smuzhiyun * console support.
725*4882a593Smuzhiyun */
726*4882a593Smuzhiyun if (co->index == -1 || co->index >= NR_PORTS)
727*4882a593Smuzhiyun co->index = 0;
728*4882a593Smuzhiyun sport = &pnx8xxx_ports[co->index];
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun if (options)
731*4882a593Smuzhiyun uart_parse_options(options, &baud, &parity, &bits, &flow);
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun return uart_set_options(&sport->port, co, baud, parity, bits, flow);
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun static struct uart_driver pnx8xxx_reg;
737*4882a593Smuzhiyun static struct console pnx8xxx_console = {
738*4882a593Smuzhiyun .name = "ttyS",
739*4882a593Smuzhiyun .write = pnx8xxx_console_write,
740*4882a593Smuzhiyun .device = uart_console_device,
741*4882a593Smuzhiyun .setup = pnx8xxx_console_setup,
742*4882a593Smuzhiyun .flags = CON_PRINTBUFFER,
743*4882a593Smuzhiyun .index = -1,
744*4882a593Smuzhiyun .data = &pnx8xxx_reg,
745*4882a593Smuzhiyun };
746*4882a593Smuzhiyun
pnx8xxx_rs_console_init(void)747*4882a593Smuzhiyun static int __init pnx8xxx_rs_console_init(void)
748*4882a593Smuzhiyun {
749*4882a593Smuzhiyun pnx8xxx_init_ports();
750*4882a593Smuzhiyun register_console(&pnx8xxx_console);
751*4882a593Smuzhiyun return 0;
752*4882a593Smuzhiyun }
753*4882a593Smuzhiyun console_initcall(pnx8xxx_rs_console_init);
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun #define PNX8XXX_CONSOLE &pnx8xxx_console
756*4882a593Smuzhiyun #else
757*4882a593Smuzhiyun #define PNX8XXX_CONSOLE NULL
758*4882a593Smuzhiyun #endif
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun static struct uart_driver pnx8xxx_reg = {
761*4882a593Smuzhiyun .owner = THIS_MODULE,
762*4882a593Smuzhiyun .driver_name = "ttyS",
763*4882a593Smuzhiyun .dev_name = "ttyS",
764*4882a593Smuzhiyun .major = SERIAL_PNX8XXX_MAJOR,
765*4882a593Smuzhiyun .minor = MINOR_START,
766*4882a593Smuzhiyun .nr = NR_PORTS,
767*4882a593Smuzhiyun .cons = PNX8XXX_CONSOLE,
768*4882a593Smuzhiyun };
769*4882a593Smuzhiyun
pnx8xxx_serial_suspend(struct platform_device * pdev,pm_message_t state)770*4882a593Smuzhiyun static int pnx8xxx_serial_suspend(struct platform_device *pdev, pm_message_t state)
771*4882a593Smuzhiyun {
772*4882a593Smuzhiyun struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun return uart_suspend_port(&pnx8xxx_reg, &sport->port);
775*4882a593Smuzhiyun }
776*4882a593Smuzhiyun
pnx8xxx_serial_resume(struct platform_device * pdev)777*4882a593Smuzhiyun static int pnx8xxx_serial_resume(struct platform_device *pdev)
778*4882a593Smuzhiyun {
779*4882a593Smuzhiyun struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun return uart_resume_port(&pnx8xxx_reg, &sport->port);
782*4882a593Smuzhiyun }
783*4882a593Smuzhiyun
pnx8xxx_serial_probe(struct platform_device * pdev)784*4882a593Smuzhiyun static int pnx8xxx_serial_probe(struct platform_device *pdev)
785*4882a593Smuzhiyun {
786*4882a593Smuzhiyun struct resource *res = pdev->resource;
787*4882a593Smuzhiyun int i;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun for (i = 0; i < pdev->num_resources; i++, res++) {
790*4882a593Smuzhiyun if (!(res->flags & IORESOURCE_MEM))
791*4882a593Smuzhiyun continue;
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun for (i = 0; i < NR_PORTS; i++) {
794*4882a593Smuzhiyun if (pnx8xxx_ports[i].port.mapbase != res->start)
795*4882a593Smuzhiyun continue;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun pnx8xxx_ports[i].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PNX8XXX_CONSOLE);
798*4882a593Smuzhiyun pnx8xxx_ports[i].port.dev = &pdev->dev;
799*4882a593Smuzhiyun uart_add_one_port(&pnx8xxx_reg, &pnx8xxx_ports[i].port);
800*4882a593Smuzhiyun platform_set_drvdata(pdev, &pnx8xxx_ports[i]);
801*4882a593Smuzhiyun break;
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun return 0;
806*4882a593Smuzhiyun }
807*4882a593Smuzhiyun
pnx8xxx_serial_remove(struct platform_device * pdev)808*4882a593Smuzhiyun static int pnx8xxx_serial_remove(struct platform_device *pdev)
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun if (sport)
813*4882a593Smuzhiyun uart_remove_one_port(&pnx8xxx_reg, &sport->port);
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun return 0;
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun static struct platform_driver pnx8xxx_serial_driver = {
819*4882a593Smuzhiyun .driver = {
820*4882a593Smuzhiyun .name = "pnx8xxx-uart",
821*4882a593Smuzhiyun },
822*4882a593Smuzhiyun .probe = pnx8xxx_serial_probe,
823*4882a593Smuzhiyun .remove = pnx8xxx_serial_remove,
824*4882a593Smuzhiyun .suspend = pnx8xxx_serial_suspend,
825*4882a593Smuzhiyun .resume = pnx8xxx_serial_resume,
826*4882a593Smuzhiyun };
827*4882a593Smuzhiyun
pnx8xxx_serial_init(void)828*4882a593Smuzhiyun static int __init pnx8xxx_serial_init(void)
829*4882a593Smuzhiyun {
830*4882a593Smuzhiyun int ret;
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun printk(KERN_INFO "Serial: PNX8XXX driver\n");
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun pnx8xxx_init_ports();
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun ret = uart_register_driver(&pnx8xxx_reg);
837*4882a593Smuzhiyun if (ret == 0) {
838*4882a593Smuzhiyun ret = platform_driver_register(&pnx8xxx_serial_driver);
839*4882a593Smuzhiyun if (ret)
840*4882a593Smuzhiyun uart_unregister_driver(&pnx8xxx_reg);
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun return ret;
843*4882a593Smuzhiyun }
844*4882a593Smuzhiyun
pnx8xxx_serial_exit(void)845*4882a593Smuzhiyun static void __exit pnx8xxx_serial_exit(void)
846*4882a593Smuzhiyun {
847*4882a593Smuzhiyun platform_driver_unregister(&pnx8xxx_serial_driver);
848*4882a593Smuzhiyun uart_unregister_driver(&pnx8xxx_reg);
849*4882a593Smuzhiyun }
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun module_init(pnx8xxx_serial_init);
852*4882a593Smuzhiyun module_exit(pnx8xxx_serial_exit);
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun MODULE_AUTHOR("Embedded Alley Solutions, Inc.");
855*4882a593Smuzhiyun MODULE_DESCRIPTION("PNX8XXX SoCs serial port driver");
856*4882a593Smuzhiyun MODULE_LICENSE("GPL");
857*4882a593Smuzhiyun MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_PNX8XXX_MAJOR);
858*4882a593Smuzhiyun MODULE_ALIAS("platform:pnx8xxx-uart");
859