1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * PIC32 Integrated Serial Driver.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015 Microchip Technology, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Authors:
8*4882a593Smuzhiyun * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #ifndef __DT_PIC32_UART_H__
11*4882a593Smuzhiyun #define __DT_PIC32_UART_H__
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define PIC32_UART_DFLT_BRATE (9600)
14*4882a593Smuzhiyun #define PIC32_UART_TX_FIFO_DEPTH (8)
15*4882a593Smuzhiyun #define PIC32_UART_RX_FIFO_DEPTH (8)
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define PIC32_UART_MODE 0x00
18*4882a593Smuzhiyun #define PIC32_UART_STA 0x10
19*4882a593Smuzhiyun #define PIC32_UART_TX 0x20
20*4882a593Smuzhiyun #define PIC32_UART_RX 0x30
21*4882a593Smuzhiyun #define PIC32_UART_BRG 0x40
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct pic32_console_opt {
24*4882a593Smuzhiyun int baud;
25*4882a593Smuzhiyun int parity;
26*4882a593Smuzhiyun int bits;
27*4882a593Smuzhiyun int flow;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* struct pic32_sport - pic32 serial port descriptor
31*4882a593Smuzhiyun * @port: uart port descriptor
32*4882a593Smuzhiyun * @idx: port index
33*4882a593Smuzhiyun * @irq_fault: virtual fault interrupt number
34*4882a593Smuzhiyun * @irqflags_fault: flags related to fault irq
35*4882a593Smuzhiyun * @irq_fault_name: irq fault name
36*4882a593Smuzhiyun * @irq_rx: virtual rx interrupt number
37*4882a593Smuzhiyun * @irqflags_rx: flags related to rx irq
38*4882a593Smuzhiyun * @irq_rx_name: irq rx name
39*4882a593Smuzhiyun * @irq_tx: virtual tx interrupt number
40*4882a593Smuzhiyun * @irqflags_tx: : flags related to tx irq
41*4882a593Smuzhiyun * @irq_tx_name: irq tx name
42*4882a593Smuzhiyun * @cts_gpio: clear to send gpio
43*4882a593Smuzhiyun * @dev: device descriptor
44*4882a593Smuzhiyun **/
45*4882a593Smuzhiyun struct pic32_sport {
46*4882a593Smuzhiyun struct uart_port port;
47*4882a593Smuzhiyun struct pic32_console_opt opt;
48*4882a593Smuzhiyun int idx;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun int irq_fault;
51*4882a593Smuzhiyun int irqflags_fault;
52*4882a593Smuzhiyun const char *irq_fault_name;
53*4882a593Smuzhiyun int irq_rx;
54*4882a593Smuzhiyun int irqflags_rx;
55*4882a593Smuzhiyun const char *irq_rx_name;
56*4882a593Smuzhiyun int irq_tx;
57*4882a593Smuzhiyun int irqflags_tx;
58*4882a593Smuzhiyun const char *irq_tx_name;
59*4882a593Smuzhiyun u8 enable_tx_irq;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun bool hw_flow_ctrl;
62*4882a593Smuzhiyun int cts_gpio;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun int ref_clk;
65*4882a593Smuzhiyun struct clk *clk;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun struct device *dev;
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun #define to_pic32_sport(c) container_of(c, struct pic32_sport, port)
70*4882a593Smuzhiyun #define pic32_get_port(sport) (&sport->port)
71*4882a593Smuzhiyun #define pic32_get_opt(sport) (&sport->opt)
72*4882a593Smuzhiyun #define tx_irq_enabled(sport) (sport->enable_tx_irq)
73*4882a593Smuzhiyun
pic32_uart_writel(struct pic32_sport * sport,u32 reg,u32 val)74*4882a593Smuzhiyun static inline void pic32_uart_writel(struct pic32_sport *sport,
75*4882a593Smuzhiyun u32 reg, u32 val)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct uart_port *port = pic32_get_port(sport);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun __raw_writel(val, port->membase + reg);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
pic32_uart_readl(struct pic32_sport * sport,u32 reg)82*4882a593Smuzhiyun static inline u32 pic32_uart_readl(struct pic32_sport *sport, u32 reg)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct uart_port *port = pic32_get_port(sport);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return __raw_readl(port->membase + reg);
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* pic32 uart mode register bits */
90*4882a593Smuzhiyun #define PIC32_UART_MODE_ON BIT(15)
91*4882a593Smuzhiyun #define PIC32_UART_MODE_FRZ BIT(14)
92*4882a593Smuzhiyun #define PIC32_UART_MODE_SIDL BIT(13)
93*4882a593Smuzhiyun #define PIC32_UART_MODE_IREN BIT(12)
94*4882a593Smuzhiyun #define PIC32_UART_MODE_RTSMD BIT(11)
95*4882a593Smuzhiyun #define PIC32_UART_MODE_RESV1 BIT(10)
96*4882a593Smuzhiyun #define PIC32_UART_MODE_UEN1 BIT(9)
97*4882a593Smuzhiyun #define PIC32_UART_MODE_UEN0 BIT(8)
98*4882a593Smuzhiyun #define PIC32_UART_MODE_WAKE BIT(7)
99*4882a593Smuzhiyun #define PIC32_UART_MODE_LPBK BIT(6)
100*4882a593Smuzhiyun #define PIC32_UART_MODE_ABAUD BIT(5)
101*4882a593Smuzhiyun #define PIC32_UART_MODE_RXINV BIT(4)
102*4882a593Smuzhiyun #define PIC32_UART_MODE_BRGH BIT(3)
103*4882a593Smuzhiyun #define PIC32_UART_MODE_PDSEL1 BIT(2)
104*4882a593Smuzhiyun #define PIC32_UART_MODE_PDSEL0 BIT(1)
105*4882a593Smuzhiyun #define PIC32_UART_MODE_STSEL BIT(0)
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* pic32 uart status register bits */
108*4882a593Smuzhiyun #define PIC32_UART_STA_UTXISEL1 BIT(15)
109*4882a593Smuzhiyun #define PIC32_UART_STA_UTXISEL0 BIT(14)
110*4882a593Smuzhiyun #define PIC32_UART_STA_UTXINV BIT(13)
111*4882a593Smuzhiyun #define PIC32_UART_STA_URXEN BIT(12)
112*4882a593Smuzhiyun #define PIC32_UART_STA_UTXBRK BIT(11)
113*4882a593Smuzhiyun #define PIC32_UART_STA_UTXEN BIT(10)
114*4882a593Smuzhiyun #define PIC32_UART_STA_UTXBF BIT(9)
115*4882a593Smuzhiyun #define PIC32_UART_STA_TRMT BIT(8)
116*4882a593Smuzhiyun #define PIC32_UART_STA_URXISEL1 BIT(7)
117*4882a593Smuzhiyun #define PIC32_UART_STA_URXISEL0 BIT(6)
118*4882a593Smuzhiyun #define PIC32_UART_STA_ADDEN BIT(5)
119*4882a593Smuzhiyun #define PIC32_UART_STA_RIDLE BIT(4)
120*4882a593Smuzhiyun #define PIC32_UART_STA_PERR BIT(3)
121*4882a593Smuzhiyun #define PIC32_UART_STA_FERR BIT(2)
122*4882a593Smuzhiyun #define PIC32_UART_STA_OERR BIT(1)
123*4882a593Smuzhiyun #define PIC32_UART_STA_URXDA BIT(0)
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun #endif /* __DT_PIC32_UART_H__ */
126