xref: /OK3568_Linux_fs/kernel/drivers/tty/serial/max3100.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright (C) 2008 Christian Pellegrin <chripell@evolware.org>
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Notes: the MAX3100 doesn't provide an interrupt on CTS so we have
7*4882a593Smuzhiyun  * to use polling for flow control. TX empty IRQ is unusable, since
8*4882a593Smuzhiyun  * writing conf clears FIFO buffer and we cannot have this interrupt
9*4882a593Smuzhiyun  * always asking us for attention.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Example platform data:
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun  static struct plat_max3100 max3100_plat_data = {
14*4882a593Smuzhiyun  .loopback = 0,
15*4882a593Smuzhiyun  .crystal = 0,
16*4882a593Smuzhiyun  .poll_time = 100,
17*4882a593Smuzhiyun  };
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun  static struct spi_board_info spi_board_info[] = {
20*4882a593Smuzhiyun  {
21*4882a593Smuzhiyun  .modalias	= "max3100",
22*4882a593Smuzhiyun  .platform_data	= &max3100_plat_data,
23*4882a593Smuzhiyun  .irq		= IRQ_EINT12,
24*4882a593Smuzhiyun  .max_speed_hz	= 5*1000*1000,
25*4882a593Smuzhiyun  .chip_select	= 0,
26*4882a593Smuzhiyun  },
27*4882a593Smuzhiyun  };
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun  * The initial minor number is 209 in the low-density serial port:
30*4882a593Smuzhiyun  * mknod /dev/ttyMAX0 c 204 209
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define MAX3100_MAJOR 204
34*4882a593Smuzhiyun #define MAX3100_MINOR 209
35*4882a593Smuzhiyun /* 4 MAX3100s should be enough for everyone */
36*4882a593Smuzhiyun #define MAX_MAX3100 4
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #include <linux/delay.h>
39*4882a593Smuzhiyun #include <linux/slab.h>
40*4882a593Smuzhiyun #include <linux/device.h>
41*4882a593Smuzhiyun #include <linux/module.h>
42*4882a593Smuzhiyun #include <linux/serial_core.h>
43*4882a593Smuzhiyun #include <linux/serial.h>
44*4882a593Smuzhiyun #include <linux/spi/spi.h>
45*4882a593Smuzhiyun #include <linux/freezer.h>
46*4882a593Smuzhiyun #include <linux/tty.h>
47*4882a593Smuzhiyun #include <linux/tty_flip.h>
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun #include <linux/serial_max3100.h>
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define MAX3100_C    (1<<14)
52*4882a593Smuzhiyun #define MAX3100_D    (0<<14)
53*4882a593Smuzhiyun #define MAX3100_W    (1<<15)
54*4882a593Smuzhiyun #define MAX3100_RX   (0<<15)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define MAX3100_WC   (MAX3100_W  | MAX3100_C)
57*4882a593Smuzhiyun #define MAX3100_RC   (MAX3100_RX | MAX3100_C)
58*4882a593Smuzhiyun #define MAX3100_WD   (MAX3100_W  | MAX3100_D)
59*4882a593Smuzhiyun #define MAX3100_RD   (MAX3100_RX | MAX3100_D)
60*4882a593Smuzhiyun #define MAX3100_CMD  (3 << 14)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define MAX3100_T    (1<<14)
63*4882a593Smuzhiyun #define MAX3100_R    (1<<15)
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define MAX3100_FEN  (1<<13)
66*4882a593Smuzhiyun #define MAX3100_SHDN (1<<12)
67*4882a593Smuzhiyun #define MAX3100_TM   (1<<11)
68*4882a593Smuzhiyun #define MAX3100_RM   (1<<10)
69*4882a593Smuzhiyun #define MAX3100_PM   (1<<9)
70*4882a593Smuzhiyun #define MAX3100_RAM  (1<<8)
71*4882a593Smuzhiyun #define MAX3100_IR   (1<<7)
72*4882a593Smuzhiyun #define MAX3100_ST   (1<<6)
73*4882a593Smuzhiyun #define MAX3100_PE   (1<<5)
74*4882a593Smuzhiyun #define MAX3100_L    (1<<4)
75*4882a593Smuzhiyun #define MAX3100_BAUD (0xf)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define MAX3100_TE   (1<<10)
78*4882a593Smuzhiyun #define MAX3100_RAFE (1<<10)
79*4882a593Smuzhiyun #define MAX3100_RTS  (1<<9)
80*4882a593Smuzhiyun #define MAX3100_CTS  (1<<9)
81*4882a593Smuzhiyun #define MAX3100_PT   (1<<8)
82*4882a593Smuzhiyun #define MAX3100_DATA (0xff)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define MAX3100_RT   (MAX3100_R | MAX3100_T)
85*4882a593Smuzhiyun #define MAX3100_RTC  (MAX3100_RT | MAX3100_CTS | MAX3100_RAFE)
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun /* the following simulate a status reg for ignore_status_mask */
88*4882a593Smuzhiyun #define MAX3100_STATUS_PE 1
89*4882a593Smuzhiyun #define MAX3100_STATUS_FE 2
90*4882a593Smuzhiyun #define MAX3100_STATUS_OE 4
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun struct max3100_port {
93*4882a593Smuzhiyun 	struct uart_port port;
94*4882a593Smuzhiyun 	struct spi_device *spi;
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	int cts;	        /* last CTS received for flow ctrl */
97*4882a593Smuzhiyun 	int tx_empty;		/* last TX empty bit */
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	spinlock_t conf_lock;	/* shared data */
100*4882a593Smuzhiyun 	int conf_commit;	/* need to make changes */
101*4882a593Smuzhiyun 	int conf;		/* configuration for the MAX31000
102*4882a593Smuzhiyun 				 * (bits 0-7, bits 8-11 are irqs) */
103*4882a593Smuzhiyun 	int rts_commit;	        /* need to change rts */
104*4882a593Smuzhiyun 	int rts;		/* rts status */
105*4882a593Smuzhiyun 	int baud;		/* current baud rate */
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	int parity;		/* keeps track if we should send parity */
108*4882a593Smuzhiyun #define MAX3100_PARITY_ON 1
109*4882a593Smuzhiyun #define MAX3100_PARITY_ODD 2
110*4882a593Smuzhiyun #define MAX3100_7BIT 4
111*4882a593Smuzhiyun 	int rx_enabled;	        /* if we should rx chars */
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	int irq;		/* irq assigned to the max3100 */
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	int minor;		/* minor number */
116*4882a593Smuzhiyun 	int crystal;		/* 1 if 3.6864Mhz crystal 0 for 1.8432 */
117*4882a593Smuzhiyun 	int loopback;		/* 1 if we are in loopback mode */
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	/* for handling irqs: need workqueue since we do spi_sync */
120*4882a593Smuzhiyun 	struct workqueue_struct *workqueue;
121*4882a593Smuzhiyun 	struct work_struct work;
122*4882a593Smuzhiyun 	/* set to 1 to make the workhandler exit as soon as possible */
123*4882a593Smuzhiyun 	int  force_end_work;
124*4882a593Smuzhiyun 	/* need to know we are suspending to avoid deadlock on workqueue */
125*4882a593Smuzhiyun 	int suspending;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	/* hook for suspending MAX3100 via dedicated pin */
128*4882a593Smuzhiyun 	void (*max3100_hw_suspend) (int suspend);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	/* poll time (in ms) for ctrl lines */
131*4882a593Smuzhiyun 	int poll_time;
132*4882a593Smuzhiyun 	/* and its timer */
133*4882a593Smuzhiyun 	struct timer_list	timer;
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun static struct max3100_port *max3100s[MAX_MAX3100]; /* the chips */
137*4882a593Smuzhiyun static DEFINE_MUTEX(max3100s_lock);		   /* race on probe */
138*4882a593Smuzhiyun 
max3100_do_parity(struct max3100_port * s,u16 c)139*4882a593Smuzhiyun static int max3100_do_parity(struct max3100_port *s, u16 c)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	int parity;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	if (s->parity & MAX3100_PARITY_ODD)
144*4882a593Smuzhiyun 		parity = 1;
145*4882a593Smuzhiyun 	else
146*4882a593Smuzhiyun 		parity = 0;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	if (s->parity & MAX3100_7BIT)
149*4882a593Smuzhiyun 		c &= 0x7f;
150*4882a593Smuzhiyun 	else
151*4882a593Smuzhiyun 		c &= 0xff;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	parity = parity ^ (hweight8(c) & 1);
154*4882a593Smuzhiyun 	return parity;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
max3100_check_parity(struct max3100_port * s,u16 c)157*4882a593Smuzhiyun static int max3100_check_parity(struct max3100_port *s, u16 c)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	return max3100_do_parity(s, c) == ((c >> 8) & 1);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun 
max3100_calc_parity(struct max3100_port * s,u16 * c)162*4882a593Smuzhiyun static void max3100_calc_parity(struct max3100_port *s, u16 *c)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	if (s->parity & MAX3100_7BIT)
165*4882a593Smuzhiyun 		*c &= 0x7f;
166*4882a593Smuzhiyun 	else
167*4882a593Smuzhiyun 		*c &= 0xff;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	if (s->parity & MAX3100_PARITY_ON)
170*4882a593Smuzhiyun 		*c |= max3100_do_parity(s, *c) << 8;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static void max3100_work(struct work_struct *w);
174*4882a593Smuzhiyun 
max3100_dowork(struct max3100_port * s)175*4882a593Smuzhiyun static void max3100_dowork(struct max3100_port *s)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	if (!s->force_end_work && !freezing(current) && !s->suspending)
178*4882a593Smuzhiyun 		queue_work(s->workqueue, &s->work);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
max3100_timeout(struct timer_list * t)181*4882a593Smuzhiyun static void max3100_timeout(struct timer_list *t)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	struct max3100_port *s = from_timer(s, t, timer);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	if (s->port.state) {
186*4882a593Smuzhiyun 		max3100_dowork(s);
187*4882a593Smuzhiyun 		mod_timer(&s->timer, jiffies + s->poll_time);
188*4882a593Smuzhiyun 	}
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
max3100_sr(struct max3100_port * s,u16 tx,u16 * rx)191*4882a593Smuzhiyun static int max3100_sr(struct max3100_port *s, u16 tx, u16 *rx)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	struct spi_message message;
194*4882a593Smuzhiyun 	u16 etx, erx;
195*4882a593Smuzhiyun 	int status;
196*4882a593Smuzhiyun 	struct spi_transfer tran = {
197*4882a593Smuzhiyun 		.tx_buf = &etx,
198*4882a593Smuzhiyun 		.rx_buf = &erx,
199*4882a593Smuzhiyun 		.len = 2,
200*4882a593Smuzhiyun 	};
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	etx = cpu_to_be16(tx);
203*4882a593Smuzhiyun 	spi_message_init(&message);
204*4882a593Smuzhiyun 	spi_message_add_tail(&tran, &message);
205*4882a593Smuzhiyun 	status = spi_sync(s->spi, &message);
206*4882a593Smuzhiyun 	if (status) {
207*4882a593Smuzhiyun 		dev_warn(&s->spi->dev, "error while calling spi_sync\n");
208*4882a593Smuzhiyun 		return -EIO;
209*4882a593Smuzhiyun 	}
210*4882a593Smuzhiyun 	*rx = be16_to_cpu(erx);
211*4882a593Smuzhiyun 	s->tx_empty = (*rx & MAX3100_T) > 0;
212*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%04x - %04x\n", tx, *rx);
213*4882a593Smuzhiyun 	return 0;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
max3100_handlerx(struct max3100_port * s,u16 rx)216*4882a593Smuzhiyun static int max3100_handlerx(struct max3100_port *s, u16 rx)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun 	unsigned int ch, flg, status = 0;
219*4882a593Smuzhiyun 	int ret = 0, cts;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	if (rx & MAX3100_R && s->rx_enabled) {
222*4882a593Smuzhiyun 		dev_dbg(&s->spi->dev, "%s\n", __func__);
223*4882a593Smuzhiyun 		ch = rx & (s->parity & MAX3100_7BIT ? 0x7f : 0xff);
224*4882a593Smuzhiyun 		if (rx & MAX3100_RAFE) {
225*4882a593Smuzhiyun 			s->port.icount.frame++;
226*4882a593Smuzhiyun 			flg = TTY_FRAME;
227*4882a593Smuzhiyun 			status |= MAX3100_STATUS_FE;
228*4882a593Smuzhiyun 		} else {
229*4882a593Smuzhiyun 			if (s->parity & MAX3100_PARITY_ON) {
230*4882a593Smuzhiyun 				if (max3100_check_parity(s, rx)) {
231*4882a593Smuzhiyun 					s->port.icount.rx++;
232*4882a593Smuzhiyun 					flg = TTY_NORMAL;
233*4882a593Smuzhiyun 				} else {
234*4882a593Smuzhiyun 					s->port.icount.parity++;
235*4882a593Smuzhiyun 					flg = TTY_PARITY;
236*4882a593Smuzhiyun 					status |= MAX3100_STATUS_PE;
237*4882a593Smuzhiyun 				}
238*4882a593Smuzhiyun 			} else {
239*4882a593Smuzhiyun 				s->port.icount.rx++;
240*4882a593Smuzhiyun 				flg = TTY_NORMAL;
241*4882a593Smuzhiyun 			}
242*4882a593Smuzhiyun 		}
243*4882a593Smuzhiyun 		uart_insert_char(&s->port, status, MAX3100_STATUS_OE, ch, flg);
244*4882a593Smuzhiyun 		ret = 1;
245*4882a593Smuzhiyun 	}
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	cts = (rx & MAX3100_CTS) > 0;
248*4882a593Smuzhiyun 	if (s->cts != cts) {
249*4882a593Smuzhiyun 		s->cts = cts;
250*4882a593Smuzhiyun 		uart_handle_cts_change(&s->port, cts ? TIOCM_CTS : 0);
251*4882a593Smuzhiyun 	}
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	return ret;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun 
max3100_work(struct work_struct * w)256*4882a593Smuzhiyun static void max3100_work(struct work_struct *w)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun 	struct max3100_port *s = container_of(w, struct max3100_port, work);
259*4882a593Smuzhiyun 	int rxchars;
260*4882a593Smuzhiyun 	u16 tx, rx;
261*4882a593Smuzhiyun 	int conf, cconf, crts;
262*4882a593Smuzhiyun 	struct circ_buf *xmit = &s->port.state->xmit;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	rxchars = 0;
267*4882a593Smuzhiyun 	do {
268*4882a593Smuzhiyun 		spin_lock(&s->conf_lock);
269*4882a593Smuzhiyun 		conf = s->conf;
270*4882a593Smuzhiyun 		cconf = s->conf_commit;
271*4882a593Smuzhiyun 		s->conf_commit = 0;
272*4882a593Smuzhiyun 		crts = s->rts_commit;
273*4882a593Smuzhiyun 		s->rts_commit = 0;
274*4882a593Smuzhiyun 		spin_unlock(&s->conf_lock);
275*4882a593Smuzhiyun 		if (cconf)
276*4882a593Smuzhiyun 			max3100_sr(s, MAX3100_WC | conf, &rx);
277*4882a593Smuzhiyun 		if (crts) {
278*4882a593Smuzhiyun 			max3100_sr(s, MAX3100_WD | MAX3100_TE |
279*4882a593Smuzhiyun 				   (s->rts ? MAX3100_RTS : 0), &rx);
280*4882a593Smuzhiyun 			rxchars += max3100_handlerx(s, rx);
281*4882a593Smuzhiyun 		}
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 		max3100_sr(s, MAX3100_RD, &rx);
284*4882a593Smuzhiyun 		rxchars += max3100_handlerx(s, rx);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 		if (rx & MAX3100_T) {
287*4882a593Smuzhiyun 			tx = 0xffff;
288*4882a593Smuzhiyun 			if (s->port.x_char) {
289*4882a593Smuzhiyun 				tx = s->port.x_char;
290*4882a593Smuzhiyun 				s->port.icount.tx++;
291*4882a593Smuzhiyun 				s->port.x_char = 0;
292*4882a593Smuzhiyun 			} else if (!uart_circ_empty(xmit) &&
293*4882a593Smuzhiyun 				   !uart_tx_stopped(&s->port)) {
294*4882a593Smuzhiyun 				tx = xmit->buf[xmit->tail];
295*4882a593Smuzhiyun 				xmit->tail = (xmit->tail + 1) &
296*4882a593Smuzhiyun 					(UART_XMIT_SIZE - 1);
297*4882a593Smuzhiyun 				s->port.icount.tx++;
298*4882a593Smuzhiyun 			}
299*4882a593Smuzhiyun 			if (tx != 0xffff) {
300*4882a593Smuzhiyun 				max3100_calc_parity(s, &tx);
301*4882a593Smuzhiyun 				tx |= MAX3100_WD | (s->rts ? MAX3100_RTS : 0);
302*4882a593Smuzhiyun 				max3100_sr(s, tx, &rx);
303*4882a593Smuzhiyun 				rxchars += max3100_handlerx(s, rx);
304*4882a593Smuzhiyun 			}
305*4882a593Smuzhiyun 		}
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 		if (rxchars > 16) {
308*4882a593Smuzhiyun 			tty_flip_buffer_push(&s->port.state->port);
309*4882a593Smuzhiyun 			rxchars = 0;
310*4882a593Smuzhiyun 		}
311*4882a593Smuzhiyun 		if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
312*4882a593Smuzhiyun 			uart_write_wakeup(&s->port);
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	} while (!s->force_end_work &&
315*4882a593Smuzhiyun 		 !freezing(current) &&
316*4882a593Smuzhiyun 		 ((rx & MAX3100_R) ||
317*4882a593Smuzhiyun 		  (!uart_circ_empty(xmit) &&
318*4882a593Smuzhiyun 		   !uart_tx_stopped(&s->port))));
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	if (rxchars > 0)
321*4882a593Smuzhiyun 		tty_flip_buffer_push(&s->port.state->port);
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
max3100_irq(int irqno,void * dev_id)324*4882a593Smuzhiyun static irqreturn_t max3100_irq(int irqno, void *dev_id)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	struct max3100_port *s = dev_id;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	max3100_dowork(s);
331*4882a593Smuzhiyun 	return IRQ_HANDLED;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun 
max3100_enable_ms(struct uart_port * port)334*4882a593Smuzhiyun static void max3100_enable_ms(struct uart_port *port)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
337*4882a593Smuzhiyun 					      struct max3100_port,
338*4882a593Smuzhiyun 					      port);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	if (s->poll_time > 0)
341*4882a593Smuzhiyun 		mod_timer(&s->timer, jiffies);
342*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun 
max3100_start_tx(struct uart_port * port)345*4882a593Smuzhiyun static void max3100_start_tx(struct uart_port *port)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
348*4882a593Smuzhiyun 					      struct max3100_port,
349*4882a593Smuzhiyun 					      port);
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	max3100_dowork(s);
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun 
max3100_stop_rx(struct uart_port * port)356*4882a593Smuzhiyun static void max3100_stop_rx(struct uart_port *port)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
359*4882a593Smuzhiyun 					      struct max3100_port,
360*4882a593Smuzhiyun 					      port);
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	s->rx_enabled = 0;
365*4882a593Smuzhiyun 	spin_lock(&s->conf_lock);
366*4882a593Smuzhiyun 	s->conf &= ~MAX3100_RM;
367*4882a593Smuzhiyun 	s->conf_commit = 1;
368*4882a593Smuzhiyun 	spin_unlock(&s->conf_lock);
369*4882a593Smuzhiyun 	max3100_dowork(s);
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun 
max3100_tx_empty(struct uart_port * port)372*4882a593Smuzhiyun static unsigned int max3100_tx_empty(struct uart_port *port)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
375*4882a593Smuzhiyun 					      struct max3100_port,
376*4882a593Smuzhiyun 					      port);
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	/* may not be truly up-to-date */
381*4882a593Smuzhiyun 	max3100_dowork(s);
382*4882a593Smuzhiyun 	return s->tx_empty;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun 
max3100_get_mctrl(struct uart_port * port)385*4882a593Smuzhiyun static unsigned int max3100_get_mctrl(struct uart_port *port)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
388*4882a593Smuzhiyun 					      struct max3100_port,
389*4882a593Smuzhiyun 					      port);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	/* may not be truly up-to-date */
394*4882a593Smuzhiyun 	max3100_dowork(s);
395*4882a593Smuzhiyun 	/* always assert DCD and DSR since these lines are not wired */
396*4882a593Smuzhiyun 	return (s->cts ? TIOCM_CTS : 0) | TIOCM_DSR | TIOCM_CAR;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun 
max3100_set_mctrl(struct uart_port * port,unsigned int mctrl)399*4882a593Smuzhiyun static void max3100_set_mctrl(struct uart_port *port, unsigned int mctrl)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
402*4882a593Smuzhiyun 					      struct max3100_port,
403*4882a593Smuzhiyun 					      port);
404*4882a593Smuzhiyun 	int rts;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	rts = (mctrl & TIOCM_RTS) > 0;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	spin_lock(&s->conf_lock);
411*4882a593Smuzhiyun 	if (s->rts != rts) {
412*4882a593Smuzhiyun 		s->rts = rts;
413*4882a593Smuzhiyun 		s->rts_commit = 1;
414*4882a593Smuzhiyun 		max3100_dowork(s);
415*4882a593Smuzhiyun 	}
416*4882a593Smuzhiyun 	spin_unlock(&s->conf_lock);
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun static void
max3100_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)420*4882a593Smuzhiyun max3100_set_termios(struct uart_port *port, struct ktermios *termios,
421*4882a593Smuzhiyun 		    struct ktermios *old)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
424*4882a593Smuzhiyun 					      struct max3100_port,
425*4882a593Smuzhiyun 					      port);
426*4882a593Smuzhiyun 	int baud = 0;
427*4882a593Smuzhiyun 	unsigned cflag;
428*4882a593Smuzhiyun 	u32 param_new, param_mask, parity = 0;
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	cflag = termios->c_cflag;
433*4882a593Smuzhiyun 	param_mask = 0;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	baud = tty_termios_baud_rate(termios);
436*4882a593Smuzhiyun 	param_new = s->conf & MAX3100_BAUD;
437*4882a593Smuzhiyun 	switch (baud) {
438*4882a593Smuzhiyun 	case 300:
439*4882a593Smuzhiyun 		if (s->crystal)
440*4882a593Smuzhiyun 			baud = s->baud;
441*4882a593Smuzhiyun 		else
442*4882a593Smuzhiyun 			param_new = 15;
443*4882a593Smuzhiyun 		break;
444*4882a593Smuzhiyun 	case 600:
445*4882a593Smuzhiyun 		param_new = 14 + s->crystal;
446*4882a593Smuzhiyun 		break;
447*4882a593Smuzhiyun 	case 1200:
448*4882a593Smuzhiyun 		param_new = 13 + s->crystal;
449*4882a593Smuzhiyun 		break;
450*4882a593Smuzhiyun 	case 2400:
451*4882a593Smuzhiyun 		param_new = 12 + s->crystal;
452*4882a593Smuzhiyun 		break;
453*4882a593Smuzhiyun 	case 4800:
454*4882a593Smuzhiyun 		param_new = 11 + s->crystal;
455*4882a593Smuzhiyun 		break;
456*4882a593Smuzhiyun 	case 9600:
457*4882a593Smuzhiyun 		param_new = 10 + s->crystal;
458*4882a593Smuzhiyun 		break;
459*4882a593Smuzhiyun 	case 19200:
460*4882a593Smuzhiyun 		param_new = 9 + s->crystal;
461*4882a593Smuzhiyun 		break;
462*4882a593Smuzhiyun 	case 38400:
463*4882a593Smuzhiyun 		param_new = 8 + s->crystal;
464*4882a593Smuzhiyun 		break;
465*4882a593Smuzhiyun 	case 57600:
466*4882a593Smuzhiyun 		param_new = 1 + s->crystal;
467*4882a593Smuzhiyun 		break;
468*4882a593Smuzhiyun 	case 115200:
469*4882a593Smuzhiyun 		param_new = 0 + s->crystal;
470*4882a593Smuzhiyun 		break;
471*4882a593Smuzhiyun 	case 230400:
472*4882a593Smuzhiyun 		if (s->crystal)
473*4882a593Smuzhiyun 			param_new = 0;
474*4882a593Smuzhiyun 		else
475*4882a593Smuzhiyun 			baud = s->baud;
476*4882a593Smuzhiyun 		break;
477*4882a593Smuzhiyun 	default:
478*4882a593Smuzhiyun 		baud = s->baud;
479*4882a593Smuzhiyun 	}
480*4882a593Smuzhiyun 	tty_termios_encode_baud_rate(termios, baud, baud);
481*4882a593Smuzhiyun 	s->baud = baud;
482*4882a593Smuzhiyun 	param_mask |= MAX3100_BAUD;
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	if ((cflag & CSIZE) == CS8) {
485*4882a593Smuzhiyun 		param_new &= ~MAX3100_L;
486*4882a593Smuzhiyun 		parity &= ~MAX3100_7BIT;
487*4882a593Smuzhiyun 	} else {
488*4882a593Smuzhiyun 		param_new |= MAX3100_L;
489*4882a593Smuzhiyun 		parity |= MAX3100_7BIT;
490*4882a593Smuzhiyun 		cflag = (cflag & ~CSIZE) | CS7;
491*4882a593Smuzhiyun 	}
492*4882a593Smuzhiyun 	param_mask |= MAX3100_L;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	if (cflag & CSTOPB)
495*4882a593Smuzhiyun 		param_new |= MAX3100_ST;
496*4882a593Smuzhiyun 	else
497*4882a593Smuzhiyun 		param_new &= ~MAX3100_ST;
498*4882a593Smuzhiyun 	param_mask |= MAX3100_ST;
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	if (cflag & PARENB) {
501*4882a593Smuzhiyun 		param_new |= MAX3100_PE;
502*4882a593Smuzhiyun 		parity |= MAX3100_PARITY_ON;
503*4882a593Smuzhiyun 	} else {
504*4882a593Smuzhiyun 		param_new &= ~MAX3100_PE;
505*4882a593Smuzhiyun 		parity &= ~MAX3100_PARITY_ON;
506*4882a593Smuzhiyun 	}
507*4882a593Smuzhiyun 	param_mask |= MAX3100_PE;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	if (cflag & PARODD)
510*4882a593Smuzhiyun 		parity |= MAX3100_PARITY_ODD;
511*4882a593Smuzhiyun 	else
512*4882a593Smuzhiyun 		parity &= ~MAX3100_PARITY_ODD;
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	/* mask termios capabilities we don't support */
515*4882a593Smuzhiyun 	cflag &= ~CMSPAR;
516*4882a593Smuzhiyun 	termios->c_cflag = cflag;
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	s->port.ignore_status_mask = 0;
519*4882a593Smuzhiyun 	if (termios->c_iflag & IGNPAR)
520*4882a593Smuzhiyun 		s->port.ignore_status_mask |=
521*4882a593Smuzhiyun 			MAX3100_STATUS_PE | MAX3100_STATUS_FE |
522*4882a593Smuzhiyun 			MAX3100_STATUS_OE;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	/* we are sending char from a workqueue so enable */
525*4882a593Smuzhiyun 	s->port.state->port.low_latency = 1;
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	if (s->poll_time > 0)
528*4882a593Smuzhiyun 		del_timer_sync(&s->timer);
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	uart_update_timeout(port, termios->c_cflag, baud);
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	spin_lock(&s->conf_lock);
533*4882a593Smuzhiyun 	s->conf = (s->conf & ~param_mask) | (param_new & param_mask);
534*4882a593Smuzhiyun 	s->conf_commit = 1;
535*4882a593Smuzhiyun 	s->parity = parity;
536*4882a593Smuzhiyun 	spin_unlock(&s->conf_lock);
537*4882a593Smuzhiyun 	max3100_dowork(s);
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	if (UART_ENABLE_MS(&s->port, termios->c_cflag))
540*4882a593Smuzhiyun 		max3100_enable_ms(&s->port);
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun 
max3100_shutdown(struct uart_port * port)543*4882a593Smuzhiyun static void max3100_shutdown(struct uart_port *port)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
546*4882a593Smuzhiyun 					      struct max3100_port,
547*4882a593Smuzhiyun 					      port);
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	if (s->suspending)
552*4882a593Smuzhiyun 		return;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	s->force_end_work = 1;
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	if (s->poll_time > 0)
557*4882a593Smuzhiyun 		del_timer_sync(&s->timer);
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	if (s->workqueue) {
560*4882a593Smuzhiyun 		flush_workqueue(s->workqueue);
561*4882a593Smuzhiyun 		destroy_workqueue(s->workqueue);
562*4882a593Smuzhiyun 		s->workqueue = NULL;
563*4882a593Smuzhiyun 	}
564*4882a593Smuzhiyun 	if (s->irq)
565*4882a593Smuzhiyun 		free_irq(s->irq, s);
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	/* set shutdown mode to save power */
568*4882a593Smuzhiyun 	if (s->max3100_hw_suspend)
569*4882a593Smuzhiyun 		s->max3100_hw_suspend(1);
570*4882a593Smuzhiyun 	else  {
571*4882a593Smuzhiyun 		u16 tx, rx;
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 		tx = MAX3100_WC | MAX3100_SHDN;
574*4882a593Smuzhiyun 		max3100_sr(s, tx, &rx);
575*4882a593Smuzhiyun 	}
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun 
max3100_startup(struct uart_port * port)578*4882a593Smuzhiyun static int max3100_startup(struct uart_port *port)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
581*4882a593Smuzhiyun 					      struct max3100_port,
582*4882a593Smuzhiyun 					      port);
583*4882a593Smuzhiyun 	char b[12];
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	s->conf = MAX3100_RM;
588*4882a593Smuzhiyun 	s->baud = s->crystal ? 230400 : 115200;
589*4882a593Smuzhiyun 	s->rx_enabled = 1;
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	if (s->suspending)
592*4882a593Smuzhiyun 		return 0;
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	s->force_end_work = 0;
595*4882a593Smuzhiyun 	s->parity = 0;
596*4882a593Smuzhiyun 	s->rts = 0;
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	sprintf(b, "max3100-%d", s->minor);
599*4882a593Smuzhiyun 	s->workqueue = create_freezable_workqueue(b);
600*4882a593Smuzhiyun 	if (!s->workqueue) {
601*4882a593Smuzhiyun 		dev_warn(&s->spi->dev, "cannot create workqueue\n");
602*4882a593Smuzhiyun 		return -EBUSY;
603*4882a593Smuzhiyun 	}
604*4882a593Smuzhiyun 	INIT_WORK(&s->work, max3100_work);
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	if (request_irq(s->irq, max3100_irq,
607*4882a593Smuzhiyun 			IRQF_TRIGGER_FALLING, "max3100", s) < 0) {
608*4882a593Smuzhiyun 		dev_warn(&s->spi->dev, "cannot allocate irq %d\n", s->irq);
609*4882a593Smuzhiyun 		s->irq = 0;
610*4882a593Smuzhiyun 		destroy_workqueue(s->workqueue);
611*4882a593Smuzhiyun 		s->workqueue = NULL;
612*4882a593Smuzhiyun 		return -EBUSY;
613*4882a593Smuzhiyun 	}
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	if (s->loopback) {
616*4882a593Smuzhiyun 		u16 tx, rx;
617*4882a593Smuzhiyun 		tx = 0x4001;
618*4882a593Smuzhiyun 		max3100_sr(s, tx, &rx);
619*4882a593Smuzhiyun 	}
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	if (s->max3100_hw_suspend)
622*4882a593Smuzhiyun 		s->max3100_hw_suspend(0);
623*4882a593Smuzhiyun 	s->conf_commit = 1;
624*4882a593Smuzhiyun 	max3100_dowork(s);
625*4882a593Smuzhiyun 	/* wait for clock to settle */
626*4882a593Smuzhiyun 	msleep(50);
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun 	max3100_enable_ms(&s->port);
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	return 0;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun 
max3100_type(struct uart_port * port)633*4882a593Smuzhiyun static const char *max3100_type(struct uart_port *port)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
636*4882a593Smuzhiyun 					      struct max3100_port,
637*4882a593Smuzhiyun 					      port);
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	return s->port.type == PORT_MAX3100 ? "MAX3100" : NULL;
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun 
max3100_release_port(struct uart_port * port)644*4882a593Smuzhiyun static void max3100_release_port(struct uart_port *port)
645*4882a593Smuzhiyun {
646*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
647*4882a593Smuzhiyun 					      struct max3100_port,
648*4882a593Smuzhiyun 					      port);
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
651*4882a593Smuzhiyun }
652*4882a593Smuzhiyun 
max3100_config_port(struct uart_port * port,int flags)653*4882a593Smuzhiyun static void max3100_config_port(struct uart_port *port, int flags)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
656*4882a593Smuzhiyun 					      struct max3100_port,
657*4882a593Smuzhiyun 					      port);
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	if (flags & UART_CONFIG_TYPE)
662*4882a593Smuzhiyun 		s->port.type = PORT_MAX3100;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun 
max3100_verify_port(struct uart_port * port,struct serial_struct * ser)665*4882a593Smuzhiyun static int max3100_verify_port(struct uart_port *port,
666*4882a593Smuzhiyun 			       struct serial_struct *ser)
667*4882a593Smuzhiyun {
668*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
669*4882a593Smuzhiyun 					      struct max3100_port,
670*4882a593Smuzhiyun 					      port);
671*4882a593Smuzhiyun 	int ret = -EINVAL;
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
674*4882a593Smuzhiyun 
675*4882a593Smuzhiyun 	if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3100)
676*4882a593Smuzhiyun 		ret = 0;
677*4882a593Smuzhiyun 	return ret;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun 
max3100_stop_tx(struct uart_port * port)680*4882a593Smuzhiyun static void max3100_stop_tx(struct uart_port *port)
681*4882a593Smuzhiyun {
682*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
683*4882a593Smuzhiyun 					      struct max3100_port,
684*4882a593Smuzhiyun 					      port);
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun 
max3100_request_port(struct uart_port * port)689*4882a593Smuzhiyun static int max3100_request_port(struct uart_port *port)
690*4882a593Smuzhiyun {
691*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
692*4882a593Smuzhiyun 					      struct max3100_port,
693*4882a593Smuzhiyun 					      port);
694*4882a593Smuzhiyun 
695*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
696*4882a593Smuzhiyun 	return 0;
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun 
max3100_break_ctl(struct uart_port * port,int break_state)699*4882a593Smuzhiyun static void max3100_break_ctl(struct uart_port *port, int break_state)
700*4882a593Smuzhiyun {
701*4882a593Smuzhiyun 	struct max3100_port *s = container_of(port,
702*4882a593Smuzhiyun 					      struct max3100_port,
703*4882a593Smuzhiyun 					      port);
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun static const struct uart_ops max3100_ops = {
709*4882a593Smuzhiyun 	.tx_empty	= max3100_tx_empty,
710*4882a593Smuzhiyun 	.set_mctrl	= max3100_set_mctrl,
711*4882a593Smuzhiyun 	.get_mctrl	= max3100_get_mctrl,
712*4882a593Smuzhiyun 	.stop_tx        = max3100_stop_tx,
713*4882a593Smuzhiyun 	.start_tx	= max3100_start_tx,
714*4882a593Smuzhiyun 	.stop_rx	= max3100_stop_rx,
715*4882a593Smuzhiyun 	.enable_ms      = max3100_enable_ms,
716*4882a593Smuzhiyun 	.break_ctl      = max3100_break_ctl,
717*4882a593Smuzhiyun 	.startup	= max3100_startup,
718*4882a593Smuzhiyun 	.shutdown	= max3100_shutdown,
719*4882a593Smuzhiyun 	.set_termios	= max3100_set_termios,
720*4882a593Smuzhiyun 	.type		= max3100_type,
721*4882a593Smuzhiyun 	.release_port   = max3100_release_port,
722*4882a593Smuzhiyun 	.request_port   = max3100_request_port,
723*4882a593Smuzhiyun 	.config_port	= max3100_config_port,
724*4882a593Smuzhiyun 	.verify_port	= max3100_verify_port,
725*4882a593Smuzhiyun };
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun static struct uart_driver max3100_uart_driver = {
728*4882a593Smuzhiyun 	.owner          = THIS_MODULE,
729*4882a593Smuzhiyun 	.driver_name    = "ttyMAX",
730*4882a593Smuzhiyun 	.dev_name       = "ttyMAX",
731*4882a593Smuzhiyun 	.major          = MAX3100_MAJOR,
732*4882a593Smuzhiyun 	.minor          = MAX3100_MINOR,
733*4882a593Smuzhiyun 	.nr             = MAX_MAX3100,
734*4882a593Smuzhiyun };
735*4882a593Smuzhiyun static int uart_driver_registered;
736*4882a593Smuzhiyun 
max3100_probe(struct spi_device * spi)737*4882a593Smuzhiyun static int max3100_probe(struct spi_device *spi)
738*4882a593Smuzhiyun {
739*4882a593Smuzhiyun 	int i, retval;
740*4882a593Smuzhiyun 	struct plat_max3100 *pdata;
741*4882a593Smuzhiyun 	u16 tx, rx;
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	mutex_lock(&max3100s_lock);
744*4882a593Smuzhiyun 
745*4882a593Smuzhiyun 	if (!uart_driver_registered) {
746*4882a593Smuzhiyun 		uart_driver_registered = 1;
747*4882a593Smuzhiyun 		retval = uart_register_driver(&max3100_uart_driver);
748*4882a593Smuzhiyun 		if (retval) {
749*4882a593Smuzhiyun 			printk(KERN_ERR "Couldn't register max3100 uart driver\n");
750*4882a593Smuzhiyun 			mutex_unlock(&max3100s_lock);
751*4882a593Smuzhiyun 			return retval;
752*4882a593Smuzhiyun 		}
753*4882a593Smuzhiyun 	}
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	for (i = 0; i < MAX_MAX3100; i++)
756*4882a593Smuzhiyun 		if (!max3100s[i])
757*4882a593Smuzhiyun 			break;
758*4882a593Smuzhiyun 	if (i == MAX_MAX3100) {
759*4882a593Smuzhiyun 		dev_warn(&spi->dev, "too many MAX3100 chips\n");
760*4882a593Smuzhiyun 		mutex_unlock(&max3100s_lock);
761*4882a593Smuzhiyun 		return -ENOMEM;
762*4882a593Smuzhiyun 	}
763*4882a593Smuzhiyun 
764*4882a593Smuzhiyun 	max3100s[i] = kzalloc(sizeof(struct max3100_port), GFP_KERNEL);
765*4882a593Smuzhiyun 	if (!max3100s[i]) {
766*4882a593Smuzhiyun 		dev_warn(&spi->dev,
767*4882a593Smuzhiyun 			 "kmalloc for max3100 structure %d failed!\n", i);
768*4882a593Smuzhiyun 		mutex_unlock(&max3100s_lock);
769*4882a593Smuzhiyun 		return -ENOMEM;
770*4882a593Smuzhiyun 	}
771*4882a593Smuzhiyun 	max3100s[i]->spi = spi;
772*4882a593Smuzhiyun 	max3100s[i]->irq = spi->irq;
773*4882a593Smuzhiyun 	spin_lock_init(&max3100s[i]->conf_lock);
774*4882a593Smuzhiyun 	spi_set_drvdata(spi, max3100s[i]);
775*4882a593Smuzhiyun 	pdata = dev_get_platdata(&spi->dev);
776*4882a593Smuzhiyun 	max3100s[i]->crystal = pdata->crystal;
777*4882a593Smuzhiyun 	max3100s[i]->loopback = pdata->loopback;
778*4882a593Smuzhiyun 	max3100s[i]->poll_time = msecs_to_jiffies(pdata->poll_time);
779*4882a593Smuzhiyun 	if (pdata->poll_time > 0 && max3100s[i]->poll_time == 0)
780*4882a593Smuzhiyun 		max3100s[i]->poll_time = 1;
781*4882a593Smuzhiyun 	max3100s[i]->max3100_hw_suspend = pdata->max3100_hw_suspend;
782*4882a593Smuzhiyun 	max3100s[i]->minor = i;
783*4882a593Smuzhiyun 	timer_setup(&max3100s[i]->timer, max3100_timeout, 0);
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun 	dev_dbg(&spi->dev, "%s: adding port %d\n", __func__, i);
786*4882a593Smuzhiyun 	max3100s[i]->port.irq = max3100s[i]->irq;
787*4882a593Smuzhiyun 	max3100s[i]->port.uartclk = max3100s[i]->crystal ? 3686400 : 1843200;
788*4882a593Smuzhiyun 	max3100s[i]->port.fifosize = 16;
789*4882a593Smuzhiyun 	max3100s[i]->port.ops = &max3100_ops;
790*4882a593Smuzhiyun 	max3100s[i]->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
791*4882a593Smuzhiyun 	max3100s[i]->port.line = i;
792*4882a593Smuzhiyun 	max3100s[i]->port.type = PORT_MAX3100;
793*4882a593Smuzhiyun 	max3100s[i]->port.dev = &spi->dev;
794*4882a593Smuzhiyun 	retval = uart_add_one_port(&max3100_uart_driver, &max3100s[i]->port);
795*4882a593Smuzhiyun 	if (retval < 0)
796*4882a593Smuzhiyun 		dev_warn(&spi->dev,
797*4882a593Smuzhiyun 			 "uart_add_one_port failed for line %d with error %d\n",
798*4882a593Smuzhiyun 			 i, retval);
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun 	/* set shutdown mode to save power. Will be woken-up on open */
801*4882a593Smuzhiyun 	if (max3100s[i]->max3100_hw_suspend)
802*4882a593Smuzhiyun 		max3100s[i]->max3100_hw_suspend(1);
803*4882a593Smuzhiyun 	else {
804*4882a593Smuzhiyun 		tx = MAX3100_WC | MAX3100_SHDN;
805*4882a593Smuzhiyun 		max3100_sr(max3100s[i], tx, &rx);
806*4882a593Smuzhiyun 	}
807*4882a593Smuzhiyun 	mutex_unlock(&max3100s_lock);
808*4882a593Smuzhiyun 	return 0;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun 
max3100_remove(struct spi_device * spi)811*4882a593Smuzhiyun static int max3100_remove(struct spi_device *spi)
812*4882a593Smuzhiyun {
813*4882a593Smuzhiyun 	struct max3100_port *s = spi_get_drvdata(spi);
814*4882a593Smuzhiyun 	int i;
815*4882a593Smuzhiyun 
816*4882a593Smuzhiyun 	mutex_lock(&max3100s_lock);
817*4882a593Smuzhiyun 
818*4882a593Smuzhiyun 	/* find out the index for the chip we are removing */
819*4882a593Smuzhiyun 	for (i = 0; i < MAX_MAX3100; i++)
820*4882a593Smuzhiyun 		if (max3100s[i] == s) {
821*4882a593Smuzhiyun 			dev_dbg(&spi->dev, "%s: removing port %d\n", __func__, i);
822*4882a593Smuzhiyun 			uart_remove_one_port(&max3100_uart_driver, &max3100s[i]->port);
823*4882a593Smuzhiyun 			kfree(max3100s[i]);
824*4882a593Smuzhiyun 			max3100s[i] = NULL;
825*4882a593Smuzhiyun 			break;
826*4882a593Smuzhiyun 		}
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun 	WARN_ON(i == MAX_MAX3100);
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 	/* check if this is the last chip we have */
831*4882a593Smuzhiyun 	for (i = 0; i < MAX_MAX3100; i++)
832*4882a593Smuzhiyun 		if (max3100s[i]) {
833*4882a593Smuzhiyun 			mutex_unlock(&max3100s_lock);
834*4882a593Smuzhiyun 			return 0;
835*4882a593Smuzhiyun 		}
836*4882a593Smuzhiyun 	pr_debug("removing max3100 driver\n");
837*4882a593Smuzhiyun 	uart_unregister_driver(&max3100_uart_driver);
838*4882a593Smuzhiyun 
839*4882a593Smuzhiyun 	mutex_unlock(&max3100s_lock);
840*4882a593Smuzhiyun 	return 0;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
844*4882a593Smuzhiyun 
max3100_suspend(struct device * dev)845*4882a593Smuzhiyun static int max3100_suspend(struct device *dev)
846*4882a593Smuzhiyun {
847*4882a593Smuzhiyun 	struct max3100_port *s = dev_get_drvdata(dev);
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	disable_irq(s->irq);
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun 	s->suspending = 1;
854*4882a593Smuzhiyun 	uart_suspend_port(&max3100_uart_driver, &s->port);
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun 	if (s->max3100_hw_suspend)
857*4882a593Smuzhiyun 		s->max3100_hw_suspend(1);
858*4882a593Smuzhiyun 	else {
859*4882a593Smuzhiyun 		/* no HW suspend, so do SW one */
860*4882a593Smuzhiyun 		u16 tx, rx;
861*4882a593Smuzhiyun 
862*4882a593Smuzhiyun 		tx = MAX3100_WC | MAX3100_SHDN;
863*4882a593Smuzhiyun 		max3100_sr(s, tx, &rx);
864*4882a593Smuzhiyun 	}
865*4882a593Smuzhiyun 	return 0;
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun 
max3100_resume(struct device * dev)868*4882a593Smuzhiyun static int max3100_resume(struct device *dev)
869*4882a593Smuzhiyun {
870*4882a593Smuzhiyun 	struct max3100_port *s = dev_get_drvdata(dev);
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun 	dev_dbg(&s->spi->dev, "%s\n", __func__);
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun 	if (s->max3100_hw_suspend)
875*4882a593Smuzhiyun 		s->max3100_hw_suspend(0);
876*4882a593Smuzhiyun 	uart_resume_port(&max3100_uart_driver, &s->port);
877*4882a593Smuzhiyun 	s->suspending = 0;
878*4882a593Smuzhiyun 
879*4882a593Smuzhiyun 	enable_irq(s->irq);
880*4882a593Smuzhiyun 
881*4882a593Smuzhiyun 	s->conf_commit = 1;
882*4882a593Smuzhiyun 	if (s->workqueue)
883*4882a593Smuzhiyun 		max3100_dowork(s);
884*4882a593Smuzhiyun 
885*4882a593Smuzhiyun 	return 0;
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun 
888*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(max3100_pm_ops, max3100_suspend, max3100_resume);
889*4882a593Smuzhiyun #define MAX3100_PM_OPS (&max3100_pm_ops)
890*4882a593Smuzhiyun 
891*4882a593Smuzhiyun #else
892*4882a593Smuzhiyun #define MAX3100_PM_OPS NULL
893*4882a593Smuzhiyun #endif
894*4882a593Smuzhiyun 
895*4882a593Smuzhiyun static struct spi_driver max3100_driver = {
896*4882a593Smuzhiyun 	.driver = {
897*4882a593Smuzhiyun 		.name		= "max3100",
898*4882a593Smuzhiyun 		.pm		= MAX3100_PM_OPS,
899*4882a593Smuzhiyun 	},
900*4882a593Smuzhiyun 	.probe		= max3100_probe,
901*4882a593Smuzhiyun 	.remove		= max3100_remove,
902*4882a593Smuzhiyun };
903*4882a593Smuzhiyun 
904*4882a593Smuzhiyun module_spi_driver(max3100_driver);
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun MODULE_DESCRIPTION("MAX3100 driver");
907*4882a593Smuzhiyun MODULE_AUTHOR("Christian Pellegrin <chripell@evolware.org>");
908*4882a593Smuzhiyun MODULE_LICENSE("GPL");
909*4882a593Smuzhiyun MODULE_ALIAS("spi:max3100");
910