1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2020 NXP
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/module.h>
7*4882a593Smuzhiyun #include <linux/ioport.h>
8*4882a593Smuzhiyun #include <linux/init.h>
9*4882a593Smuzhiyun #include <linux/serial_core.h>
10*4882a593Smuzhiyun #include <linux/serial.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define URTX0 0x40 /* Transmitter Register */
16*4882a593Smuzhiyun #define UTS_TXFULL (1<<4) /* TxFIFO full */
17*4882a593Smuzhiyun #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
18*4882a593Smuzhiyun
imx_uart_console_early_putchar(struct uart_port * port,int ch)19*4882a593Smuzhiyun static void imx_uart_console_early_putchar(struct uart_port *port, int ch)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
22*4882a593Smuzhiyun cpu_relax();
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun writel_relaxed(ch, port->membase + URTX0);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
imx_uart_console_early_write(struct console * con,const char * s,unsigned count)27*4882a593Smuzhiyun static void imx_uart_console_early_write(struct console *con, const char *s,
28*4882a593Smuzhiyun unsigned count)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct earlycon_device *dev = con->data;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun uart_console_write(&dev->port, s, count, imx_uart_console_early_putchar);
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static int __init
imx_console_early_setup(struct earlycon_device * dev,const char * opt)36*4882a593Smuzhiyun imx_console_early_setup(struct earlycon_device *dev, const char *opt)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun if (!dev->port.membase)
39*4882a593Smuzhiyun return -ENODEV;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun dev->con->write = imx_uart_console_early_write;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
46*4882a593Smuzhiyun OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun MODULE_AUTHOR("NXP");
49*4882a593Smuzhiyun MODULE_DESCRIPTION("IMX earlycon driver");
50*4882a593Smuzhiyun MODULE_LICENSE("GPL");
51